ath/ath5k/eeprom.h

0001 /*
0002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
0003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
0004  *
0005  * Permission to use, copy, modify, and distribute this software for any
0006  * purpose with or without fee is hereby granted, provided that the above
0007  * copyright notice and this permission notice appear in all copies.
0008  *
0009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0016  *
0017  */
0018
0019 /*
0020  * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
0021  */
0022 #define AR5K_EEPROM_PCIE_OFFSET     0x02    /* Contains offset to PCI-E infos */
0023 #define AR5K_EEPROM_PCIE_SERDES_SECTION 0x40    /* PCIE_OFFSET points here when
0024                          * SERDES infos are present */
0025 #define AR5K_EEPROM_MAGIC       0x003d  /* EEPROM Magic number */
0026 #define AR5K_EEPROM_MAGIC_VALUE     0x5aa5  /* Default - found on EEPROM */
0027
0028 #define AR5K_EEPROM_IS_HB63     0x000b  /* Talon detect */
0029
0030 #define AR5K_EEPROM_RFKILL      0x0f
0031 #define AR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c
0032 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
0033 #define AR5K_EEPROM_RFKILL_POLARITY 0x00000002
0034 #define AR5K_EEPROM_RFKILL_POLARITY_S   1
0035
0036 #define AR5K_EEPROM_REG_DOMAIN      0x00bf  /* EEPROM regdom */
0037
0038 /* FLASH(EEPROM) Defines for AR531X chips */
0039 #define AR5K_EEPROM_SIZE_LOWER      0x1b /* size info -- lower */
0040 #define AR5K_EEPROM_SIZE_UPPER      0x1c /* size info -- upper */
0041 #define AR5K_EEPROM_SIZE_UPPER_MASK 0xfff0
0042 #define AR5K_EEPROM_SIZE_UPPER_SHIFT    4
0043 #define AR5K_EEPROM_SIZE_ENDLOC_SHIFT   12
0044
0045 #define AR5K_EEPROM_CHECKSUM        0x00c0  /* EEPROM checksum */
0046 #define AR5K_EEPROM_INFO_BASE       0x00c0  /* EEPROM header */
0047 #define AR5K_EEPROM_INFO_MAX        (0x400 - AR5K_EEPROM_INFO_BASE)
0048 #define AR5K_EEPROM_INFO_CKSUM      0xffff
0049 #define AR5K_EEPROM_INFO(_n)        (AR5K_EEPROM_INFO_BASE + (_n))
0050
0051 #define AR5K_EEPROM_VERSION     AR5K_EEPROM_INFO(1) /* EEPROM Version */
0052 #define AR5K_EEPROM_VERSION_3_0     0x3000  /* No idea what's going on before this version */
0053 #define AR5K_EEPROM_VERSION_3_1     0x3001  /* ob/db values for 2GHz (ar5211_rfregs) */
0054 #define AR5K_EEPROM_VERSION_3_2     0x3002  /* different frequency representation (eeprom_bin2freq) */
0055 #define AR5K_EEPROM_VERSION_3_3     0x3003  /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
0056 #define AR5K_EEPROM_VERSION_3_4     0x3004  /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
0057 #define AR5K_EEPROM_VERSION_4_0     0x4000  /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
0058 #define AR5K_EEPROM_VERSION_4_1     0x4001  /* has ee_margin_tx_rx (eeprom_init) */
0059 #define AR5K_EEPROM_VERSION_4_2     0x4002  /* has ee_cck_ofdm_gain_delta (eeprom_init) */
0060 #define AR5K_EEPROM_VERSION_4_3     0x4003  /* power calibration changes */
0061 #define AR5K_EEPROM_VERSION_4_4     0x4004
0062 #define AR5K_EEPROM_VERSION_4_5     0x4005
0063 #define AR5K_EEPROM_VERSION_4_6     0x4006  /* has ee_scaled_cck_delta */
0064 #define AR5K_EEPROM_VERSION_4_7     0x3007  /* 4007 ? */
0065 #define AR5K_EEPROM_VERSION_4_9     0x4009  /* EAR futureproofing */
0066 #define AR5K_EEPROM_VERSION_5_0     0x5000  /* Has 2413 PDADC calibration etc */
0067 #define AR5K_EEPROM_VERSION_5_1     0x5001  /* Has capability values */
0068 #define AR5K_EEPROM_VERSION_5_3     0x5003  /* Has spur mitigation tables */
0069
0070 #define AR5K_EEPROM_MODE_11A        0
0071 #define AR5K_EEPROM_MODE_11B        1
0072 #define AR5K_EEPROM_MODE_11G        2
0073
0074 #define AR5K_EEPROM_HDR         AR5K_EEPROM_INFO(2) /* Header that contains the device caps */
0075 #define AR5K_EEPROM_HDR_11A(_v)     (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
0076 #define AR5K_EEPROM_HDR_11B(_v)     (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
0077 #define AR5K_EEPROM_HDR_11G(_v)     (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
0078 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)  (((_v) >> 3) & 0x1) /* Disable turbo for 2GHz */
0079 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)  (((_v) >> 4) & 0x7f)    /* Max turbo power for < 2W power consumption */
0080 #define AR5K_EEPROM_HDR_DEVICE(_v)  (((_v) >> 11) & 0x7)    /* Device type (1 Cardbus, 2 PCI, 3 MiniPCI, 4 AP) */
0081 #define AR5K_EEPROM_HDR_RFKILL(_v)  (((_v) >> 14) & 0x1)    /* Device has RFKill support */
0082 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)  (((_v) >> 15) & 0x1)    /* Disable turbo for 5GHz */
0083
0084 /* Newer EEPROMs are using a different offset */
0085 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
0086     (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
0087
0088 #define AR5K_EEPROM_ANT_GAIN(_v)    AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
0089 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)   ((s8)(((_v) >> 8) & 0xff))
0090 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)   ((s8)((_v) & 0xff))
0091
0092 /* Misc values available since EEPROM 4.0 */
0093 #define AR5K_EEPROM_MISC0       AR5K_EEPROM_INFO(4)
0094 #define AR5K_EEPROM_EARSTART(_v)    ((_v) & 0xfff)
0095 #define AR5K_EEPROM_HDR_XR2_DIS(_v) (((_v) >> 12) & 0x1)
0096 #define AR5K_EEPROM_HDR_XR5_DIS(_v) (((_v) >> 13) & 0x1)
0097 #define AR5K_EEPROM_EEMAP(_v)       (((_v) >> 14) & 0x3)
0098
0099 #define AR5K_EEPROM_MISC1           AR5K_EEPROM_INFO(5)
0100 #define AR5K_EEPROM_TARGET_PWRSTART(_v)     ((_v) & 0xfff)
0101 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v)     (((_v) >> 14) & 0x1)    /* has 32KHz crystal for sleep mode */
0102 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v) (((_v) >> 15) & 0x1)
0103
0104 #define AR5K_EEPROM_MISC2           AR5K_EEPROM_INFO(6)
0105 #define AR5K_EEPROM_EEP_FILE_VERSION(_v)    (((_v) >> 8) & 0xff)
0106 #define AR5K_EEPROM_EAR_FILE_VERSION(_v)    ((_v) & 0xff)
0107
0108 #define AR5K_EEPROM_MISC3       AR5K_EEPROM_INFO(7)
0109 #define AR5K_EEPROM_ART_BUILD_NUM(_v)   (((_v) >> 10) & 0x3f)
0110 #define AR5K_EEPROM_EAR_FILE_ID(_v) ((_v) & 0xff)
0111
0112 #define AR5K_EEPROM_MISC4       AR5K_EEPROM_INFO(8)
0113 #define AR5K_EEPROM_CAL_DATA_START(_v)  (((_v) >> 4) & 0xfff)
0114 #define AR5K_EEPROM_MASK_R0(_v)     (((_v) >> 2) & 0x3) /* modes supported by radio 0 (bit 1: G, bit 2: A) */
0115 #define AR5K_EEPROM_MASK_R1(_v)     ((_v) & 0x3)        /* modes supported by radio 1 (bit 1: G, bit 2: A) */
0116
0117 #define AR5K_EEPROM_MISC5       AR5K_EEPROM_INFO(9)
0118 #define AR5K_EEPROM_COMP_DIS(_v)    ((_v) & 0x1)        /* disable compression */
0119 #define AR5K_EEPROM_AES_DIS(_v)     (((_v) >> 1) & 0x1) /* disable AES */
0120 #define AR5K_EEPROM_FF_DIS(_v)      (((_v) >> 2) & 0x1) /* disable fast frames */
0121 #define AR5K_EEPROM_BURST_DIS(_v)   (((_v) >> 3) & 0x1) /* disable bursting */
0122 #define AR5K_EEPROM_MAX_QCU(_v)     (((_v) >> 4) & 0xf) /* max number of QCUs. defaults to 10 */
0123 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v)   (((_v) >> 8) & 0x1) /* enable heavy clipping */
0124 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v)  (((_v) >> 12) & 0xf)    /* key cache size. defaults to 128 */
0125
0126 #define AR5K_EEPROM_MISC6       AR5K_EEPROM_INFO(10)
0127 #define AR5K_EEPROM_TX_CHAIN_DIS    ((_v) & 0x7)        /* MIMO chains disabled for TX bitmask */
0128 #define AR5K_EEPROM_RX_CHAIN_DIS    (((_v) >> 3) & 0x7) /* MIMO chains disabled for RX bitmask */
0129 #define AR5K_EEPROM_FCC_MID_EN      (((_v) >> 6) & 0x1) /* 5.47-5.7GHz supported */
0130 #define AR5K_EEPROM_JAP_U1EVEN_EN   (((_v) >> 7) & 0x1) /* Japan UNII1 band (5.15-5.25GHz) on even channels (5180, 5200, 5220, 5240) supported */
0131 #define AR5K_EEPROM_JAP_U2_EN       (((_v) >> 8) & 0x1) /* Japan UNII2 band (5.25-5.35GHz) supported */
0132 #define AR5K_EEPROM_JAP_MID_EN      (((_v) >> 9) & 0x1) /* Japan band from 5.47-5.7GHz supported */
0133 #define AR5K_EEPROM_JAP_U1ODD_EN    (((_v) >> 10) & 0x1)    /* Japan UNII2 band (5.15-5.25GHz) on odd channels (5170, 5190, 5210, 5230) supported */
0134 #define AR5K_EEPROM_JAP_11A_NEW_EN  (((_v) >> 11) & 0x1)    /* Japan A mode enabled (using even channels) */
0135
0136 /* calibration settings */
0137 #define AR5K_EEPROM_MODES_11A(_v)   AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
0138 #define AR5K_EEPROM_MODES_11B(_v)   AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
0139 #define AR5K_EEPROM_MODES_11G(_v)   AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
0140 #define AR5K_EEPROM_CTL(_v)     AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128) /* Conformance test limits */
0141 #define AR5K_EEPROM_GROUPS_START(_v)    AR5K_EEPROM_OFF(_v, 0x0100, 0x0150) /* Start of Groups */
0142 #define AR5K_EEPROM_GROUP1_OFFSET   0x0
0143 #define AR5K_EEPROM_GROUP2_OFFSET   0x5
0144 #define AR5K_EEPROM_GROUP3_OFFSET   0x37
0145 #define AR5K_EEPROM_GROUP4_OFFSET   0x46
0146 #define AR5K_EEPROM_GROUP5_OFFSET   0x55
0147 #define AR5K_EEPROM_GROUP6_OFFSET   0x65
0148 #define AR5K_EEPROM_GROUP7_OFFSET   0x69
0149 #define AR5K_EEPROM_GROUP8_OFFSET   0x6f
0150
0151 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)  AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
0152                                 AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
0153 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)  AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
0154                                 AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
0155 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)  AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
0156                                 AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
0157
0158 /* [3.1 - 3.3] */
0159 #define AR5K_EEPROM_OBDB0_2GHZ      0x00ec
0160 #define AR5K_EEPROM_OBDB1_2GHZ      0x00ed
0161
0162 #define AR5K_EEPROM_PROTECT     0x003f  /* EEPROM protect status */
0163 #define AR5K_EEPROM_PROTECT_RD_0_31 0x0001  /* Read protection bit for offsets 0x0 - 0x1f */
0164 #define AR5K_EEPROM_PROTECT_WR_0_31 0x0002  /* Write protection bit for offsets 0x0 - 0x1f */
0165 #define AR5K_EEPROM_PROTECT_RD_32_63    0x0004  /* 0x20 - 0x3f */
0166 #define AR5K_EEPROM_PROTECT_WR_32_63    0x0008
0167 #define AR5K_EEPROM_PROTECT_RD_64_127   0x0010  /* 0x40 - 0x7f */
0168 #define AR5K_EEPROM_PROTECT_WR_64_127   0x0020
0169 #define AR5K_EEPROM_PROTECT_RD_128_191  0x0040  /* 0x80 - 0xbf (regdom) */
0170 #define AR5K_EEPROM_PROTECT_WR_128_191  0x0080
0171 #define AR5K_EEPROM_PROTECT_RD_192_207  0x0100  /* 0xc0 - 0xcf */
0172 #define AR5K_EEPROM_PROTECT_WR_192_207  0x0200
0173 #define AR5K_EEPROM_PROTECT_RD_208_223  0x0400  /* 0xd0 - 0xdf */
0174 #define AR5K_EEPROM_PROTECT_WR_208_223  0x0800
0175 #define AR5K_EEPROM_PROTECT_RD_224_239  0x1000  /* 0xe0 - 0xef */
0176 #define AR5K_EEPROM_PROTECT_WR_224_239  0x2000
0177 #define AR5K_EEPROM_PROTECT_RD_240_255  0x4000  /* 0xf0 - 0xff */
0178 #define AR5K_EEPROM_PROTECT_WR_240_255  0x8000
0179
0180 /* Some EEPROM defines */
0181 #define AR5K_EEPROM_EEP_SCALE       100
0182 #define AR5K_EEPROM_EEP_DELTA       10
0183 #define AR5K_EEPROM_N_MODES     3
0184 #define AR5K_EEPROM_N_5GHZ_CHAN     10
0185 #define AR5K_EEPROM_N_5GHZ_RATE_CHAN    8
0186 #define AR5K_EEPROM_N_2GHZ_CHAN     3
0187 #define AR5K_EEPROM_N_2GHZ_CHAN_2413    4
0188 #define AR5K_EEPROM_N_2GHZ_CHAN_MAX 4
0189 #define AR5K_EEPROM_MAX_CHAN        10
0190 #define AR5K_EEPROM_N_PWR_POINTS_5111   11
0191 #define AR5K_EEPROM_N_PCDAC     11
0192 #define AR5K_EEPROM_N_PHASE_CAL     5
0193 #define AR5K_EEPROM_N_TEST_FREQ     8
0194 #define AR5K_EEPROM_N_EDGES     8
0195 #define AR5K_EEPROM_N_INTERCEPTS    11
0196 #define AR5K_EEPROM_FREQ_M(_v)      AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
0197 #define AR5K_EEPROM_PCDAC_M     0x3f
0198 #define AR5K_EEPROM_PCDAC_START     1
0199 #define AR5K_EEPROM_PCDAC_STOP      63
0200 #define AR5K_EEPROM_PCDAC_STEP      1
0201 #define AR5K_EEPROM_NON_EDGE_M      0x40
0202 #define AR5K_EEPROM_CHANNEL_POWER   8
0203 #define AR5K_EEPROM_N_OBDB      4
0204 #define AR5K_EEPROM_OBDB_DIS        0xffff
0205 #define AR5K_EEPROM_CHANNEL_DIS     0xff
0206 #define AR5K_EEPROM_SCALE_OC_DELTA(_x)  (((_x) * 2) / 10)
0207 #define AR5K_EEPROM_N_CTLS(_v)      AR5K_EEPROM_OFF(_v, 16, 32)
0208 #define AR5K_EEPROM_MAX_CTLS        32
0209 #define AR5K_EEPROM_N_PD_CURVES     4
0210 #define AR5K_EEPROM_N_XPD0_POINTS   4
0211 #define AR5K_EEPROM_N_XPD3_POINTS   3
0212 #define AR5K_EEPROM_N_PD_GAINS      4
0213 #define AR5K_EEPROM_N_PD_POINTS     5
0214 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
0215 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
0216 #define AR5K_EEPROM_POWER_M     0x3f
0217 #define AR5K_EEPROM_POWER_MIN       0
0218 #define AR5K_EEPROM_POWER_MAX       3150
0219 #define AR5K_EEPROM_POWER_STEP      50
0220 #define AR5K_EEPROM_POWER_TABLE_SIZE    64
0221 #define AR5K_EEPROM_N_POWER_LOC_11B 4
0222 #define AR5K_EEPROM_N_POWER_LOC_11G 6
0223 #define AR5K_EEPROM_I_GAIN      10
0224 #define AR5K_EEPROM_CCK_OFDM_DELTA  15
0225 #define AR5K_EEPROM_N_IQ_CAL        2
0226 /* 5GHz/2GHz */
0227 enum ath5k_eeprom_freq_bands {
0228     AR5K_EEPROM_BAND_5GHZ = 0,
0229     AR5K_EEPROM_BAND_2GHZ = 1,
0230     AR5K_EEPROM_N_FREQ_BANDS,
0231 };
0232 /* Spur chans per freq band */
0233 #define AR5K_EEPROM_N_SPUR_CHANS    5
0234 /* fbin value for chan 2464 x2 */
0235 #define AR5K_EEPROM_5413_SPUR_CHAN_1    1640
0236 /* fbin value for chan 2420 x2 */
0237 #define AR5K_EEPROM_5413_SPUR_CHAN_2    1200
0238 #define AR5K_EEPROM_SPUR_CHAN_MASK  0x3FFF
0239 #define AR5K_EEPROM_NO_SPUR     0x8000
0240 #define AR5K_SPUR_CHAN_WIDTH            87
0241 #define AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz   3125
0242 #define AR5K_SPUR_SYMBOL_WIDTH_TURBO_100Hz  6250
0243
0244 #define AR5K_EEPROM_READ(_o, _v) do {           \
0245     if (!ath5k_hw_nvram_read(ah, (_o), &(_v)))  \
0246         return -EIO;                \
0247 } while (0)
0248
0249 #define AR5K_EEPROM_READ_HDR(_o, _v)                    \
0250     AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v);    \
0251
0252 enum ath5k_ant_table {
0253     AR5K_ANT_CTL        = 0,    /* Idle switch table settings */
0254     AR5K_ANT_SWTABLE_A  = 1,    /* Switch table for antenna A */
0255     AR5K_ANT_SWTABLE_B  = 2,    /* Switch table for antenna B */
0256     AR5K_ANT_MAX,
0257 };
0258
0259 enum ath5k_ctl_mode {
0260     AR5K_CTL_11A = 0,
0261     AR5K_CTL_11B = 1,
0262     AR5K_CTL_11G = 2,
0263     AR5K_CTL_TURBO = 3,
0264     AR5K_CTL_TURBOG = 4,
0265     AR5K_CTL_2GHT20 = 5,
0266     AR5K_CTL_5GHT20 = 6,
0267     AR5K_CTL_2GHT40 = 7,
0268     AR5K_CTL_5GHT40 = 8,
0269     AR5K_CTL_MODE_M = 15,
0270 };
0271
0272 /* Per channel calibration data, used for power table setup */
0273 struct ath5k_chan_pcal_info_rf5111 {
0274     /* Power levels in half dBm units
0275      * for one power curve. */
0276     u8 pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
0277     /* PCDAC table steps
0278      * for the above values */
0279     u8 pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
0280     /* Starting PCDAC step */
0281     u8 pcdac_min;
0282     /* Final PCDAC step */
0283     u8 pcdac_max;
0284 };
0285
0286 struct ath5k_chan_pcal_info_rf5112 {
0287     /* Power levels in quarter dBm units
0288      * for lower (0) and higher (3)
0289      * level curves in 0.25dB units */
0290     s8 pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
0291     s8 pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
0292     /* PCDAC table steps
0293      * for the above values */
0294     u8 pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
0295     u8 pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
0296 };
0297
0298 struct ath5k_chan_pcal_info_rf2413 {
0299     /* Starting pwr/pddac values */
0300     s8 pwr_i[AR5K_EEPROM_N_PD_GAINS];
0301     u8 pddac_i[AR5K_EEPROM_N_PD_GAINS];
0302     /* (pwr,pddac) points
0303      * power levels in 0.5dB units */
0304     s8 pwr[AR5K_EEPROM_N_PD_GAINS]
0305         [AR5K_EEPROM_N_PD_POINTS];
0306     u8 pddac[AR5K_EEPROM_N_PD_GAINS]
0307         [AR5K_EEPROM_N_PD_POINTS];
0308 };
0309
0310 enum ath5k_powertable_type {
0311     AR5K_PWRTABLE_PWR_TO_PCDAC = 0,
0312     AR5K_PWRTABLE_LINEAR_PCDAC = 1,
0313     AR5K_PWRTABLE_PWR_TO_PDADC = 2,
0314 };
0315
0316 struct ath5k_pdgain_info {
0317     u8 pd_points;
0318     u8 *pd_step;
0319     /* Power values are in
0320      * 0.25dB units */
0321     s16 *pd_pwr;
0322 };
0323
0324 struct ath5k_chan_pcal_info {
0325     /* Frequency */
0326     u16 freq;
0327     /* Tx power boundaries */
0328     s16 max_pwr;
0329     s16 min_pwr;
0330     union {
0331         struct ath5k_chan_pcal_info_rf5111 rf5111_info;
0332         struct ath5k_chan_pcal_info_rf5112 rf5112_info;
0333         struct ath5k_chan_pcal_info_rf2413 rf2413_info;
0334     };
0335     /* Raw values used by phy code
0336      * Curves are stored in order from lower
0337      * gain to higher gain (max txpower -> min txpower) */
0338     struct ath5k_pdgain_info *pd_curves;
0339 };
0340
0341 /* Per rate calibration data for each mode,
0342  * used for rate power table setup.
0343  * Note: Values in 0.5dB units */
0344 struct ath5k_rate_pcal_info {
0345     u16 freq; /* Frequency */
0346     /* Power level for 6-24Mbit/s rates or
0347      * 1Mb rate */
0348     u16 target_power_6to24;
0349     /* Power level for 36Mbit rate or
0350      * 2Mb rate */
0351     u16 target_power_36;
0352     /* Power level for 48Mbit rate or
0353      * 5.5Mbit rate */
0354     u16 target_power_48;
0355     /* Power level for 54Mbit rate or
0356      * 11Mbit rate */
0357     u16 target_power_54;
0358 };
0359
0360 /* Power edges for conformance test limits */
0361 struct ath5k_edge_power {
0362     u16 freq;
0363     u16 edge; /* in half dBm */
0364     bool flag;
0365 };
0366
0367 /**
0368  * struct ath5k_eeprom_info - EEPROM calibration data
0369  *
0370  * @ee_regdomain: ath/regd.c takes care of COUNTRY_ERD and WORLDWIDE_ROAMING
0371  *  flags
0372  * @ee_ant_gain: Antenna gain in 0.5dB steps signed [5211 only?]
0373  * @ee_cck_ofdm_gain_delta: difference in gainF to output the same power for
0374  *  OFDM and CCK packets
0375  * @ee_cck_ofdm_power_delta: power difference between OFDM (6Mbps) and CCK
0376  *  (11Mbps) rate in G mode. 0.1dB steps
0377  * @ee_scaled_cck_delta: for Japan Channel 14: 0.1dB resolution
0378  *
0379  * @ee_i_cal: Initial I coefficient to correct I/Q mismatch in the receive path
0380  * @ee_q_cal: Initial Q coefficient to correct I/Q mismatch in the receive path
0381  * @ee_fixed_bias: use ee_ob and ee_db settings or use automatic control
0382  * @ee_switch_settling: RX/TX Switch settling time
0383  * @ee_atn_tx_rx: Difference in attenuation between TX and RX in 1dB steps
0384  * @ee_ant_control: Antenna Control Settings
0385  * @ee_ob: Bias current for Output stage of PA
0386  *  B/G mode: Index [0] is used for AR2112/5112, otherwise [1]
0387  *  A mode: [0] 5.15-5.25 [1] 5.25-5.50 [2] 5.50-5.70 [3] 5.70-5.85 GHz
0388  * @ee_db: Bias current for Output stage of PA. see @ee_ob
0389  * @ee_tx_end2xlna_enable: Time difference from when BB finishes sending a frame
0390  *  to when the external LNA is activated
0391  * @ee_tx_end2xpa_disable: Time difference from when BB finishes sending a frame
0392  *  to when the external PA switch is deactivated
0393  * @ee_tx_frm2xpa_enable: Time difference from when MAC sends frame to when
0394  *  external PA switch is activated
0395  * @ee_thr_62: Clear Channel Assessment (CCA) sensitivity
0396  *  (IEEE802.11a section 17.3.10.5 )
0397  * @ee_xlna_gain: Total gain of the LNA (information only)
0398  * @ee_xpd: Use external (1) or internal power detector
0399  * @ee_x_gain: Gain for external power detector output (differences in EEMAP
0400  *  versions!)
0401  * @ee_i_gain: Initial gain value after reset
0402  * @ee_margin_tx_rx: Margin in dB when final attenuation stage should be used
0403  *
0404  * @ee_false_detect: Backoff in Sensitivity (dB) on channels with spur signals
0405  * @ee_noise_floor_thr: Noise floor threshold in 1dB steps
0406  * @ee_adc_desired_size: Desired amplitude for ADC, used by AGC; in 0.5 dB steps
0407  * @ee_pga_desired_size: Desired output of PGA (for BB gain) in 0.5 dB steps
0408  * @ee_pd_gain_overlap: PD ADC curves need to overlap in 0.5dB steps (ee_map>=2)
0409  */
0410 struct ath5k_eeprom_info {
0411
0412     /* Header information */
0413     u16 ee_magic;
0414     u16 ee_protect;
0415     u16 ee_regdomain;
0416     u16 ee_version;
0417     u16 ee_header;
0418     u16 ee_ant_gain;
0419     u8  ee_rfkill_pin;
0420     bool    ee_rfkill_pol;
0421     bool    ee_is_hb63;
0422     bool    ee_serdes;
0423     u16 ee_misc0;
0424     u16 ee_misc1;
0425     u16 ee_misc2;
0426     u16 ee_misc3;
0427     u16 ee_misc4;
0428     u16 ee_misc5;
0429     u16 ee_misc6;
0430     u16 ee_cck_ofdm_gain_delta;
0431     u16 ee_cck_ofdm_power_delta;
0432     u16 ee_scaled_cck_delta;
0433
0434     /* RF Calibration settings (reset, rfregs) */
0435     u16 ee_i_cal[AR5K_EEPROM_N_MODES];
0436     u16 ee_q_cal[AR5K_EEPROM_N_MODES];
0437     u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
0438     u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
0439     u16 ee_xr_power[AR5K_EEPROM_N_MODES];
0440     u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
0441     u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
0442     u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
0443     u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
0444     u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
0445     u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
0446     u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
0447     u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
0448     u16 ee_thr_62[AR5K_EEPROM_N_MODES];
0449     u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
0450     u16 ee_xpd[AR5K_EEPROM_N_MODES];
0451     u16 ee_x_gain[AR5K_EEPROM_N_MODES];
0452     u16 ee_i_gain[AR5K_EEPROM_N_MODES];
0453     u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
0454     u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
0455     u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
0456     u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
0457
0458     /* Power calibration data */
0459     u16 ee_false_detect[AR5K_EEPROM_N_MODES];
0460
0461     /* Number of pd gain curves per mode */
0462     u8  ee_pd_gains[AR5K_EEPROM_N_MODES];
0463     /* Back mapping pdcurve number -> pdcurve index in pd->pd_curves */
0464     u8  ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
0465
0466     u8  ee_n_piers[AR5K_EEPROM_N_MODES];
0467     struct ath5k_chan_pcal_info ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
0468     struct ath5k_chan_pcal_info ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
0469     struct ath5k_chan_pcal_info ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
0470
0471     /* Per rate target power levels */
0472     u8  ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
0473     struct ath5k_rate_pcal_info ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
0474     struct ath5k_rate_pcal_info ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
0475     struct ath5k_rate_pcal_info ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN_MAX];
0476
0477     /* Conformance test limits (Unused) */
0478     u8  ee_ctls;
0479     u8  ee_ctl[AR5K_EEPROM_MAX_CTLS];
0480     struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
0481
0482     /* Noise Floor Calibration settings */
0483     s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
0484     s8  ee_adc_desired_size[AR5K_EEPROM_N_MODES];
0485     s8  ee_pga_desired_size[AR5K_EEPROM_N_MODES];
0486     s8  ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
0487     s8  ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
0488     s8  ee_pd_gain_overlap;
0489
0490     /* Spur mitigation data (fbin values for spur channels) */
0491     u16 ee_spur_chans[AR5K_EEPROM_N_SPUR_CHANS][AR5K_EEPROM_N_FREQ_BANDS];
0492
0493     /* Antenna raw switch tables */
0494     u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
0495 };