ath/ath5k/desc.h

0001 /*
0002  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
0003  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
0004  *
0005  * Permission to use, copy, modify, and distribute this software for any
0006  * purpose with or without fee is hereby granted, provided that the above
0007  * copyright notice and this permission notice appear in all copies.
0008  *
0009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0016  *
0017  */
0018
0019 /*
0020  * RX/TX descriptor structures
0021  */
0022
0023 /**
0024  * struct ath5k_hw_rx_ctl - Common hardware RX control descriptor
0025  * @rx_control_0: RX control word 0
0026  * @rx_control_1: RX control word 1
0027  */
0028 struct ath5k_hw_rx_ctl {
0029     u32 rx_control_0;
0030     u32 rx_control_1;
0031 } __packed __aligned(4);
0032
0033 /* RX control word 1 fields/flags */
0034 #define AR5K_DESC_RX_CTL1_BUF_LEN       0x00000fff /* data buffer length */
0035 #define AR5K_DESC_RX_CTL1_INTREQ        0x00002000 /* RX interrupt request */
0036
0037 /**
0038  * struct ath5k_hw_rx_status - Common hardware RX status descriptor
0039  * @rx_status_0: RX status word 0
0040  * @rx_status_1: RX status word 1
0041  *
0042  * 5210, 5211 and 5212 differ only in the fields and flags defined below
0043  */
0044 struct ath5k_hw_rx_status {
0045     u32 rx_status_0;
0046     u32 rx_status_1;
0047 } __packed __aligned(4);
0048
0049 /* 5210/5211 */
0050 /* RX status word 0 fields/flags */
0051 #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN      0x00000fff /* RX data length */
0052 #define AR5K_5210_RX_DESC_STATUS0_MORE          0x00001000 /* more desc for this frame */
0053 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210  0x00004000 /* [5210] receive on ant 1 */
0054 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE      0x00078000 /* reception rate */
0055 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S    15
0056 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL    0x07f80000 /* rssi */
0057 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S  19
0058 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211  0x38000000 /* [5211] receive antenna */
0059 #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211_S    27
0060
0061 /* RX status word 1 fields/flags */
0062 #define AR5K_5210_RX_DESC_STATUS1_DONE          0x00000001 /* descriptor complete */
0063 #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK  0x00000002 /* reception success */
0064 #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR     0x00000004 /* CRC error */
0065 #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210 0x00000008 /* [5210] FIFO overrun */
0066 #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 /* decryption CRC failure */
0067 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR     0x000000e0 /* PHY error */
0068 #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S       5
0069 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID   0x00000100 /* key index valid */
0070 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX     0x00007e00 /* decryption key index */
0071 #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S       9
0072 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 /* 13 bit of TSF */
0073 #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S   15
0074 #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS    0x10000000 /* key cache miss */
0075
0076 /* 5212 */
0077 /* RX status word 0 fields/flags */
0078 #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN      0x00000fff /* RX data length */
0079 #define AR5K_5212_RX_DESC_STATUS0_MORE          0x00001000 /* more desc for this frame */
0080 #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR  0x00002000 /* decompression CRC error */
0081 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE      0x000f8000 /* reception rate */
0082 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S    15
0083 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL    0x0ff00000 /* rssi */
0084 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S  20
0085 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA   0xf0000000 /* receive antenna */
0086 #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
0087
0088 /* RX status word 1 fields/flags */
0089 #define AR5K_5212_RX_DESC_STATUS1_DONE          0x00000001 /* descriptor complete */
0090 #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK  0x00000002 /* frame reception success */
0091 #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR     0x00000004 /* CRC error */
0092 #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 /* decryption CRC failure */
0093 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR     0x00000010 /* PHY error */
0094 #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR     0x00000020 /* MIC decrypt error */
0095 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID   0x00000100 /* key index valid */
0096 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX     0x0000fe00 /* decryption key index */
0097 #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S       9
0098 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 /* first 15bit of the TSF */
0099 #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S   16
0100 #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS    0x80000000 /* key cache miss */
0101 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE    0x0000ff00 /* phy error code overlays key index and valid fields */
0102 #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE_S  8
0103
0104 /**
0105  * enum ath5k_phy_error_code - PHY Error codes
0106  * @AR5K_RX_PHY_ERROR_UNDERRUN: Transmit underrun, [5210] No error
0107  * @AR5K_RX_PHY_ERROR_TIMING: Timing error
0108  * @AR5K_RX_PHY_ERROR_PARITY: Illegal parity
0109  * @AR5K_RX_PHY_ERROR_RATE: Illegal rate
0110  * @AR5K_RX_PHY_ERROR_LENGTH: Illegal length
0111  * @AR5K_RX_PHY_ERROR_RADAR: Radar detect, [5210] 64 QAM rate
0112  * @AR5K_RX_PHY_ERROR_SERVICE: Illegal service
0113  * @AR5K_RX_PHY_ERROR_TOR: Transmit override receive
0114  * @AR5K_RX_PHY_ERROR_OFDM_TIMING: OFDM Timing error [5212+]
0115  * @AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY: OFDM Signal parity error [5212+]
0116  * @AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL: OFDM Illegal rate [5212+]
0117  * @AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL: OFDM Illegal length [5212+]
0118  * @AR5K_RX_PHY_ERROR_OFDM_POWER_DROP: OFDM Power drop [5212+]
0119  * @AR5K_RX_PHY_ERROR_OFDM_SERVICE: OFDM Service (?) [5212+]
0120  * @AR5K_RX_PHY_ERROR_OFDM_RESTART: OFDM Restart (?) [5212+]
0121  * @AR5K_RX_PHY_ERROR_CCK_TIMING: CCK Timing error [5212+]
0122  * @AR5K_RX_PHY_ERROR_CCK_HEADER_CRC: Header CRC error [5212+]
0123  * @AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL: Illegal rate [5212+]
0124  * @AR5K_RX_PHY_ERROR_CCK_SERVICE: CCK Service (?) [5212+]
0125  * @AR5K_RX_PHY_ERROR_CCK_RESTART: CCK Restart (?) [5212+]
0126  */
0127 enum ath5k_phy_error_code {
0128     AR5K_RX_PHY_ERROR_UNDERRUN      = 0,
0129     AR5K_RX_PHY_ERROR_TIMING        = 1,
0130     AR5K_RX_PHY_ERROR_PARITY        = 2,
0131     AR5K_RX_PHY_ERROR_RATE          = 3,
0132     AR5K_RX_PHY_ERROR_LENGTH        = 4,
0133     AR5K_RX_PHY_ERROR_RADAR         = 5,
0134     AR5K_RX_PHY_ERROR_SERVICE       = 6,
0135     AR5K_RX_PHY_ERROR_TOR           = 7,
0136     AR5K_RX_PHY_ERROR_OFDM_TIMING       = 17,
0137     AR5K_RX_PHY_ERROR_OFDM_SIGNAL_PARITY    = 18,
0138     AR5K_RX_PHY_ERROR_OFDM_RATE_ILLEGAL = 19,
0139     AR5K_RX_PHY_ERROR_OFDM_LENGTH_ILLEGAL   = 20,
0140     AR5K_RX_PHY_ERROR_OFDM_POWER_DROP   = 21,
0141     AR5K_RX_PHY_ERROR_OFDM_SERVICE      = 22,
0142     AR5K_RX_PHY_ERROR_OFDM_RESTART      = 23,
0143     AR5K_RX_PHY_ERROR_CCK_TIMING        = 25,
0144     AR5K_RX_PHY_ERROR_CCK_HEADER_CRC    = 26,
0145     AR5K_RX_PHY_ERROR_CCK_RATE_ILLEGAL  = 27,
0146     AR5K_RX_PHY_ERROR_CCK_SERVICE       = 30,
0147     AR5K_RX_PHY_ERROR_CCK_RESTART       = 31,
0148 };
0149
0150 /**
0151  * struct ath5k_hw_2w_tx_ctl  - 5210/5211 hardware 2-word TX control descriptor
0152  * @tx_control_0: TX control word 0
0153  * @tx_control_1: TX control word 1
0154  */
0155 struct ath5k_hw_2w_tx_ctl {
0156     u32 tx_control_0;
0157     u32 tx_control_1;
0158 } __packed __aligned(4);
0159
0160 /* TX control word 0 fields/flags */
0161 #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN      0x00000fff /* frame length */
0162 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210    0x0003f000 /* [5210] header length */
0163 #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210_S  12
0164 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE      0x003c0000 /* tx rate */
0165 #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S    18
0166 #define AR5K_2W_TX_DESC_CTL0_RTSENA     0x00400000 /* RTS/CTS enable */
0167 #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET_5210   0x00800000 /* [5210] long packet */
0168 #define AR5K_2W_TX_DESC_CTL0_VEOL_5211      0x00800000 /* [5211] virtual end-of-list */
0169 #define AR5K_2W_TX_DESC_CTL0_CLRDMASK       0x01000000 /* clear destination mask */
0170 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 /* [5210] antenna selection */
0171 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 /* [5211] antenna selection */
0172 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT          \
0173         (ah->ah_version == AR5K_AR5210 ?        \
0174         AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 :   \
0175         AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
0176 #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S    25
0177 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210    0x1c000000 /* [5210] frame type */
0178 #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210_S  26
0179 #define AR5K_2W_TX_DESC_CTL0_INTREQ     0x20000000 /* TX interrupt request */
0180 #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID  0x40000000 /* key is valid */
0181
0182 /* TX control word 1 fields/flags */
0183 #define AR5K_2W_TX_DESC_CTL1_BUF_LEN        0x00000fff /* data buffer length */
0184 #define AR5K_2W_TX_DESC_CTL1_MORE       0x00001000 /* more desc for this frame */
0185 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210   0x0007e000 /* [5210] key table index */
0186 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211   0x000fe000 /* [5211] key table index */
0187 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX                \
0188             (ah->ah_version == AR5K_AR5210 ?        \
0189             AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5210 :     \
0190             AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_5211)
0191 #define AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX_S  13
0192 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211    0x00700000 /* [5211] frame type */
0193 #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211_S  20
0194 #define AR5K_2W_TX_DESC_CTL1_NOACK_5211     0x00800000 /* [5211] no ACK */
0195 #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210  0xfff80000 /* [5210] lower 13 bit of duration */
0196
0197 /* Frame types */
0198 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL   0
0199 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 1
0200 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL   2
0201 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 3
0202 #define AR5K_AR5211_TX_DESC_FRAME_TYPE_BEACON   3
0203 #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 4
0204 #define AR5K_AR5211_TX_DESC_FRAME_TYPE_PRESP    4
0205
0206 /**
0207  * struct ath5k_hw_4w_tx_ctl - 5212 hardware 4-word TX control descriptor
0208  * @tx_control_0: TX control word 0
0209  * @tx_control_1: TX control word 1
0210  * @tx_control_2: TX control word 2
0211  * @tx_control_3: TX control word 3
0212  */
0213 struct ath5k_hw_4w_tx_ctl {
0214     u32 tx_control_0;
0215     u32 tx_control_1;
0216     u32 tx_control_2;
0217     u32 tx_control_3;
0218 } __packed __aligned(4);
0219
0220 /* TX control word 0 fields/flags */
0221 #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN      0x00000fff /* frame length */
0222 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER     0x003f0000 /* transmit power */
0223 #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S   16
0224 #define AR5K_4W_TX_DESC_CTL0_RTSENA     0x00400000 /* RTS/CTS enable */
0225 #define AR5K_4W_TX_DESC_CTL0_VEOL       0x00800000 /* virtual end-of-list */
0226 #define AR5K_4W_TX_DESC_CTL0_CLRDMASK       0x01000000 /* clear destination mask */
0227 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT  0x1e000000 /* TX antenna selection */
0228 #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S    25
0229 #define AR5K_4W_TX_DESC_CTL0_INTREQ     0x20000000 /* TX interrupt request */
0230 #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID  0x40000000 /* destination index valid */
0231 #define AR5K_4W_TX_DESC_CTL0_CTSENA     0x80000000 /* precede frame with CTS */
0232
0233 /* TX control word 1 fields/flags */
0234 #define AR5K_4W_TX_DESC_CTL1_BUF_LEN        0x00000fff /* data buffer length */
0235 #define AR5K_4W_TX_DESC_CTL1_MORE       0x00001000 /* more desc for this frame */
0236 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX    0x000fe000 /* destination table index */
0237 #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX_S  13
0238 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE     0x00f00000 /* frame type */
0239 #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S   20
0240 #define AR5K_4W_TX_DESC_CTL1_NOACK      0x01000000 /* no ACK */
0241 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC      0x06000000 /* compression processing */
0242 #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S    25
0243 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN    0x18000000 /* length of frame IV */
0244 #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S  27
0245 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN   0x60000000 /* length of frame ICV */
0246 #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29
0247
0248 /* TX control word 2 fields/flags */
0249 #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION   0x00007fff /* RTS/CTS duration */
0250 #define AR5K_4W_TX_DESC_CTL2_DURATION_UPD_EN    0x00008000 /* frame duration update */
0251 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0    0x000f0000 /* series 0 max attempts */
0252 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S  16
0253 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1    0x00f00000 /* series 1 max attempts */
0254 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S  20
0255 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2    0x0f000000 /* series 2 max attempts */
0256 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S  24
0257 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3    0xf0000000 /* series 3 max attempts */
0258 #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S  28
0259
0260 /* TX control word 3 fields/flags */
0261 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0     0x0000001f /* series 0 tx rate */
0262 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1     0x000003e0 /* series 1 tx rate */
0263 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S   5
0264 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2     0x00007c00 /* series 2 tx rate */
0265 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S   10
0266 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3     0x000f8000 /* series 3 tx rate */
0267 #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S   15
0268 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE   0x01f00000 /* RTS or CTS rate */
0269 #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
0270
0271 /**
0272  * struct ath5k_hw_tx_status - Common TX status descriptor
0273  * @tx_status_0: TX status word 0
0274  * @tx_status_1: TX status word 1
0275  */
0276 struct ath5k_hw_tx_status {
0277     u32 tx_status_0;
0278     u32 tx_status_1;
0279 } __packed __aligned(4);
0280
0281 /* TX status word 0 fields/flags */
0282 #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK  0x00000001 /* TX success */
0283 #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES  0x00000002 /* excessive retries */
0284 #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN  0x00000004 /* FIFO underrun */
0285 #define AR5K_DESC_TX_STATUS0_FILTERED       0x00000008 /* TX filter indication */
0286 /* according to the HAL sources the spec has short/long retry counts reversed.
0287  * we have it reversed to the HAL sources as well, for 5210 and 5211.
0288  * For 5212 these fields are defined as RTS_FAIL_COUNT and DATA_FAIL_COUNT,
0289  * but used respectively as SHORT and LONG retry count in the code later. This
0290  * is consistent with the definitions here... TODO: check */
0291 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT  0x000000f0 /* short retry count */
0292 #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S    4
0293 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT   0x00000f00 /* long retry count */
0294 #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
0295 #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5211   0x0000f000 /* [5211+] virtual collision count */
0296 #define AR5K_DESC_TX_STATUS0_VIRTCOLL_CT_5212_S 12
0297 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 /* TX timestamp */
0298 #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S   16
0299
0300 /* TX status word 1 fields/flags */
0301 #define AR5K_DESC_TX_STATUS1_DONE       0x00000001 /* descriptor complete */
0302 #define AR5K_DESC_TX_STATUS1_SEQ_NUM        0x00001ffe /* TX sequence number */
0303 #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S      1
0304 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH   0x001fe000 /* signal strength of ACK */
0305 #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
0306 #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212   0x00600000 /* [5212] final TX attempt series ix */
0307 #define AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212_S 21
0308 #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS_5212  0x00800000 /* [5212] compression status */
0309 #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212  0x01000000 /* [5212] transmit antenna */
0310
0311 /**
0312  * struct ath5k_hw_5210_tx_desc - 5210/5211 hardware TX descriptor
0313  * @tx_ctl: The &struct ath5k_hw_2w_tx_ctl
0314  * @tx_stat: The &struct ath5k_hw_tx_status
0315  */
0316 struct ath5k_hw_5210_tx_desc {
0317     struct ath5k_hw_2w_tx_ctl   tx_ctl;
0318     struct ath5k_hw_tx_status   tx_stat;
0319 } __packed __aligned(4);
0320
0321 /**
0322  * struct ath5k_hw_5212_tx_desc - 5212 hardware TX descriptor
0323  * @tx_ctl: The &struct ath5k_hw_4w_tx_ctl
0324  * @tx_stat: The &struct ath5k_hw_tx_status
0325  */
0326 struct ath5k_hw_5212_tx_desc {
0327     struct ath5k_hw_4w_tx_ctl   tx_ctl;
0328     struct ath5k_hw_tx_status   tx_stat;
0329 } __packed __aligned(4);
0330
0331 /**
0332  * struct ath5k_hw_all_rx_desc - Common hardware RX descriptor
0333  * @rx_ctl: The &struct ath5k_hw_rx_ctl
0334  * @rx_stat: The &struct ath5k_hw_rx_status
0335  */
0336 struct ath5k_hw_all_rx_desc {
0337     struct ath5k_hw_rx_ctl      rx_ctl;
0338     struct ath5k_hw_rx_status   rx_stat;
0339 } __packed __aligned(4);
0340
0341 /**
0342  * struct ath5k_desc - Atheros hardware DMA descriptor
0343  * @ds_link: Physical address of the next descriptor
0344  * @ds_data: Physical address of data buffer (skb)
0345  * @ud: Union containing hw_5xxx_tx_desc structs and hw_all_rx_desc
0346  *
0347  * This is read and written to by the hardware
0348  */
0349 struct ath5k_desc {
0350     u32 ds_link;
0351     u32 ds_data;
0352
0353     union {
0354         struct ath5k_hw_5210_tx_desc    ds_tx5210;
0355         struct ath5k_hw_5212_tx_desc    ds_tx5212;
0356         struct ath5k_hw_all_rx_desc ds_rx;
0357     } ud;
0358 } __packed __aligned(4);
0359
0360 #define AR5K_RXDESC_INTREQ  0x0020
0361
0362 #define AR5K_TXDESC_CLRDMASK    0x0001
0363 #define AR5K_TXDESC_NOACK   0x0002  /*[5211+]*/
0364 #define AR5K_TXDESC_RTSENA  0x0004
0365 #define AR5K_TXDESC_CTSENA  0x0008
0366 #define AR5K_TXDESC_INTREQ  0x0010
0367 #define AR5K_TXDESC_VEOL    0x0020  /*[5211+]*/