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0024 #include "ath5k.h"
0025 #include "reg.h"
0026 #include "debug.h"
0027 #include "../regd.h"
0028
0029
0030
0031
0032
0033 int ath5k_hw_set_capabilities(struct ath5k_hw *ah)
0034 {
0035 struct ath5k_capabilities *caps = &ah->ah_capabilities;
0036 u16 ee_header;
0037
0038
0039 ee_header = caps->cap_eeprom.ee_header;
0040
0041 if (ah->ah_version == AR5K_AR5210) {
0042
0043
0044
0045
0046 caps->cap_range.range_5ghz_min = 5120;
0047 caps->cap_range.range_5ghz_max = 5430;
0048 caps->cap_range.range_2ghz_min = 0;
0049 caps->cap_range.range_2ghz_max = 0;
0050
0051
0052 __set_bit(AR5K_MODE_11A, caps->cap_mode);
0053 } else {
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068 if (AR5K_EEPROM_HDR_11A(ee_header)) {
0069 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain))
0070 caps->cap_range.range_5ghz_min = 4920;
0071 else
0072 caps->cap_range.range_5ghz_min = 5005;
0073 caps->cap_range.range_5ghz_max = 6100;
0074
0075
0076 __set_bit(AR5K_MODE_11A, caps->cap_mode);
0077 }
0078
0079
0080
0081 if (AR5K_EEPROM_HDR_11B(ee_header) ||
0082 (AR5K_EEPROM_HDR_11G(ee_header) &&
0083 ah->ah_version != AR5K_AR5211)) {
0084
0085 caps->cap_range.range_2ghz_min = 2412;
0086 caps->cap_range.range_2ghz_max = 2732;
0087
0088
0089
0090
0091 if (!caps->cap_needs_2GHz_ovr) {
0092 if (AR5K_EEPROM_HDR_11B(ee_header))
0093 __set_bit(AR5K_MODE_11B,
0094 caps->cap_mode);
0095
0096 if (AR5K_EEPROM_HDR_11G(ee_header) &&
0097 ah->ah_version != AR5K_AR5211)
0098 __set_bit(AR5K_MODE_11G,
0099 caps->cap_mode);
0100 }
0101 }
0102 }
0103
0104 if ((ah->ah_radio_5ghz_revision & 0xf0) == AR5K_SREV_RAD_2112)
0105 __clear_bit(AR5K_MODE_11A, caps->cap_mode);
0106
0107
0108 if (ah->ah_version == AR5K_AR5210)
0109 caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES_NOQCU;
0110 else
0111 caps->cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
0112
0113
0114 if (ah->ah_mac_srev >= AR5K_SREV_AR5213A)
0115 caps->cap_has_phyerr_counters = true;
0116 else
0117 caps->cap_has_phyerr_counters = false;
0118
0119
0120 if (ah->ah_version == AR5K_AR5212)
0121 caps->cap_has_mrr_support = true;
0122 else
0123 caps->cap_has_mrr_support = false;
0124
0125 return 0;
0126 }
0127
0128
0129
0130
0131
0132
0133 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
0134 u16 assoc_id)
0135 {
0136 if (ah->ah_version == AR5K_AR5210) {
0137 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
0138 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
0139 return 0;
0140 }
0141
0142 return -EIO;
0143 }
0144
0145 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
0146 {
0147 if (ah->ah_version == AR5K_AR5210) {
0148 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
0149 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
0150 return 0;
0151 }
0152
0153 return -EIO;
0154 }