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0001 /*
0002  * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
0003  * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
0004  *
0005  * Permission to use, copy, modify, and distribute this software for any
0006  * purpose with or without fee is hereby granted, provided that the above
0007  * copyright notice and this permission notice appear in all copies.
0008  *
0009  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0010  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0011  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0012  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0013  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0014  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0015  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0016  */
0017 
0018 #ifndef _ATH5K_H
0019 #define _ATH5K_H
0020 
0021 /* TODO: Clean up channel debugging (doesn't work anyway) and start
0022  * working on reg. control code using all available eeprom information
0023  * (rev. engineering needed) */
0024 #define CHAN_DEBUG  0
0025 
0026 #include <linux/io.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/types.h>
0029 #include <linux/average.h>
0030 #include <linux/leds.h>
0031 #include <net/mac80211.h>
0032 #include <net/cfg80211.h>
0033 
0034 /* RX/TX descriptor hw structs
0035  * TODO: Driver part should only see sw structs */
0036 #include "desc.h"
0037 
0038 /* EEPROM structs/offsets
0039  * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
0040  * and clean up common bits, then introduce set/get functions in eeprom.c */
0041 #include "eeprom.h"
0042 #include "debug.h"
0043 #include "../ath.h"
0044 #include "ani.h"
0045 
0046 /* PCI IDs */
0047 #define PCI_DEVICE_ID_ATHEROS_AR5210        0x0007 /* AR5210 */
0048 #define PCI_DEVICE_ID_ATHEROS_AR5311        0x0011 /* AR5311 */
0049 #define PCI_DEVICE_ID_ATHEROS_AR5211        0x0012 /* AR5211 */
0050 #define PCI_DEVICE_ID_ATHEROS_AR5212        0x0013 /* AR5212 */
0051 #define PCI_DEVICE_ID_3COM_3CRDAG675        0x0013 /* 3CRDAG675 (Atheros AR5212) */
0052 #define PCI_DEVICE_ID_3COM_2_3CRPAG175      0x0013 /* 3CRPAG175 (Atheros AR5212) */
0053 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP     0x0207 /* AR5210 (Early) */
0054 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM    0x1014 /* AR5212 (IBM MiniPCI) */
0055 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT    0x1107 /* AR5210 (no eeprom) */
0056 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT    0x1113 /* AR5212 (no eeprom) */
0057 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT    0x1112 /* AR5211 (no eeprom) */
0058 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA   0xf013 /* AR5212 (emulation board) */
0059 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
0060 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B    0xf11b /* AR5211 (emulation board) */
0061 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2   0x0052 /* AR5312 WMAC (AP31) */
0062 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7   0x0057 /* AR5312 WMAC (AP30-040) */
0063 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8   0x0058 /* AR5312 WMAC (AP43-030) */
0064 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014   0x0014 /* AR5212 compatible */
0065 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015   0x0015 /* AR5212 compatible */
0066 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016   0x0016 /* AR5212 compatible */
0067 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017   0x0017 /* AR5212 compatible */
0068 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018   0x0018 /* AR5212 compatible */
0069 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019   0x0019 /* AR5212 compatible */
0070 #define PCI_DEVICE_ID_ATHEROS_AR2413        0x001a /* AR2413 (Griffin-lite) */
0071 #define PCI_DEVICE_ID_ATHEROS_AR5413        0x001b /* AR5413 (Eagle) */
0072 #define PCI_DEVICE_ID_ATHEROS_AR5424        0x001c /* AR5424 (Condor PCI-E) */
0073 #define PCI_DEVICE_ID_ATHEROS_AR5416        0x0023 /* AR5416 */
0074 #define PCI_DEVICE_ID_ATHEROS_AR5418        0x0024 /* AR5418 */
0075 
0076 /****************************\
0077   GENERIC DRIVER DEFINITIONS
0078 \****************************/
0079 
0080 #define ATH5K_PRINTF(fmt, ...)                      \
0081     pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)
0082 
0083 void __printf(3, 4)
0084 _ath5k_printk(const struct ath5k_hw *ah, const char *level,
0085           const char *fmt, ...);
0086 
0087 #define ATH5K_PRINTK(_sc, _level, _fmt, ...)                \
0088     _ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)
0089 
0090 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...)          \
0091 do {                                    \
0092     if (net_ratelimit())                        \
0093         ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__);     \
0094 } while (0)
0095 
0096 #define ATH5K_INFO(_sc, _fmt, ...)                  \
0097     ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
0098 
0099 #define ATH5K_WARN(_sc, _fmt, ...)                  \
0100     ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
0101 
0102 #define ATH5K_ERR(_sc, _fmt, ...)                   \
0103     ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
0104 
0105 /*
0106  * AR5K REGISTER ACCESS
0107  */
0108 
0109 /* Some macros to read/write fields */
0110 
0111 /* First shift, then mask */
0112 #define AR5K_REG_SM(_val, _flags)                   \
0113     (((_val) << _flags##_S) & (_flags))
0114 
0115 /* First mask, then shift */
0116 #define AR5K_REG_MS(_val, _flags)                   \
0117     (((_val) & (_flags)) >> _flags##_S)
0118 
0119 /* Some registers can hold multiple values of interest. For this
0120  * reason when we want to write to these registers we must first
0121  * retrieve the values which we do not want to clear (lets call this
0122  * old_data) and then set the register with this and our new_value:
0123  * ( old_data | new_value) */
0124 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)         \
0125     ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
0126         (((_val) << _flags##_S) & (_flags)), _reg)
0127 
0128 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)           \
0129     ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) &       \
0130             (_mask)) | (_flags), _reg)
0131 
0132 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)              \
0133     ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
0134 
0135 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)         \
0136     ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
0137 
0138 /* Access QCU registers per queue */
0139 #define AR5K_REG_READ_Q(ah, _reg, _queue)               \
0140     (ath5k_hw_reg_read(ah, _reg) & (1 << _queue))           \
0141 
0142 #define AR5K_REG_WRITE_Q(ah, _reg, _queue)              \
0143     ath5k_hw_reg_write(ah, (1 << _queue), _reg)
0144 
0145 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do {               \
0146     _reg |= 1 << _queue;                        \
0147 } while (0)
0148 
0149 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do {              \
0150     _reg &= ~(1 << _queue);                     \
0151 } while (0)
0152 
0153 /* Used while writing initvals */
0154 #define AR5K_REG_WAIT(_i) do {                      \
0155     if (_i % 64)                            \
0156         udelay(1);                      \
0157 } while (0)
0158 
0159 /*
0160  * Some tunable values (these should be changeable by the user)
0161  * TODO: Make use of them and add more options OR use debug/configfs
0162  */
0163 #define AR5K_TUNE_DMA_BEACON_RESP       2
0164 #define AR5K_TUNE_SW_BEACON_RESP        10
0165 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF   0
0166 #define AR5K_TUNE_MIN_TX_FIFO_THRES     1
0167 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
0168 #define AR5K_TUNE_REGISTER_TIMEOUT      20000
0169 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
0170  * be the max value. */
0171 #define AR5K_TUNE_RSSI_THRES            129
0172 /* This must be set when setting the RSSI threshold otherwise it can
0173  * prevent a reset. If AR5K_RSSI_THR is read after writing to it
0174  * the BMISS_THRES will be seen as 0, seems hardware doesn't keep
0175  * track of it. Max value depends on hardware. For AR5210 this is just 7.
0176  * For AR5211+ this seems to be up to 255. */
0177 #define AR5K_TUNE_BMISS_THRES           7
0178 #define AR5K_TUNE_REGISTER_DWELL_TIME       20000
0179 #define AR5K_TUNE_BEACON_INTERVAL       100
0180 #define AR5K_TUNE_AIFS              2
0181 #define AR5K_TUNE_AIFS_11B          2
0182 #define AR5K_TUNE_AIFS_XR           0
0183 #define AR5K_TUNE_CWMIN             15
0184 #define AR5K_TUNE_CWMIN_11B         31
0185 #define AR5K_TUNE_CWMIN_XR          3
0186 #define AR5K_TUNE_CWMAX             1023
0187 #define AR5K_TUNE_CWMAX_11B         1023
0188 #define AR5K_TUNE_CWMAX_XR          7
0189 #define AR5K_TUNE_NOISE_FLOOR           -72
0190 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE        -95
0191 #define AR5K_TUNE_MAX_TXPOWER           63
0192 #define AR5K_TUNE_DEFAULT_TXPOWER       25
0193 #define AR5K_TUNE_TPC_TXPOWER           false
0194 #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL    60000   /* 60 sec */
0195 #define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT   10000   /* 10 sec */
0196 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000    /* 1 sec */
0197 #define ATH5K_TX_COMPLETE_POLL_INT      3000    /* 3 sec */
0198 
0199 #define AR5K_INIT_CARR_SENSE_EN         1
0200 
0201 /*Swap RX/TX Descriptor for big endian archs*/
0202 #if defined(__BIG_ENDIAN)
0203 #define AR5K_INIT_CFG   (       \
0204     AR5K_CFG_SWTD | AR5K_CFG_SWRD   \
0205 )
0206 #else
0207 #define AR5K_INIT_CFG   0x00000000
0208 #endif
0209 
0210 /* Initial values */
0211 #define AR5K_INIT_CYCRSSI_THR1          2
0212 
0213 /* Tx retry limit defaults from standard */
0214 #define AR5K_INIT_RETRY_SHORT           7
0215 #define AR5K_INIT_RETRY_LONG            4
0216 
0217 /* Slot time */
0218 #define AR5K_INIT_SLOT_TIME_TURBO       6
0219 #define AR5K_INIT_SLOT_TIME_DEFAULT     9
0220 #define AR5K_INIT_SLOT_TIME_HALF_RATE       13
0221 #define AR5K_INIT_SLOT_TIME_QUARTER_RATE    21
0222 #define AR5K_INIT_SLOT_TIME_B           20
0223 #define AR5K_SLOT_TIME_MAX          0xffff
0224 
0225 /* SIFS */
0226 #define AR5K_INIT_SIFS_TURBO            6
0227 #define AR5K_INIT_SIFS_DEFAULT_BG       10
0228 #define AR5K_INIT_SIFS_DEFAULT_A        16
0229 #define AR5K_INIT_SIFS_HALF_RATE        32
0230 #define AR5K_INIT_SIFS_QUARTER_RATE     64
0231 
0232 /* Used to calculate tx time for non 5/10/40MHz
0233  * operation */
0234 /* It's preamble time + signal time (16 + 4) */
0235 #define AR5K_INIT_OFDM_PREAMPLE_TIME        20
0236 /* Preamble time for 40MHz (turbo) operation (min ?) */
0237 #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN    14
0238 #define AR5K_INIT_OFDM_SYMBOL_TIME      4
0239 #define AR5K_INIT_OFDM_PLCP_BITS        22
0240 
0241 /* Rx latency for 5 and 10MHz operation (max ?) */
0242 #define AR5K_INIT_RX_LAT_MAX            63
0243 /* Tx latencies from initvals (5212 only but no problem
0244  * because we only tweak them on 5212) */
0245 #define AR5K_INIT_TX_LAT_A          54
0246 #define AR5K_INIT_TX_LAT_BG         384
0247 /* Tx latency for 40MHz (turbo) operation (min ?) */
0248 #define AR5K_INIT_TX_LAT_MIN            32
0249 /* Default Tx/Rx latencies (same for 5211)*/
0250 #define AR5K_INIT_TX_LATENCY_5210       54
0251 #define AR5K_INIT_RX_LATENCY_5210       29
0252 
0253 /* Tx frame to Tx data start delay */
0254 #define AR5K_INIT_TXF2TXD_START_DEFAULT     14
0255 #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
0256 #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ  13
0257 
0258 /* We need to increase PHY switch and agc settling time
0259  * on turbo mode */
0260 #define AR5K_SWITCH_SETTLING            5760
0261 #define AR5K_SWITCH_SETTLING_TURBO      7168
0262 
0263 #define AR5K_AGC_SETTLING           28
0264 /* 38 on 5210 but shouldn't matter */
0265 #define AR5K_AGC_SETTLING_TURBO         37
0266 
0267 
0268 
0269 /*****************************\
0270 * GENERIC CHIPSET DEFINITIONS *
0271 \*****************************/
0272 
0273 /**
0274  * enum ath5k_version - MAC Chips
0275  * @AR5K_AR5210: AR5210 (Crete)
0276  * @AR5K_AR5211: AR5211 (Oahu/Maui)
0277  * @AR5K_AR5212: AR5212 (Venice) and newer
0278  */
0279 enum ath5k_version {
0280     AR5K_AR5210 = 0,
0281     AR5K_AR5211 = 1,
0282     AR5K_AR5212 = 2,
0283 };
0284 
0285 /**
0286  * enum ath5k_radio - PHY Chips
0287  * @AR5K_RF5110: RF5110 (Fez)
0288  * @AR5K_RF5111: RF5111 (Sombrero)
0289  * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
0290  * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
0291  * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
0292  * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
0293  * @AR5K_RF2317: RF2317 (Spider SoC)
0294  * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
0295  */
0296 enum ath5k_radio {
0297     AR5K_RF5110 = 0,
0298     AR5K_RF5111 = 1,
0299     AR5K_RF5112 = 2,
0300     AR5K_RF2413 = 3,
0301     AR5K_RF5413 = 4,
0302     AR5K_RF2316 = 5,
0303     AR5K_RF2317 = 6,
0304     AR5K_RF2425 = 7,
0305 };
0306 
0307 /*
0308  * Common silicon revision/version values
0309  */
0310 
0311 #define AR5K_SREV_UNKNOWN   0xffff
0312 
0313 #define AR5K_SREV_AR5210    0x00 /* Crete */
0314 #define AR5K_SREV_AR5311    0x10 /* Maui 1 */
0315 #define AR5K_SREV_AR5311A   0x20 /* Maui 2 */
0316 #define AR5K_SREV_AR5311B   0x30 /* Spirit */
0317 #define AR5K_SREV_AR5211    0x40 /* Oahu */
0318 #define AR5K_SREV_AR5212    0x50 /* Venice */
0319 #define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
0320 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
0321 #define AR5K_SREV_AR5213    0x55 /* ??? */
0322 #define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
0323 #define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
0324 #define AR5K_SREV_AR5213A   0x59 /* Hainan */
0325 #define AR5K_SREV_AR2413    0x78 /* Griffin lite */
0326 #define AR5K_SREV_AR2414    0x70 /* Griffin */
0327 #define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
0328 #define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
0329 #define AR5K_SREV_AR5424    0x90 /* Condor */
0330 #define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
0331 #define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
0332 #define AR5K_SREV_AR5413    0xa4 /* Eagle lite */
0333 #define AR5K_SREV_AR5414    0xa0 /* Eagle */
0334 #define AR5K_SREV_AR2415    0xb0 /* Talon */
0335 #define AR5K_SREV_AR5416    0xc0 /* PCI-E */
0336 #define AR5K_SREV_AR5418    0xca /* PCI-E */
0337 #define AR5K_SREV_AR2425    0xe0 /* Swan */
0338 #define AR5K_SREV_AR2417    0xf0 /* Nala */
0339 
0340 #define AR5K_SREV_RAD_5110  0x00
0341 #define AR5K_SREV_RAD_5111  0x10
0342 #define AR5K_SREV_RAD_5111A 0x15
0343 #define AR5K_SREV_RAD_2111  0x20
0344 #define AR5K_SREV_RAD_5112  0x30
0345 #define AR5K_SREV_RAD_5112A 0x35
0346 #define AR5K_SREV_RAD_5112B 0x36
0347 #define AR5K_SREV_RAD_2112  0x40
0348 #define AR5K_SREV_RAD_2112A 0x45
0349 #define AR5K_SREV_RAD_2112B 0x46
0350 #define AR5K_SREV_RAD_2413  0x50
0351 #define AR5K_SREV_RAD_5413  0x60
0352 #define AR5K_SREV_RAD_2316  0x70 /* Cobra SoC */
0353 #define AR5K_SREV_RAD_2317  0x80
0354 #define AR5K_SREV_RAD_5424  0xa0 /* Mostly same as 5413 */
0355 #define AR5K_SREV_RAD_2425  0xa2
0356 #define AR5K_SREV_RAD_5133  0xc0
0357 
0358 #define AR5K_SREV_PHY_5211  0x30
0359 #define AR5K_SREV_PHY_5212  0x41
0360 #define AR5K_SREV_PHY_5212A 0x42
0361 #define AR5K_SREV_PHY_5212B 0x43
0362 #define AR5K_SREV_PHY_2413  0x45
0363 #define AR5K_SREV_PHY_5413  0x61
0364 #define AR5K_SREV_PHY_2425  0x70
0365 
0366 /* TODO add support to mac80211 for vendor-specific rates and modes */
0367 
0368 /**
0369  * DOC: Atheros XR
0370  *
0371  * Some of this information is based on Documentation from:
0372  *
0373  * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
0374  *
0375  * Atheros' eXtended Range - range enhancing extension is a modulation scheme
0376  * that is supposed to double the link distance between an Atheros XR-enabled
0377  * client device with an Atheros XR-enabled access point. This is achieved
0378  * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
0379  * above what the 802.11 specifications demand. In addition, new (proprietary)
0380  * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
0381  *
0382  * Please note that can you either use XR or TURBO but you cannot use both,
0383  * they are exclusive.
0384  *
0385  * Also note that we do not plan to support XR mode at least for now. You can
0386  * get a mode similar to XR by using 5MHz bwmode.
0387  */
0388 
0389 
0390 /**
0391  * DOC: Atheros SuperAG
0392  *
0393  * In addition to XR we have another modulation scheme called TURBO mode
0394  * that is supposed to provide a throughput transmission speed up to 40Mbit/s
0395  * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
0396  * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
0397  * There is also a distinction between "static" and "dynamic" turbo modes:
0398  *
0399  * - Static: is the dumb version: devices set to this mode stick to it until
0400  *     the mode is turned off.
0401  *
0402  * - Dynamic: is the intelligent version, the network decides itself if it
0403  *     is ok to use turbo. As soon as traffic is detected on adjacent channels
0404  *     (which would get used in turbo mode), or when a non-turbo station joins
0405  *     the network, turbo mode won't be used until the situation changes again.
0406  *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
0407  *     monitors the used radio band in order to decide whether turbo mode may
0408  *     be used or not.
0409  *
0410  * This article claims Super G sticks to bonding of channels 5 and 6 for
0411  * USA:
0412  *
0413  * https://www.pcworld.com/article/id,113428-page,1/article.html
0414  *
0415  * The channel bonding seems to be driver specific though.
0416  *
0417  * In addition to TURBO modes we also have the following features for even
0418  * greater speed-up:
0419  *
0420  * - Bursting: allows multiple frames to be sent at once, rather than pausing
0421  *     after each frame. Bursting is a standards-compliant feature that can be
0422  *     used with any Access Point.
0423  *
0424  * - Fast frames: increases the amount of information that can be sent per
0425  *     frame, also resulting in a reduction of transmission overhead. It is a
0426  *     proprietary feature that needs to be supported by the Access Point.
0427  *
0428  * - Compression: data frames are compressed in real time using a Lempel Ziv
0429  *     algorithm. This is done transparently. Once this feature is enabled,
0430  *     compression and decompression takes place inside the chipset, without
0431  *     putting additional load on the host CPU.
0432  *
0433  * As with XR we also don't plan to support SuperAG features for now. You can
0434  * get a mode similar to TURBO by using 40MHz bwmode.
0435  */
0436 
0437 
0438 /**
0439  * enum ath5k_driver_mode - PHY operation mode
0440  * @AR5K_MODE_11A: 802.11a
0441  * @AR5K_MODE_11B: 802.11b
0442  * @AR5K_MODE_11G: 801.11g
0443  * @AR5K_MODE_MAX: Used for boundary checks
0444  *
0445  * Do not change the order here, we use these as
0446  * array indices and it also maps EEPROM structures.
0447  */
0448 enum ath5k_driver_mode {
0449     AR5K_MODE_11A       =   0,
0450     AR5K_MODE_11B       =   1,
0451     AR5K_MODE_11G       =   2,
0452     AR5K_MODE_MAX       =   3
0453 };
0454 
0455 /**
0456  * enum ath5k_ant_mode - Antenna operation mode
0457  * @AR5K_ANTMODE_DEFAULT: Default antenna setup
0458  * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
0459  * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
0460  * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
0461  * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
0462  * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
0463  * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
0464  * @AR5K_ANTMODE_MAX: Used for boundary checks
0465  *
0466  * For more infos on antenna control check out phy.c
0467  */
0468 enum ath5k_ant_mode {
0469     AR5K_ANTMODE_DEFAULT    = 0,
0470     AR5K_ANTMODE_FIXED_A    = 1,
0471     AR5K_ANTMODE_FIXED_B    = 2,
0472     AR5K_ANTMODE_SINGLE_AP  = 3,
0473     AR5K_ANTMODE_SECTOR_AP  = 4,
0474     AR5K_ANTMODE_SECTOR_STA = 5,
0475     AR5K_ANTMODE_DEBUG  = 6,
0476     AR5K_ANTMODE_MAX,
0477 };
0478 
0479 /**
0480  * enum ath5k_bw_mode - Bandwidth operation mode
0481  * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
0482  * @AR5K_BWMODE_5MHZ: Quarter rate
0483  * @AR5K_BWMODE_10MHZ: Half rate
0484  * @AR5K_BWMODE_40MHZ: Turbo
0485  */
0486 enum ath5k_bw_mode {
0487     AR5K_BWMODE_DEFAULT = 0,
0488     AR5K_BWMODE_5MHZ    = 1,
0489     AR5K_BWMODE_10MHZ   = 2,
0490     AR5K_BWMODE_40MHZ   = 3
0491 };
0492 
0493 
0494 
0495 /****************\
0496   TX DEFINITIONS
0497 \****************/
0498 
0499 /**
0500  * struct ath5k_tx_status - TX Status descriptor
0501  * @ts_seqnum: Sequence number
0502  * @ts_tstamp: Timestamp
0503  * @ts_status: Status code
0504  * @ts_final_idx: Final transmission series index
0505  * @ts_final_retry: Final retry count
0506  * @ts_rssi: RSSI for received ACK
0507  * @ts_shortretry: Short retry count
0508  * @ts_virtcol: Virtual collision count
0509  * @ts_antenna: Antenna used
0510  *
0511  * TX status descriptor gets filled by the hw
0512  * on each transmission attempt.
0513  */
0514 struct ath5k_tx_status {
0515     u16 ts_seqnum;
0516     u16 ts_tstamp;
0517     u8  ts_status;
0518     u8  ts_final_idx;
0519     u8  ts_final_retry;
0520     s8  ts_rssi;
0521     u8  ts_shortretry;
0522     u8  ts_virtcol;
0523     u8  ts_antenna;
0524 };
0525 
0526 #define AR5K_TXSTAT_ALTRATE 0x80
0527 #define AR5K_TXERR_XRETRY   0x01
0528 #define AR5K_TXERR_FILT     0x02
0529 #define AR5K_TXERR_FIFO     0x04
0530 
0531 /**
0532  * enum ath5k_tx_queue - Queue types used to classify tx queues.
0533  * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
0534  * @AR5K_TX_QUEUE_DATA: A normal data queue
0535  * @AR5K_TX_QUEUE_BEACON: The beacon queue
0536  * @AR5K_TX_QUEUE_CAB: The after-beacon queue
0537  * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
0538  */
0539 enum ath5k_tx_queue {
0540     AR5K_TX_QUEUE_INACTIVE = 0,
0541     AR5K_TX_QUEUE_DATA,
0542     AR5K_TX_QUEUE_BEACON,
0543     AR5K_TX_QUEUE_CAB,
0544     AR5K_TX_QUEUE_UAPSD,
0545 };
0546 
0547 #define AR5K_NUM_TX_QUEUES      10
0548 #define AR5K_NUM_TX_QUEUES_NOQCU    2
0549 
0550 /**
0551  * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
0552  * @AR5K_WME_AC_BK: Background traffic
0553  * @AR5K_WME_AC_BE: Best-effort (normal) traffic
0554  * @AR5K_WME_AC_VI: Video traffic
0555  * @AR5K_WME_AC_VO: Voice traffic
0556  *
0557  * These are the 4 Access Categories as defined in
0558  * WME spec. 0 is the lowest priority and 4 is the
0559  * highest. Normal data that hasn't been classified
0560  * goes to the Best Effort AC.
0561  */
0562 enum ath5k_tx_queue_subtype {
0563     AR5K_WME_AC_BK = 0,
0564     AR5K_WME_AC_BE,
0565     AR5K_WME_AC_VI,
0566     AR5K_WME_AC_VO,
0567 };
0568 
0569 /**
0570  * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
0571  * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
0572  * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
0573  * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
0574  * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
0575  * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
0576  * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
0577  * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
0578  *
0579  * Each number represents a hw queue. If hw does not support hw queues
0580  * (eg 5210) all data goes in one queue.
0581  */
0582 enum ath5k_tx_queue_id {
0583     AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
0584     AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
0585     AR5K_TX_QUEUE_ID_DATA_MIN   = 0,
0586     AR5K_TX_QUEUE_ID_DATA_MAX   = 3,
0587     AR5K_TX_QUEUE_ID_UAPSD      = 7,
0588     AR5K_TX_QUEUE_ID_CAB        = 8,
0589     AR5K_TX_QUEUE_ID_BEACON     = 9,
0590 };
0591 
0592 /*
0593  * Flags to set hw queue's parameters...
0594  */
0595 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE        0x0001  /* Enable TXOK interrupt */
0596 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE       0x0002  /* Enable TXERR interrupt */
0597 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE       0x0004  /* Enable TXEOL interrupt -not used- */
0598 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE      0x0008  /* Enable TXDESC interrupt -not used- */
0599 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE       0x0010  /* Enable TXURN interrupt */
0600 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE      0x0020  /* Enable CBRORN interrupt */
0601 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE      0x0040  /* Enable CBRURN interrupt */
0602 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE       0x0080  /* Enable QTRIG interrupt */
0603 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE     0x0100  /* Enable TXNOFRM interrupt */
0604 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE       0x0200  /* Disable random post-backoff */
0605 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300  /* Enable ready time expiry policy (?)*/
0606 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800  /* Enable backoff while bursting */
0607 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS     0x1000  /* Disable backoff while bursting */
0608 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE    0x2000  /* Enable hw compression -not implemented-*/
0609 
0610 /**
0611  * struct ath5k_txq - Transmit queue state
0612  * @qnum: Hardware q number
0613  * @link: Link ptr in last TX desc
0614  * @q: Transmit queue (&struct list_head)
0615  * @lock: Lock on q and link
0616  * @setup: Is the queue configured
0617  * @txq_len:Number of queued buffers
0618  * @txq_max: Max allowed num of queued buffers
0619  * @txq_poll_mark: Used to check if queue got stuck
0620  * @txq_stuck: Queue stuck counter
0621  *
0622  * One of these exists for each hardware transmit queue.
0623  * Packets sent to us from above are assigned to queues based
0624  * on their priority.  Not all devices support a complete set
0625  * of hardware transmit queues. For those devices the array
0626  * sc_ac2q will map multiple priorities to fewer hardware queues
0627  * (typically all to one hardware queue).
0628  */
0629 struct ath5k_txq {
0630     unsigned int        qnum;
0631     u32         *link;
0632     struct list_head    q;
0633     spinlock_t      lock;
0634     bool            setup;
0635     int         txq_len;
0636     int         txq_max;
0637     bool            txq_poll_mark;
0638     unsigned int        txq_stuck;
0639 };
0640 
0641 /**
0642  * struct ath5k_txq_info - A struct to hold TX queue's parameters
0643  * @tqi_type: One of enum ath5k_tx_queue
0644  * @tqi_subtype: One of enum ath5k_tx_queue_subtype
0645  * @tqi_flags: TX queue flags (see above)
0646  * @tqi_aifs: Arbitrated Inter-frame Space
0647  * @tqi_cw_min: Minimum Contention Window
0648  * @tqi_cw_max: Maximum Contention Window
0649  * @tqi_cbr_period: Constant bit rate period
0650  * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
0651  */
0652 struct ath5k_txq_info {
0653     enum ath5k_tx_queue tqi_type;
0654     enum ath5k_tx_queue_subtype tqi_subtype;
0655     u16 tqi_flags;
0656     u8  tqi_aifs;
0657     u16 tqi_cw_min;
0658     u16 tqi_cw_max;
0659     u32 tqi_cbr_period;
0660     u32 tqi_cbr_overflow_limit;
0661     u32 tqi_burst_time;
0662     u32 tqi_ready_time;
0663 };
0664 
0665 /**
0666  * enum ath5k_pkt_type - Transmit packet types
0667  * @AR5K_PKT_TYPE_NORMAL: Normal data
0668  * @AR5K_PKT_TYPE_ATIM: ATIM
0669  * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
0670  * @AR5K_PKT_TYPE_BEACON: Beacon
0671  * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
0672  * @AR5K_PKT_TYPE_PIFS: PIFS
0673  * Used on tx control descriptor
0674  */
0675 enum ath5k_pkt_type {
0676     AR5K_PKT_TYPE_NORMAL        = 0,
0677     AR5K_PKT_TYPE_ATIM      = 1,
0678     AR5K_PKT_TYPE_PSPOLL        = 2,
0679     AR5K_PKT_TYPE_BEACON        = 3,
0680     AR5K_PKT_TYPE_PROBE_RESP    = 4,
0681     AR5K_PKT_TYPE_PIFS      = 5,
0682 };
0683 
0684 /*
0685  * TX power and TPC settings
0686  */
0687 #define AR5K_TXPOWER_OFDM(_r, _v)   (           \
0688     ((0 & 1) << ((_v) + 6)) |               \
0689     (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
0690 )
0691 
0692 #define AR5K_TXPOWER_CCK(_r, _v)    (           \
0693     (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
0694 )
0695 
0696 
0697 
0698 /****************\
0699   RX DEFINITIONS
0700 \****************/
0701 
0702 /**
0703  * struct ath5k_rx_status - RX Status descriptor
0704  * @rs_datalen: Data length
0705  * @rs_tstamp: Timestamp
0706  * @rs_status: Status code
0707  * @rs_phyerr: PHY error mask
0708  * @rs_rssi: RSSI in 0.5dbm units
0709  * @rs_keyix: Index to the key used for decrypting
0710  * @rs_rate: Rate used to decode the frame
0711  * @rs_antenna: Antenna used to receive the frame
0712  * @rs_more: Indicates this is a frame fragment (Fast frames)
0713  */
0714 struct ath5k_rx_status {
0715     u16 rs_datalen;
0716     u16 rs_tstamp;
0717     u8  rs_status;
0718     u8  rs_phyerr;
0719     s8  rs_rssi;
0720     u8  rs_keyix;
0721     u8  rs_rate;
0722     u8  rs_antenna;
0723     u8  rs_more;
0724 };
0725 
0726 #define AR5K_RXERR_CRC      0x01
0727 #define AR5K_RXERR_PHY      0x02
0728 #define AR5K_RXERR_FIFO     0x04
0729 #define AR5K_RXERR_DECRYPT  0x08
0730 #define AR5K_RXERR_MIC      0x10
0731 #define AR5K_RXKEYIX_INVALID    ((u8) -1)
0732 #define AR5K_TXKEYIX_INVALID    ((u32) -1)
0733 
0734 
0735 /**************************\
0736  BEACON TIMERS DEFINITIONS
0737 \**************************/
0738 
0739 #define AR5K_BEACON_PERIOD  0x0000ffff
0740 #define AR5K_BEACON_ENA     0x00800000 /*enable beacon xmit*/
0741 #define AR5K_BEACON_RESET_TSF   0x01000000 /*force a TSF reset*/
0742 
0743 
0744 /*
0745  * TSF to TU conversion:
0746  *
0747  * TSF is a 64bit value in usec (microseconds).
0748  * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
0749  * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
0750  */
0751 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
0752 
0753 
0754 
0755 /*******************************\
0756   GAIN OPTIMIZATION DEFINITIONS
0757 \*******************************/
0758 
0759 /**
0760  * enum ath5k_rfgain - RF Gain optimization engine state
0761  * @AR5K_RFGAIN_INACTIVE: Engine disabled
0762  * @AR5K_RFGAIN_ACTIVE: Probe active
0763  * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
0764  * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
0765  */
0766 enum ath5k_rfgain {
0767     AR5K_RFGAIN_INACTIVE = 0,
0768     AR5K_RFGAIN_ACTIVE,
0769     AR5K_RFGAIN_READ_REQUESTED,
0770     AR5K_RFGAIN_NEED_CHANGE,
0771 };
0772 
0773 /**
0774  * struct ath5k_gain - RF Gain optimization engine state data
0775  * @g_step_idx: Current step index
0776  * @g_current: Current gain
0777  * @g_target: Target gain
0778  * @g_low: Low gain boundary
0779  * @g_high: High gain boundary
0780  * @g_f_corr: Gain_F correction
0781  * @g_state: One of enum ath5k_rfgain
0782  */
0783 struct ath5k_gain {
0784     u8          g_step_idx;
0785     u8          g_current;
0786     u8          g_target;
0787     u8          g_low;
0788     u8          g_high;
0789     u8          g_f_corr;
0790     u8          g_state;
0791 };
0792 
0793 
0794 
0795 /********************\
0796   COMMON DEFINITIONS
0797 \********************/
0798 
0799 #define AR5K_SLOT_TIME_9    396
0800 #define AR5K_SLOT_TIME_20   880
0801 #define AR5K_SLOT_TIME_MAX  0xffff
0802 
0803 /**
0804  * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
0805  * @a2_flags: Channel flags (internal)
0806  * @a2_athchan: HW channel number (internal)
0807  *
0808  * This structure is used to map 2GHz channels to
0809  * 5GHz Atheros channels on 2111 frequency converter
0810  * that comes together with RF5111
0811  * TODO: Clean up
0812  */
0813 struct ath5k_athchan_2ghz {
0814     u32 a2_flags;
0815     u16 a2_athchan;
0816 };
0817 
0818 /**
0819  * enum ath5k_dmasize -  DMA size definitions (2^(n+2))
0820  * @AR5K_DMASIZE_4B: 4Bytes
0821  * @AR5K_DMASIZE_8B: 8Bytes
0822  * @AR5K_DMASIZE_16B: 16Bytes
0823  * @AR5K_DMASIZE_32B: 32Bytes
0824  * @AR5K_DMASIZE_64B: 64Bytes (Default)
0825  * @AR5K_DMASIZE_128B: 128Bytes
0826  * @AR5K_DMASIZE_256B: 256Bytes
0827  * @AR5K_DMASIZE_512B: 512Bytes
0828  *
0829  * These are used to set DMA burst size on hw
0830  *
0831  * Note: Some platforms can't handle more than 4Bytes
0832  * be careful on embedded boards.
0833  */
0834 enum ath5k_dmasize {
0835     AR5K_DMASIZE_4B = 0,
0836     AR5K_DMASIZE_8B,
0837     AR5K_DMASIZE_16B,
0838     AR5K_DMASIZE_32B,
0839     AR5K_DMASIZE_64B,
0840     AR5K_DMASIZE_128B,
0841     AR5K_DMASIZE_256B,
0842     AR5K_DMASIZE_512B
0843 };
0844 
0845 
0846 
0847 /******************\
0848   RATE DEFINITIONS
0849 \******************/
0850 
0851 /**
0852  * DOC: Rate codes
0853  *
0854  * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
0855  *
0856  * The rate code is used to get the RX rate or set the TX rate on the
0857  * hardware descriptors. It is also used for internal modulation control
0858  * and settings.
0859  *
0860  * This is the hardware rate map we are aware of (html unfriendly):
0861  *
0862  * Rate code    Rate (Kbps)
0863  * ---------    -----------
0864  * 0x01      3000 (XR)
0865  * 0x02      1000 (XR)
0866  * 0x03       250 (XR)
0867  * 0x04 - 05    -Reserved-
0868  * 0x06      2000 (XR)
0869  * 0x07       500 (XR)
0870  * 0x08     48000 (OFDM)
0871  * 0x09     24000 (OFDM)
0872  * 0x0A     12000 (OFDM)
0873  * 0x0B      6000 (OFDM)
0874  * 0x0C     54000 (OFDM)
0875  * 0x0D     36000 (OFDM)
0876  * 0x0E     18000 (OFDM)
0877  * 0x0F      9000 (OFDM)
0878  * 0x10 - 17    -Reserved-
0879  * 0x18     11000L (CCK)
0880  * 0x19      5500L (CCK)
0881  * 0x1A      2000L (CCK)
0882  * 0x1B      1000L (CCK)
0883  * 0x1C     11000S (CCK)
0884  * 0x1D      5500S (CCK)
0885  * 0x1E      2000S (CCK)
0886  * 0x1F     -Reserved-
0887  *
0888  * "S" indicates CCK rates with short preamble and "L" with long preamble.
0889  *
0890  * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
0891  * lowest 4 bits, so they are the same as above with a 0xF mask.
0892  * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
0893  * We handle this in ath5k_setup_bands().
0894  */
0895 #define AR5K_MAX_RATES 32
0896 
0897 /* B */
0898 #define ATH5K_RATE_CODE_1M  0x1B
0899 #define ATH5K_RATE_CODE_2M  0x1A
0900 #define ATH5K_RATE_CODE_5_5M    0x19
0901 #define ATH5K_RATE_CODE_11M 0x18
0902 /* A and G */
0903 #define ATH5K_RATE_CODE_6M  0x0B
0904 #define ATH5K_RATE_CODE_9M  0x0F
0905 #define ATH5K_RATE_CODE_12M 0x0A
0906 #define ATH5K_RATE_CODE_18M 0x0E
0907 #define ATH5K_RATE_CODE_24M 0x09
0908 #define ATH5K_RATE_CODE_36M 0x0D
0909 #define ATH5K_RATE_CODE_48M 0x08
0910 #define ATH5K_RATE_CODE_54M 0x0C
0911 
0912 /* Adding this flag to rate_code on B rates
0913  * enables short preamble */
0914 #define AR5K_SET_SHORT_PREAMBLE 0x04
0915 
0916 /*
0917  * Crypto definitions
0918  */
0919 
0920 #define AR5K_KEYCACHE_SIZE  8
0921 extern bool ath5k_modparam_nohwcrypt;
0922 
0923 /***********************\
0924  HW RELATED DEFINITIONS
0925 \***********************/
0926 
0927 /*
0928  * Misc definitions
0929  */
0930 #define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
0931 
0932 #define AR5K_ASSERT_ENTRY(_e, _s) do {      \
0933     if (_e >= _s)               \
0934         return false;           \
0935 } while (0)
0936 
0937 /*
0938  * Hardware interrupt abstraction
0939  */
0940 
0941 /**
0942  * enum ath5k_int - Hardware interrupt masks helpers
0943  * @AR5K_INT_RXOK: Frame successfully received
0944  * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
0945  * @AR5K_INT_RXERR: Frame reception failed
0946  * @AR5K_INT_RXNOFRM: No frame received within a specified time period
0947  * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
0948  * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
0949  *      not always fatal, on some chips we can continue operation
0950  *      without resetting the card, that's why %AR5K_INT_FATAL is not
0951  *      common for all chips.
0952  * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
0953  *
0954  * @AR5K_INT_TXOK: Frame transmission success
0955  * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
0956  * @AR5K_INT_TXERR: Frame transmission failure
0957  * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
0958  *      Queue Control Unit (QCU) signals an EOL interrupt only if a
0959  *      descriptor's LinkPtr is NULL. For more details, refer to:
0960  *      "http://www.freepatentsonline.com/20030225739.html"
0961  * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
0962  * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
0963  *      increase the TX trigger threshold.
0964  * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
0965  *
0966  * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
0967  *      one of the PHY error counters reached the maximum value and
0968  *      should be read and cleared.
0969  * @AR5K_INT_SWI: Software triggered interrupt.
0970  * @AR5K_INT_RXPHY: RX PHY Error
0971  * @AR5K_INT_RXKCM: RX Key cache miss
0972  * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
0973  *      beacon that must be handled in software. The alternative is if
0974  *      you have VEOL support, in that case you let the hardware deal
0975  *      with things.
0976  * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
0977  * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
0978  *      beacons from the AP have associated with, we should probably
0979  *      try to reassociate. When in IBSS mode this might mean we have
0980  *      not received any beacons from any local stations. Note that
0981  *      every station in an IBSS schedules to send beacons at the
0982  *      Target Beacon Transmission Time (TBTT) with a random backoff.
0983  * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
0984  * @AR5K_INT_TIM: Beacon with local station's TIM bit set
0985  * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
0986  * @AR5K_INT_DTIM_SYNC: DTIM sync lost
0987  * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
0988  *      our GPIO pins.
0989  * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
0990  * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
0991  *      nothing or an incomplete CAB frame sequence.
0992  * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
0993  * @AR5K_INT_QCBRURN: A queue got triggered wile empty
0994  * @AR5K_INT_QTRIG: A queue got triggered
0995  *
0996  * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
0997  *      errors. Indicates we need to reset the card.
0998  * @AR5K_INT_GLOBAL: Used to clear and set the IER
0999  * @AR5K_INT_NOCARD: Signals the card has been removed
1000  * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
1001  *      bit value
1002  *
1003  * These are mapped to take advantage of some common bits
1004  * between the MACs, to be able to set intr properties
1005  * easier. Some of them are not used yet inside hw.c. Most map
1006  * to the respective hw interrupt value as they are common among different
1007  * MACs.
1008  */
1009 enum ath5k_int {
1010     AR5K_INT_RXOK   = 0x00000001,
1011     AR5K_INT_RXDESC = 0x00000002,
1012     AR5K_INT_RXERR  = 0x00000004,
1013     AR5K_INT_RXNOFRM = 0x00000008,
1014     AR5K_INT_RXEOL  = 0x00000010,
1015     AR5K_INT_RXORN  = 0x00000020,
1016     AR5K_INT_TXOK   = 0x00000040,
1017     AR5K_INT_TXDESC = 0x00000080,
1018     AR5K_INT_TXERR  = 0x00000100,
1019     AR5K_INT_TXNOFRM = 0x00000200,
1020     AR5K_INT_TXEOL  = 0x00000400,
1021     AR5K_INT_TXURN  = 0x00000800,
1022     AR5K_INT_MIB    = 0x00001000,
1023     AR5K_INT_SWI    = 0x00002000,
1024     AR5K_INT_RXPHY  = 0x00004000,
1025     AR5K_INT_RXKCM  = 0x00008000,
1026     AR5K_INT_SWBA   = 0x00010000,
1027     AR5K_INT_BRSSI  = 0x00020000,
1028     AR5K_INT_BMISS  = 0x00040000,
1029     AR5K_INT_FATAL  = 0x00080000, /* Non common */
1030     AR5K_INT_BNR    = 0x00100000, /* Non common */
1031     AR5K_INT_TIM    = 0x00200000, /* Non common */
1032     AR5K_INT_DTIM   = 0x00400000, /* Non common */
1033     AR5K_INT_DTIM_SYNC =    0x00800000, /* Non common */
1034     AR5K_INT_GPIO   =   0x01000000,
1035     AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
1036     AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
1037     AR5K_INT_QCBRORN =  0x08000000, /* Non common */
1038     AR5K_INT_QCBRURN =  0x10000000, /* Non common */
1039     AR5K_INT_QTRIG  =   0x20000000, /* Non common */
1040     AR5K_INT_GLOBAL =   0x80000000,
1041 
1042     AR5K_INT_TX_ALL = AR5K_INT_TXOK
1043         | AR5K_INT_TXDESC
1044         | AR5K_INT_TXERR
1045         | AR5K_INT_TXNOFRM
1046         | AR5K_INT_TXEOL
1047         | AR5K_INT_TXURN,
1048 
1049     AR5K_INT_RX_ALL = AR5K_INT_RXOK
1050         | AR5K_INT_RXDESC
1051         | AR5K_INT_RXERR
1052         | AR5K_INT_RXNOFRM
1053         | AR5K_INT_RXEOL
1054         | AR5K_INT_RXORN,
1055 
1056     AR5K_INT_COMMON  = AR5K_INT_RXOK
1057         | AR5K_INT_RXDESC
1058         | AR5K_INT_RXERR
1059         | AR5K_INT_RXNOFRM
1060         | AR5K_INT_RXEOL
1061         | AR5K_INT_RXORN
1062         | AR5K_INT_TXOK
1063         | AR5K_INT_TXDESC
1064         | AR5K_INT_TXERR
1065         | AR5K_INT_TXNOFRM
1066         | AR5K_INT_TXEOL
1067         | AR5K_INT_TXURN
1068         | AR5K_INT_MIB
1069         | AR5K_INT_SWI
1070         | AR5K_INT_RXPHY
1071         | AR5K_INT_RXKCM
1072         | AR5K_INT_SWBA
1073         | AR5K_INT_BRSSI
1074         | AR5K_INT_BMISS
1075         | AR5K_INT_GPIO
1076         | AR5K_INT_GLOBAL,
1077 
1078     AR5K_INT_NOCARD = 0xffffffff
1079 };
1080 
1081 /**
1082  * enum ath5k_calibration_mask - Mask which calibration is active at the moment
1083  * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
1084  * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
1085  * @AR5K_CALIBRATION_NF: Noise Floor calibration
1086  * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
1087  */
1088 enum ath5k_calibration_mask {
1089     AR5K_CALIBRATION_FULL = 0x01,
1090     AR5K_CALIBRATION_SHORT = 0x02,
1091     AR5K_CALIBRATION_NF = 0x04,
1092     AR5K_CALIBRATION_ANI = 0x08,
1093 };
1094 
1095 /**
1096  * enum ath5k_power_mode - Power management modes
1097  * @AR5K_PM_UNDEFINED: Undefined
1098  * @AR5K_PM_AUTO: Allow card to sleep if possible
1099  * @AR5K_PM_AWAKE: Force card to wake up
1100  * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
1101  * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
1102  *
1103  * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
1104  * are also known to have problems on some cards. This is not a big
1105  * problem though because we can have almost the same effect as
1106  * FULL_SLEEP by putting card on warm reset (it's almost powered down).
1107  */
1108 enum ath5k_power_mode {
1109     AR5K_PM_UNDEFINED = 0,
1110     AR5K_PM_AUTO,
1111     AR5K_PM_AWAKE,
1112     AR5K_PM_FULL_SLEEP,
1113     AR5K_PM_NETWORK_SLEEP,
1114 };
1115 
1116 /*
1117  * These match net80211 definitions (not used in
1118  * mac80211).
1119  * TODO: Clean this up
1120  */
1121 #define AR5K_LED_INIT   0 /*IEEE80211_S_INIT*/
1122 #define AR5K_LED_SCAN   1 /*IEEE80211_S_SCAN*/
1123 #define AR5K_LED_AUTH   2 /*IEEE80211_S_AUTH*/
1124 #define AR5K_LED_ASSOC  3 /*IEEE80211_S_ASSOC*/
1125 #define AR5K_LED_RUN    4 /*IEEE80211_S_RUN*/
1126 
1127 /* GPIO-controlled software LED */
1128 #define AR5K_SOFTLED_PIN    0
1129 #define AR5K_SOFTLED_ON     0
1130 #define AR5K_SOFTLED_OFF    1
1131 
1132 
1133 /* XXX: we *may* move cap_range stuff to struct wiphy */
1134 struct ath5k_capabilities {
1135     /*
1136      * Supported PHY modes
1137      * (ie. AR5K_MODE_11A, AR5K_MODE_11B, ...)
1138      */
1139     DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
1140 
1141     /*
1142      * Frequency range (without regulation restrictions)
1143      */
1144     struct {
1145         u16 range_2ghz_min;
1146         u16 range_2ghz_max;
1147         u16 range_5ghz_min;
1148         u16 range_5ghz_max;
1149     } cap_range;
1150 
1151     /*
1152      * Values stored in the EEPROM (some of them...)
1153      */
1154     struct ath5k_eeprom_info    cap_eeprom;
1155 
1156     /*
1157      * Queue information
1158      */
1159     struct {
1160         u8  q_tx_num;
1161     } cap_queues;
1162 
1163     bool cap_has_phyerr_counters;
1164     bool cap_has_mrr_support;
1165     bool cap_needs_2GHz_ovr;
1166 };
1167 
1168 /* size of noise floor history (keep it a power of two) */
1169 #define ATH5K_NF_CAL_HIST_MAX   8
1170 struct ath5k_nfcal_hist {
1171     s16 index;              /* current index into nfval */
1172     s16 nfval[ATH5K_NF_CAL_HIST_MAX];   /* last few noise floors */
1173 };
1174 
1175 #define ATH5K_LED_MAX_NAME_LEN 31
1176 
1177 /*
1178  * State for LED triggers
1179  */
1180 struct ath5k_led {
1181     char name[ATH5K_LED_MAX_NAME_LEN + 1];  /* name of the LED in sysfs */
1182     struct ath5k_hw *ah;            /* driver state */
1183     struct led_classdev led_dev;        /* led classdev */
1184 };
1185 
1186 /* Rfkill */
1187 struct ath5k_rfkill {
1188     /* GPIO PIN for rfkill */
1189     u16 gpio;
1190     /* polarity of rfkill GPIO PIN */
1191     bool polarity;
1192     /* RFKILL toggle tasklet */
1193     struct tasklet_struct toggleq;
1194 };
1195 
1196 /* statistics */
1197 struct ath5k_statistics {
1198     /* antenna use */
1199     unsigned int antenna_rx[5]; /* frames count per antenna RX */
1200     unsigned int antenna_tx[5]; /* frames count per antenna TX */
1201 
1202     /* frame errors */
1203     unsigned int rx_all_count;  /* all RX frames, including errors */
1204     unsigned int tx_all_count;  /* all TX frames, including errors */
1205     unsigned int rx_bytes_count;    /* all RX bytes, including errored pkts
1206                      * and the MAC headers for each packet
1207                      */
1208     unsigned int tx_bytes_count;    /* all TX bytes, including errored pkts
1209                      * and the MAC headers and padding for
1210                      * each packet.
1211                      */
1212     unsigned int rxerr_crc;
1213     unsigned int rxerr_phy;
1214     unsigned int rxerr_phy_code[32];
1215     unsigned int rxerr_fifo;
1216     unsigned int rxerr_decrypt;
1217     unsigned int rxerr_mic;
1218     unsigned int rxerr_proc;
1219     unsigned int rxerr_jumbo;
1220     unsigned int txerr_retry;
1221     unsigned int txerr_fifo;
1222     unsigned int txerr_filt;
1223 
1224     /* MIB counters */
1225     unsigned int ack_fail;
1226     unsigned int rts_fail;
1227     unsigned int rts_ok;
1228     unsigned int fcs_error;
1229     unsigned int beacons;
1230 
1231     unsigned int mib_intr;
1232     unsigned int rxorn_intr;
1233     unsigned int rxeol_intr;
1234 };
1235 
1236 /*
1237  * Misc defines
1238  */
1239 
1240 #define AR5K_MAX_GPIO       10
1241 #define AR5K_MAX_RF_BANKS   8
1242 
1243 #if CHAN_DEBUG
1244 #define ATH_CHAN_MAX    (26 + 26 + 26 + 200 + 200)
1245 #else
1246 #define ATH_CHAN_MAX    (14 + 14 + 14 + 252 + 20)
1247 #endif
1248 
1249 #define ATH_RXBUF   40      /* number of RX buffers */
1250 #define ATH_TXBUF   200     /* number of TX buffers */
1251 #define ATH_BCBUF   4       /* number of beacon buffers */
1252 #define ATH5K_TXQ_LEN_MAX   (ATH_TXBUF / 4)     /* bufs per queue */
1253 #define ATH5K_TXQ_LEN_LOW   (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
1254 
1255 DECLARE_EWMA(beacon_rssi, 10, 8)
1256 
1257 /* Driver state associated with an instance of a device */
1258 struct ath5k_hw {
1259     struct ath_common       common;
1260 
1261     struct pci_dev      *pdev;
1262     struct device       *dev;       /* for dma mapping */
1263     int irq;
1264     u16 devid;
1265     void __iomem        *iobase;    /* address of the device */
1266     struct mutex        lock;       /* dev-level lock */
1267     struct ieee80211_hw *hw;        /* IEEE 802.11 common */
1268     struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
1269     struct ieee80211_channel channels[ATH_CHAN_MAX];
1270     struct ieee80211_rate   rates[NUM_NL80211_BANDS][AR5K_MAX_RATES];
1271     s8          rate_idx[NUM_NL80211_BANDS][AR5K_MAX_RATES];
1272     enum nl80211_iftype opmode;
1273 
1274 #ifdef CONFIG_ATH5K_DEBUG
1275     struct ath5k_dbg_info   debug;      /* debug info */
1276 #endif /* CONFIG_ATH5K_DEBUG */
1277 
1278     struct ath5k_buf    *bufptr;    /* allocated buffer ptr */
1279     struct ath5k_desc   *desc;      /* TX/RX descriptors */
1280     dma_addr_t      desc_daddr; /* DMA (physical) address */
1281     size_t          desc_len;   /* size of TX/RX descriptors */
1282 
1283     DECLARE_BITMAP(status, 4);
1284 #define ATH_STAT_INVALID    0       /* disable hardware accesses */
1285 #define ATH_STAT_LEDSOFT    2       /* enable LED gpio status */
1286 #define ATH_STAT_STARTED    3       /* opened & irqs enabled */
1287 #define ATH_STAT_RESET      4       /* hw reset */
1288 
1289     unsigned int        filter_flags;   /* HW flags, AR5K_RX_FILTER_* */
1290     unsigned int        fif_filter_flags; /* Current FIF_* filter flags */
1291     struct ieee80211_channel *curchan;  /* current h/w channel */
1292 
1293     u16         nvifs;
1294 
1295     enum ath5k_int      imask;      /* interrupt mask copy */
1296 
1297     spinlock_t      irqlock;
1298     bool            rx_pending; /* rx tasklet pending */
1299     bool            tx_pending; /* tx tasklet pending */
1300 
1301     u8          bssidmask[ETH_ALEN];
1302 
1303     unsigned int        led_pin,    /* GPIO pin for driving LED */
1304                 led_on;     /* pin setting for LED on */
1305 
1306     struct work_struct  reset_work; /* deferred chip reset */
1307     struct work_struct  calib_work; /* deferred phy calibration */
1308 
1309     struct list_head    rxbuf;      /* receive buffer */
1310     spinlock_t      rxbuflock;
1311     u32         *rxlink;    /* link ptr in last RX desc */
1312     struct tasklet_struct   rxtq;       /* rx intr tasklet */
1313     struct ath5k_led    rx_led;     /* rx led */
1314 
1315     struct list_head    txbuf;      /* transmit buffer */
1316     spinlock_t      txbuflock;
1317     unsigned int        txbuf_len;  /* buf count in txbuf list */
1318     struct ath5k_txq    txqs[AR5K_NUM_TX_QUEUES];   /* tx queues */
1319     struct tasklet_struct   txtq;       /* tx intr tasklet */
1320     struct ath5k_led    tx_led;     /* tx led */
1321 
1322     struct ath5k_rfkill rf_kill;
1323 
1324     spinlock_t      block;      /* protects beacon */
1325     struct tasklet_struct   beacontq;   /* beacon intr tasklet */
1326     struct list_head    bcbuf;      /* beacon buffer */
1327     struct ieee80211_vif    *bslot[ATH_BCBUF];
1328     u16         num_ap_vifs;
1329     u16         num_adhoc_vifs;
1330     u16         num_mesh_vifs;
1331     unsigned int        bhalq,      /* SW q for outgoing beacons */
1332                 bmisscount, /* missed beacon transmits */
1333                 bintval,    /* beacon interval in TU */
1334                 bsent;
1335     unsigned int        nexttbtt;   /* next beacon time in TU */
1336     struct ath5k_txq    *cabq;      /* content after beacon */
1337 
1338     bool            assoc;      /* associate state */
1339     bool            enable_beacon;  /* true if beacons are on */
1340 
1341     struct ath5k_statistics stats;
1342 
1343     struct ath5k_ani_state  ani_state;
1344     struct tasklet_struct   ani_tasklet;    /* ANI calibration */
1345 
1346     struct delayed_work tx_complete_work;
1347 
1348     struct survey_info  survey;     /* collected survey info */
1349 
1350     enum ath5k_int      ah_imr;
1351 
1352     struct ieee80211_channel *ah_current_channel;
1353     bool            ah_iq_cal_needed;
1354     bool            ah_single_chip;
1355 
1356     enum ath5k_version  ah_version;
1357     enum ath5k_radio    ah_radio;
1358     u32         ah_mac_srev;
1359     u16         ah_mac_version;
1360     u16         ah_phy_revision;
1361     u16         ah_radio_5ghz_revision;
1362     u16         ah_radio_2ghz_revision;
1363 
1364 #define ah_modes        ah_capabilities.cap_mode
1365 #define ah_ee_version       ah_capabilities.cap_eeprom.ee_version
1366 
1367     u8          ah_retry_long;
1368     u8          ah_retry_short;
1369 
1370     bool            ah_use_32khz_clock;
1371 
1372     u8          ah_coverage_class;
1373     bool            ah_ack_bitrate_high;
1374     u8          ah_bwmode;
1375     bool            ah_short_slot;
1376 
1377     /* Antenna Control */
1378     u32         ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1379     u8          ah_ant_mode;
1380     u8          ah_tx_ant;
1381     u8          ah_def_ant;
1382 
1383     struct ath5k_capabilities ah_capabilities;
1384 
1385     struct ath5k_txq_info   ah_txq[AR5K_NUM_TX_QUEUES];
1386     u32         ah_txq_status;
1387     u32         ah_txq_imr_txok;
1388     u32         ah_txq_imr_txerr;
1389     u32         ah_txq_imr_txurn;
1390     u32         ah_txq_imr_txdesc;
1391     u32         ah_txq_imr_txeol;
1392     u32         ah_txq_imr_cbrorn;
1393     u32         ah_txq_imr_cbrurn;
1394     u32         ah_txq_imr_qtrig;
1395     u32         ah_txq_imr_nofrm;
1396 
1397     u32         ah_txq_isr_txok_all;
1398 
1399     u32         *ah_rf_banks;
1400     size_t          ah_rf_banks_size;
1401     size_t          ah_rf_regs_count;
1402     struct ath5k_gain   ah_gain;
1403     u8          ah_offset[AR5K_MAX_RF_BANKS];
1404 
1405 
1406     struct {
1407         /* Temporary tables used for interpolation */
1408         u8      tmpL[AR5K_EEPROM_N_PD_GAINS]
1409                     [AR5K_EEPROM_POWER_TABLE_SIZE];
1410         u8      tmpR[AR5K_EEPROM_N_PD_GAINS]
1411                     [AR5K_EEPROM_POWER_TABLE_SIZE];
1412         u8      txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1413         u16     txp_rates_power_table[AR5K_MAX_RATES];
1414         u8      txp_min_idx;
1415         bool        txp_tpc;
1416         /* Values in 0.25dB units */
1417         s16     txp_min_pwr;
1418         s16     txp_max_pwr;
1419         s16     txp_cur_pwr;
1420         /* Values in 0.5dB units */
1421         s16     txp_offset;
1422         s16     txp_ofdm;
1423         s16     txp_cck_ofdm_gainf_delta;
1424         /* Value in dB units */
1425         s16     txp_cck_ofdm_pwr_delta;
1426         bool        txp_setup;
1427         int     txp_requested;  /* Requested tx power in dBm */
1428     } ah_txpower;
1429 
1430     struct ath5k_nfcal_hist ah_nfcal_hist;
1431 
1432     /* average beacon RSSI in our BSS (used by ANI) */
1433     struct ewma_beacon_rssi ah_beacon_rssi_avg;
1434 
1435     /* noise floor from last periodic calibration */
1436     s32         ah_noise_floor;
1437 
1438     /* Calibration timestamp */
1439     unsigned long       ah_cal_next_full;
1440     unsigned long       ah_cal_next_short;
1441     unsigned long       ah_cal_next_ani;
1442 
1443     /* Calibration mask */
1444     u8          ah_cal_mask;
1445 
1446     /*
1447      * Function pointers
1448      */
1449     int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1450         unsigned int, unsigned int, int, enum ath5k_pkt_type,
1451         unsigned int, unsigned int, unsigned int, unsigned int,
1452         unsigned int, unsigned int, unsigned int, unsigned int);
1453     int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1454         struct ath5k_tx_status *);
1455     int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1456         struct ath5k_rx_status *);
1457 };
1458 
1459 struct ath_bus_ops {
1460     enum ath_bus_type ath_bus_type;
1461     void (*read_cachesize)(struct ath_common *common, int *csz);
1462     bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
1463     int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
1464 };
1465 
1466 /*
1467  * Prototypes
1468  */
1469 extern const struct ieee80211_ops ath5k_hw_ops;
1470 
1471 /* Initialization and detach functions */
1472 int ath5k_hw_init(struct ath5k_hw *ah);
1473 void ath5k_hw_deinit(struct ath5k_hw *ah);
1474 
1475 int ath5k_sysfs_register(struct ath5k_hw *ah);
1476 void ath5k_sysfs_unregister(struct ath5k_hw *ah);
1477 
1478 /*Chip id helper functions */
1479 int ath5k_hw_read_srev(struct ath5k_hw *ah);
1480 
1481 /* LED functions */
1482 int ath5k_init_leds(struct ath5k_hw *ah);
1483 void ath5k_led_enable(struct ath5k_hw *ah);
1484 void ath5k_led_off(struct ath5k_hw *ah);
1485 void ath5k_unregister_leds(struct ath5k_hw *ah);
1486 
1487 
1488 /* Reset Functions */
1489 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1490 int ath5k_hw_on_hold(struct ath5k_hw *ah);
1491 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1492        struct ieee80211_channel *channel, bool fast, bool skip_pcu);
1493 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1494                   bool is_set);
1495 /* Power management functions */
1496 
1497 
1498 /* Clock rate related functions */
1499 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1500 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1501 void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
1502 
1503 
1504 /* DMA Related Functions */
1505 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1506 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1507 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1508 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1509 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
1510 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1511 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1512                 u32 phys_addr);
1513 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1514 /* Interrupt handling */
1515 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1516 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1517 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1518 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
1519 /* Init/Stop functions */
1520 void ath5k_hw_dma_init(struct ath5k_hw *ah);
1521 int ath5k_hw_dma_stop(struct ath5k_hw *ah);
1522 
1523 /* EEPROM access functions */
1524 int ath5k_eeprom_init(struct ath5k_hw *ah);
1525 void ath5k_eeprom_detach(struct ath5k_hw *ah);
1526 int ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah,
1527         struct ieee80211_channel *channel);
1528 
1529 /* Protocol Control Unit Functions */
1530 /* Helpers */
1531 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum nl80211_band band,
1532         int len, struct ieee80211_rate *rate, bool shortpre);
1533 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
1534 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
1535 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1536 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1537 /* RX filter control*/
1538 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1539 void ath5k_hw_set_bssid(struct ath5k_hw *ah);
1540 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1541 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1542 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1543 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1544 /* Receive (DRU) start/stop functions */
1545 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1546 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1547 /* Beacon control functions */
1548 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1549 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1550 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1551 void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
1552                             u32 interval);
1553 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
1554 /* Init function */
1555 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
1556 
1557 /* Queue Control Unit, DFS Control Unit Functions */
1558 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1559                    struct ath5k_txq_info *queue_info);
1560 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1561                    const struct ath5k_txq_info *queue_info);
1562 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1563                 enum ath5k_tx_queue queue_type,
1564                 struct ath5k_txq_info *queue_info);
1565 void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
1566                   unsigned int queue);
1567 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1568 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1569 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1570 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
1571 /* Init function */
1572 int ath5k_hw_init_queues(struct ath5k_hw *ah);
1573 
1574 /* Hardware Descriptor Functions */
1575 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1576 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1577                u32 size, unsigned int flags);
1578 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
1579     unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
1580     u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
1581 
1582 
1583 /* GPIO Functions */
1584 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1585 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1586 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1587 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1588 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1589 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1590                 u32 interrupt_level);
1591 
1592 
1593 /* RFkill Functions */
1594 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1595 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1596 
1597 
1598 /* Misc functions TODO: Cleanup */
1599 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1600 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1601 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1602 
1603 
1604 /* Initial register settings functions */
1605 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1606 
1607 
1608 /* PHY functions */
1609 /* Misc PHY functions */
1610 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum nl80211_band band);
1611 int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1612 /* Gain_F optimization */
1613 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1614 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1615 /* PHY/RF channel functions */
1616 bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1617 /* PHY calibration */
1618 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1619 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1620                struct ieee80211_channel *channel);
1621 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
1622 /* Spur mitigation */
1623 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1624                   struct ieee80211_channel *channel);
1625 /* Antenna control */
1626 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1627 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
1628 /* TX power setup */
1629 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1630 /* Init function */
1631 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1632                 u8 mode, bool fast);
1633 
1634 /*
1635  * Functions used internally
1636  */
1637 
1638 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1639 {
1640     return &ah->common;
1641 }
1642 
1643 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1644 {
1645     return &(ath5k_hw_common(ah)->regulatory);
1646 }
1647 
1648 #ifdef CONFIG_ATH5K_AHB
1649 #define AR5K_AR2315_PCI_BASE    ((void __iomem *)0xb0100000)
1650 
1651 static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
1652 {
1653     /* On AR2315 and AR2317 the PCI clock domain registers
1654      * are outside of the WMAC register space */
1655     if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
1656         (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
1657         return AR5K_AR2315_PCI_BASE + reg;
1658 
1659     return ah->iobase + reg;
1660 }
1661 
1662 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1663 {
1664     return ioread32(ath5k_ahb_reg(ah, reg));
1665 }
1666 
1667 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1668 {
1669     iowrite32(val, ath5k_ahb_reg(ah, reg));
1670 }
1671 
1672 #else
1673 
1674 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1675 {
1676     return ioread32(ah->iobase + reg);
1677 }
1678 
1679 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1680 {
1681     iowrite32(val, ah->iobase + reg);
1682 }
1683 
1684 #endif
1685 
1686 static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
1687 {
1688     return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
1689 }
1690 
1691 static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
1692 {
1693     common->bus_ops->read_cachesize(common, csz);
1694 }
1695 
1696 static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
1697 {
1698     struct ath_common *common = ath5k_hw_common(ah);
1699     return common->bus_ops->eeprom_read(common, off, data);
1700 }
1701 
1702 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1703 {
1704     u32 retval = 0, bit, i;
1705 
1706     for (i = 0; i < bits; i++) {
1707         bit = (val >> i) & 1;
1708         retval = (retval << 1) | bit;
1709     }
1710 
1711     return retval;
1712 }
1713 
1714 #endif
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