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0001 // SPDX-License-Identifier: BSD-3-Clause-Clear
0002 /*
0003  * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved.
0004  * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
0005  */
0006 
0007 #include <linux/module.h>
0008 #include <linux/msi.h>
0009 #include <linux/pci.h>
0010 #include <linux/of.h>
0011 
0012 #include "pci.h"
0013 #include "core.h"
0014 #include "hif.h"
0015 #include "mhi.h"
0016 #include "debug.h"
0017 #include "pcic.h"
0018 
0019 #define ATH11K_PCI_BAR_NUM      0
0020 #define ATH11K_PCI_DMA_MASK     32
0021 
0022 #define TCSR_SOC_HW_VERSION     0x0224
0023 #define TCSR_SOC_HW_VERSION_MAJOR_MASK  GENMASK(11, 8)
0024 #define TCSR_SOC_HW_VERSION_MINOR_MASK  GENMASK(7, 0)
0025 
0026 #define QCA6390_DEVICE_ID       0x1101
0027 #define QCN9074_DEVICE_ID       0x1104
0028 #define WCN6855_DEVICE_ID       0x1103
0029 
0030 static const struct pci_device_id ath11k_pci_id_table[] = {
0031     { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
0032     { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
0033     { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
0034     {0}
0035 };
0036 
0037 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
0038 
0039 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab)
0040 {
0041     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0042 
0043     return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
0044 }
0045 
0046 static void ath11k_pci_bus_release(struct ath11k_base *ab)
0047 {
0048     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0049 
0050     mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
0051 }
0052 
0053 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset)
0054 {
0055     if (!ab->hw_params.static_window_map)
0056         return ATH11K_PCI_WINDOW_START;
0057 
0058     if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK)
0059         /* if offset lies within DP register range, use 3rd window */
0060         return 3 * ATH11K_PCI_WINDOW_START;
0061     else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) <
0062          ATH11K_PCI_WINDOW_RANGE_MASK)
0063          /* if offset lies within CE register range, use 2nd window */
0064         return 2 * ATH11K_PCI_WINDOW_START;
0065     else
0066         return ATH11K_PCI_WINDOW_START;
0067 }
0068 
0069 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
0070 {
0071     struct ath11k_base *ab = ab_pci->ab;
0072 
0073     u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset);
0074 
0075     lockdep_assert_held(&ab_pci->window_lock);
0076 
0077     if (window != ab_pci->register_window) {
0078         iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
0079               ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
0080         ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
0081         ab_pci->register_window = window;
0082     }
0083 }
0084 
0085 static void
0086 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value)
0087 {
0088     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0089     u32 window_start;
0090 
0091     window_start = ath11k_pci_get_window_start(ab, offset);
0092 
0093     if (window_start == ATH11K_PCI_WINDOW_START) {
0094         spin_lock_bh(&ab_pci->window_lock);
0095         ath11k_pci_select_window(ab_pci, offset);
0096         iowrite32(value, ab->mem + window_start +
0097               (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
0098         spin_unlock_bh(&ab_pci->window_lock);
0099     } else {
0100         iowrite32(value, ab->mem + window_start +
0101               (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
0102     }
0103 }
0104 
0105 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset)
0106 {
0107     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0108     u32 window_start, val;
0109 
0110     window_start = ath11k_pci_get_window_start(ab, offset);
0111 
0112     if (window_start == ATH11K_PCI_WINDOW_START) {
0113         spin_lock_bh(&ab_pci->window_lock);
0114         ath11k_pci_select_window(ab_pci, offset);
0115         val = ioread32(ab->mem + window_start +
0116                    (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
0117         spin_unlock_bh(&ab_pci->window_lock);
0118     } else {
0119         val = ioread32(ab->mem + window_start +
0120                    (offset & ATH11K_PCI_WINDOW_RANGE_MASK));
0121     }
0122 
0123     return val;
0124 }
0125 
0126 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector)
0127 {
0128     struct pci_dev *pci_dev = to_pci_dev(ab->dev);
0129 
0130     return pci_irq_vector(pci_dev, vector);
0131 }
0132 
0133 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = {
0134     .wakeup = ath11k_pci_bus_wake_up,
0135     .release = ath11k_pci_bus_release,
0136     .get_msi_irq = ath11k_pci_get_msi_irq,
0137     .window_write32 = ath11k_pci_window_write32,
0138     .window_read32 = ath11k_pci_window_read32,
0139 };
0140 
0141 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = {
0142     .wakeup = NULL,
0143     .release = NULL,
0144     .get_msi_irq = ath11k_pci_get_msi_irq,
0145     .window_write32 = ath11k_pci_window_write32,
0146     .window_read32 = ath11k_pci_window_read32,
0147 };
0148 
0149 static const struct ath11k_msi_config msi_config_one_msi = {
0150     .total_vectors = 1,
0151     .total_users = 4,
0152     .users = (struct ath11k_msi_user[]) {
0153         { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
0154         { .name = "CE", .num_vectors = 1, .base_vector = 0 },
0155         { .name = "WAKE", .num_vectors = 1, .base_vector = 0 },
0156         { .name = "DP", .num_vectors = 1, .base_vector = 0 },
0157     },
0158 };
0159 
0160 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
0161 {
0162     u32 umac_window;
0163     u32 ce_window;
0164     u32 window;
0165 
0166     umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
0167     ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
0168     window = (umac_window << 12) | (ce_window << 6);
0169 
0170     iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window,
0171           ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS);
0172 }
0173 
0174 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
0175 {
0176     u32 val, delay;
0177 
0178     val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
0179 
0180     val |= PCIE_SOC_GLOBAL_RESET_V;
0181 
0182     ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
0183 
0184     /* TODO: exact time to sleep is uncertain */
0185     delay = 10;
0186     mdelay(delay);
0187 
0188     /* Need to toggle V bit back otherwise stuck in reset status */
0189     val &= ~PCIE_SOC_GLOBAL_RESET_V;
0190 
0191     ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
0192 
0193     mdelay(delay);
0194 
0195     val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET);
0196     if (val == 0xffffffff)
0197         ath11k_warn(ab, "link down error during global reset\n");
0198 }
0199 
0200 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
0201 {
0202     u32 val;
0203 
0204     /* read cookie */
0205     val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR);
0206     ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val);
0207 
0208     val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
0209     ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
0210 
0211     /* TODO: exact time to sleep is uncertain */
0212     mdelay(10);
0213 
0214     /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from
0215      * continuing warm path and entering dead loop.
0216      */
0217     ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0);
0218     mdelay(10);
0219 
0220     val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY);
0221     ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
0222 
0223     /* A read clear register. clear the register to prevent
0224      * Q6 from entering wrong code path.
0225      */
0226     val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
0227     ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val);
0228 }
0229 
0230 static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
0231                    u32 offset, u32 value, u32 mask)
0232 {
0233     u32 v;
0234     int i;
0235 
0236     v = ath11k_pcic_read32(ab, offset);
0237     if ((v & mask) == value)
0238         return 0;
0239 
0240     for (i = 0; i < 10; i++) {
0241         ath11k_pcic_write32(ab, offset, (v & ~mask) | value);
0242 
0243         v = ath11k_pcic_read32(ab, offset);
0244         if ((v & mask) == value)
0245             return 0;
0246 
0247         mdelay(2);
0248     }
0249 
0250     ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
0251             offset, v & mask, value);
0252 
0253     return -ETIMEDOUT;
0254 }
0255 
0256 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
0257 {
0258     int ret;
0259 
0260     ret = ath11k_pci_set_link_reg(ab,
0261                       PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
0262                       PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
0263                       PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
0264     if (ret) {
0265         ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
0266         return ret;
0267     }
0268 
0269     ret = ath11k_pci_set_link_reg(ab,
0270                       PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
0271                       PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
0272                       PCIE_PCS_OSC_DTCT_CONFIG_MSK);
0273     if (ret) {
0274         ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
0275         return ret;
0276     }
0277 
0278     ret = ath11k_pci_set_link_reg(ab,
0279                       PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
0280                       PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
0281                       PCIE_PCS_OSC_DTCT_CONFIG_MSK);
0282     if (ret) {
0283         ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
0284         return ret;
0285     }
0286 
0287     ret = ath11k_pci_set_link_reg(ab,
0288                       PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
0289                       PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
0290                       PCIE_PCS_OSC_DTCT_CONFIG_MSK);
0291     if (ret) {
0292         ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
0293         return ret;
0294     }
0295 
0296     return 0;
0297 }
0298 
0299 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
0300 {
0301     u32 val;
0302     int i;
0303 
0304     val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
0305 
0306     /* PCIE link seems very unstable after the Hot Reset*/
0307     for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
0308         if (val == 0xffffffff)
0309             mdelay(5);
0310 
0311         ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
0312         val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM);
0313     }
0314 
0315     ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val);
0316 
0317     val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
0318     val |= GCC_GCC_PCIE_HOT_RST_VAL;
0319     ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
0320     val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST);
0321 
0322     ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
0323 
0324     mdelay(5);
0325 }
0326 
0327 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
0328 {
0329     /* This is a WAR for PCIE Hotreset.
0330      * When target receive Hotreset, but will set the interrupt.
0331      * So when download SBL again, SBL will open Interrupt and
0332      * receive it, and crash immediately.
0333      */
0334     ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
0335 }
0336 
0337 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
0338 {
0339     u32 val;
0340 
0341     val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
0342     val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
0343     ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
0344 }
0345 
0346 static void ath11k_pci_force_wake(struct ath11k_base *ab)
0347 {
0348     ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
0349     mdelay(5);
0350 }
0351 
0352 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
0353 {
0354     mdelay(100);
0355 
0356     if (power_on) {
0357         ath11k_pci_enable_ltssm(ab);
0358         ath11k_pci_clear_all_intrs(ab);
0359         ath11k_pci_set_wlaon_pwr_ctrl(ab);
0360         if (ab->hw_params.fix_l1ss)
0361             ath11k_pci_fix_l1ss(ab);
0362     }
0363 
0364     ath11k_mhi_clear_vector(ab);
0365     ath11k_pci_clear_dbg_registers(ab);
0366     ath11k_pci_soc_global_reset(ab);
0367     ath11k_mhi_set_mhictrl_reset(ab);
0368 }
0369 
0370 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
0371 {
0372     struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
0373 
0374     cfg->tgt_ce = ab->hw_params.target_ce_config;
0375     cfg->tgt_ce_len = ab->hw_params.target_ce_count;
0376 
0377     cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
0378     cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
0379     ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
0380 
0381     ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
0382                     &cfg->shadow_reg_v2_len);
0383 }
0384 
0385 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable)
0386 {
0387     struct pci_dev *dev = ab_pci->pdev;
0388     u16 control;
0389 
0390     pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
0391 
0392     if (enable)
0393         control |= PCI_MSI_FLAGS_ENABLE;
0394     else
0395         control &= ~PCI_MSI_FLAGS_ENABLE;
0396 
0397     pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
0398 }
0399 
0400 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci)
0401 {
0402     ath11k_pci_msi_config(ab_pci, true);
0403 }
0404 
0405 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci)
0406 {
0407     ath11k_pci_msi_config(ab_pci, false);
0408 }
0409 
0410 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci)
0411 {
0412     struct ath11k_base *ab = ab_pci->ab;
0413     const struct ath11k_msi_config *msi_config = ab->pci.msi.config;
0414     struct pci_dev *pci_dev = ab_pci->pdev;
0415     struct msi_desc *msi_desc;
0416     int num_vectors;
0417     int ret;
0418 
0419     num_vectors = pci_alloc_irq_vectors(pci_dev,
0420                         msi_config->total_vectors,
0421                         msi_config->total_vectors,
0422                         PCI_IRQ_MSI);
0423     if (num_vectors == msi_config->total_vectors) {
0424         set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
0425     } else {
0426         num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
0427                             1,
0428                             1,
0429                             PCI_IRQ_MSI);
0430         if (num_vectors < 0) {
0431             ret = -EINVAL;
0432             goto reset_msi_config;
0433         }
0434         clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags);
0435         ab->pci.msi.config = &msi_config_one_msi;
0436         ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n");
0437     }
0438     ath11k_info(ab, "MSI vectors: %d\n", num_vectors);
0439 
0440     ath11k_pci_msi_disable(ab_pci);
0441 
0442     msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
0443     if (!msi_desc) {
0444         ath11k_err(ab, "msi_desc is NULL!\n");
0445         ret = -EINVAL;
0446         goto free_msi_vector;
0447     }
0448 
0449     ab->pci.msi.ep_base_data = msi_desc->msg.data;
0450 
0451     pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
0452                   &ab->pci.msi.addr_lo);
0453 
0454     if (msi_desc->pci.msi_attrib.is_64) {
0455         pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
0456                       &ab->pci.msi.addr_hi);
0457     } else {
0458         ab->pci.msi.addr_hi = 0;
0459     }
0460 
0461     ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data);
0462 
0463     return 0;
0464 
0465 free_msi_vector:
0466     pci_free_irq_vectors(ab_pci->pdev);
0467 
0468 reset_msi_config:
0469     return ret;
0470 }
0471 
0472 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci)
0473 {
0474     pci_free_irq_vectors(ab_pci->pdev);
0475 }
0476 
0477 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci)
0478 {
0479     struct msi_desc *msi_desc;
0480 
0481     msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
0482     if (!msi_desc) {
0483         ath11k_err(ab_pci->ab, "msi_desc is NULL!\n");
0484         pci_free_irq_vectors(ab_pci->pdev);
0485         return -EINVAL;
0486     }
0487 
0488     ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data;
0489 
0490     ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n",
0491            ab_pci->ab->pci.msi.ep_base_data);
0492 
0493     return 0;
0494 }
0495 
0496 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
0497 {
0498     struct ath11k_base *ab = ab_pci->ab;
0499     u16 device_id;
0500     int ret = 0;
0501 
0502     pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
0503     if (device_id != ab_pci->dev_id)  {
0504         ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
0505                device_id, ab_pci->dev_id);
0506         ret = -EIO;
0507         goto out;
0508     }
0509 
0510     ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
0511     if (ret) {
0512         ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
0513         goto out;
0514     }
0515 
0516     ret = pci_enable_device(pdev);
0517     if (ret) {
0518         ath11k_err(ab, "failed to enable pci device: %d\n", ret);
0519         goto out;
0520     }
0521 
0522     ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
0523     if (ret) {
0524         ath11k_err(ab, "failed to request pci region: %d\n", ret);
0525         goto disable_device;
0526     }
0527 
0528     ret = dma_set_mask_and_coherent(&pdev->dev,
0529                     DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
0530     if (ret) {
0531         ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
0532                ATH11K_PCI_DMA_MASK, ret);
0533         goto release_region;
0534     }
0535 
0536     pci_set_master(pdev);
0537 
0538     ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
0539     ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
0540     if (!ab->mem) {
0541         ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
0542         ret = -EIO;
0543         goto clear_master;
0544     }
0545 
0546     ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
0547     return 0;
0548 
0549 clear_master:
0550     pci_clear_master(pdev);
0551 release_region:
0552     pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
0553 disable_device:
0554     pci_disable_device(pdev);
0555 out:
0556     return ret;
0557 }
0558 
0559 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
0560 {
0561     struct ath11k_base *ab = ab_pci->ab;
0562     struct pci_dev *pci_dev = ab_pci->pdev;
0563 
0564     pci_iounmap(pci_dev, ab->mem);
0565     ab->mem = NULL;
0566     pci_clear_master(pci_dev);
0567     pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
0568     if (pci_is_enabled(pci_dev))
0569         pci_disable_device(pci_dev);
0570 }
0571 
0572 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
0573 {
0574     struct ath11k_base *ab = ab_pci->ab;
0575 
0576     pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
0577                   &ab_pci->link_ctl);
0578 
0579     ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
0580            ab_pci->link_ctl,
0581            u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
0582            u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
0583 
0584     /* disable L0s and L1 */
0585     pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
0586                    ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
0587 
0588     set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
0589 }
0590 
0591 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
0592 {
0593     if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
0594         pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
0595                        ab_pci->link_ctl);
0596 }
0597 
0598 static int ath11k_pci_power_up(struct ath11k_base *ab)
0599 {
0600     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0601     int ret;
0602 
0603     ab_pci->register_window = 0;
0604     clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
0605     ath11k_pci_sw_reset(ab_pci->ab, true);
0606 
0607     /* Disable ASPM during firmware download due to problems switching
0608      * to AMSS state.
0609      */
0610     ath11k_pci_aspm_disable(ab_pci);
0611 
0612     ath11k_pci_msi_enable(ab_pci);
0613 
0614     ret = ath11k_mhi_start(ab_pci);
0615     if (ret) {
0616         ath11k_err(ab, "failed to start mhi: %d\n", ret);
0617         return ret;
0618     }
0619 
0620     if (ab->hw_params.static_window_map)
0621         ath11k_pci_select_static_window(ab_pci);
0622 
0623     return 0;
0624 }
0625 
0626 static void ath11k_pci_power_down(struct ath11k_base *ab)
0627 {
0628     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0629 
0630     /* restore aspm in case firmware bootup fails */
0631     ath11k_pci_aspm_restore(ab_pci);
0632 
0633     ath11k_pci_force_wake(ab_pci->ab);
0634 
0635     ath11k_pci_msi_disable(ab_pci);
0636 
0637     ath11k_mhi_stop(ab_pci);
0638     clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags);
0639     ath11k_pci_sw_reset(ab_pci->ab, false);
0640 }
0641 
0642 static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
0643 {
0644     struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
0645 
0646     return ath11k_mhi_suspend(ar_pci);
0647 }
0648 
0649 static int ath11k_pci_hif_resume(struct ath11k_base *ab)
0650 {
0651     struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
0652 
0653     return ath11k_mhi_resume(ar_pci);
0654 }
0655 
0656 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
0657 {
0658     ath11k_pcic_ce_irqs_enable(ab);
0659 }
0660 
0661 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
0662 {
0663     ath11k_pcic_ce_irq_disable_sync(ab);
0664 }
0665 
0666 static int ath11k_pci_start(struct ath11k_base *ab)
0667 {
0668     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0669 
0670     /* TODO: for now don't restore ASPM in case of single MSI
0671      * vector as MHI register reading in M2 causes system hang.
0672      */
0673     if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
0674         ath11k_pci_aspm_restore(ab_pci);
0675     else
0676         ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n");
0677 
0678     ath11k_pcic_start(ab);
0679 
0680     return 0;
0681 }
0682 
0683 static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
0684     .start = ath11k_pci_start,
0685     .stop = ath11k_pcic_stop,
0686     .read32 = ath11k_pcic_read32,
0687     .write32 = ath11k_pcic_write32,
0688     .power_down = ath11k_pci_power_down,
0689     .power_up = ath11k_pci_power_up,
0690     .suspend = ath11k_pci_hif_suspend,
0691     .resume = ath11k_pci_hif_resume,
0692     .irq_enable = ath11k_pcic_ext_irq_enable,
0693     .irq_disable = ath11k_pcic_ext_irq_disable,
0694     .get_msi_address =  ath11k_pcic_get_msi_address,
0695     .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment,
0696     .map_service_to_pipe = ath11k_pcic_map_service_to_pipe,
0697     .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
0698     .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
0699     .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx,
0700 };
0701 
0702 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
0703 {
0704     u32 soc_hw_version;
0705 
0706     soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION);
0707     *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
0708                soc_hw_version);
0709     *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
0710                soc_hw_version);
0711 
0712     ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
0713            *major, *minor);
0714 }
0715 
0716 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci,
0717                         const struct cpumask *m)
0718 {
0719     if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags))
0720         return 0;
0721 
0722     return irq_set_affinity_hint(ab_pci->pdev->irq, m);
0723 }
0724 
0725 static int ath11k_pci_probe(struct pci_dev *pdev,
0726                 const struct pci_device_id *pci_dev)
0727 {
0728     struct ath11k_base *ab;
0729     struct ath11k_pci *ab_pci;
0730     u32 soc_hw_version_major, soc_hw_version_minor, addr;
0731     const struct ath11k_pci_ops *pci_ops;
0732     int ret;
0733 
0734     ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI);
0735 
0736     if (!ab) {
0737         dev_err(&pdev->dev, "failed to allocate ath11k base\n");
0738         return -ENOMEM;
0739     }
0740 
0741     ab->dev = &pdev->dev;
0742     pci_set_drvdata(pdev, ab);
0743     ab_pci = ath11k_pci_priv(ab);
0744     ab_pci->dev_id = pci_dev->device;
0745     ab_pci->ab = ab;
0746     ab_pci->pdev = pdev;
0747     ab->hif.ops = &ath11k_pci_hif_ops;
0748     pci_set_drvdata(pdev, ab);
0749     spin_lock_init(&ab_pci->window_lock);
0750 
0751     /* Set fixed_mem_region to true for platforms support reserved memory
0752      * from DT. If memory is reserved from DT for FW, ath11k driver need not
0753      * allocate memory.
0754      */
0755     ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr);
0756     if (!ret)
0757         set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags);
0758 
0759     ret = ath11k_pci_claim(ab_pci, pdev);
0760     if (ret) {
0761         ath11k_err(ab, "failed to claim device: %d\n", ret);
0762         goto err_free_core;
0763     }
0764 
0765     ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n",
0766            pdev->vendor, pdev->device,
0767            pdev->subsystem_vendor, pdev->subsystem_device);
0768 
0769     ab->id.vendor = pdev->vendor;
0770     ab->id.device = pdev->device;
0771     ab->id.subsystem_vendor = pdev->subsystem_vendor;
0772     ab->id.subsystem_device = pdev->subsystem_device;
0773 
0774     switch (pci_dev->device) {
0775     case QCA6390_DEVICE_ID:
0776         ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
0777                        &soc_hw_version_minor);
0778         switch (soc_hw_version_major) {
0779         case 2:
0780             ab->hw_rev = ATH11K_HW_QCA6390_HW20;
0781             break;
0782         default:
0783             dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
0784                 soc_hw_version_major, soc_hw_version_minor);
0785             ret = -EOPNOTSUPP;
0786             goto err_pci_free_region;
0787         }
0788 
0789         pci_ops = &ath11k_pci_ops_qca6390;
0790         break;
0791     case QCN9074_DEVICE_ID:
0792         pci_ops = &ath11k_pci_ops_qcn9074;
0793         ab->hw_rev = ATH11K_HW_QCN9074_HW10;
0794         break;
0795     case WCN6855_DEVICE_ID:
0796         ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD;
0797         ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
0798                        &soc_hw_version_minor);
0799         switch (soc_hw_version_major) {
0800         case 2:
0801             switch (soc_hw_version_minor) {
0802             case 0x00:
0803             case 0x01:
0804                 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
0805                 break;
0806             case 0x10:
0807             case 0x11:
0808                 ab->hw_rev = ATH11K_HW_WCN6855_HW21;
0809                 break;
0810             default:
0811                 goto unsupported_wcn6855_soc;
0812             }
0813             break;
0814         default:
0815 unsupported_wcn6855_soc:
0816             dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
0817                 soc_hw_version_major, soc_hw_version_minor);
0818             ret = -EOPNOTSUPP;
0819             goto err_pci_free_region;
0820         }
0821 
0822         pci_ops = &ath11k_pci_ops_qca6390;
0823         break;
0824     default:
0825         dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
0826             pci_dev->device);
0827         ret = -EOPNOTSUPP;
0828         goto err_pci_free_region;
0829     }
0830 
0831     ret = ath11k_pcic_register_pci_ops(ab, pci_ops);
0832     if (ret) {
0833         ath11k_err(ab, "failed to register PCI ops: %d\n", ret);
0834         goto err_pci_free_region;
0835     }
0836 
0837     ret = ath11k_pcic_init_msi_config(ab);
0838     if (ret) {
0839         ath11k_err(ab, "failed to init msi config: %d\n", ret);
0840         goto err_pci_free_region;
0841     }
0842 
0843     ret = ath11k_pci_alloc_msi(ab_pci);
0844     if (ret) {
0845         ath11k_err(ab, "failed to enable msi: %d\n", ret);
0846         goto err_pci_free_region;
0847     }
0848 
0849     ret = ath11k_core_pre_init(ab);
0850     if (ret)
0851         goto err_pci_disable_msi;
0852 
0853     ret = ath11k_mhi_register(ab_pci);
0854     if (ret) {
0855         ath11k_err(ab, "failed to register mhi: %d\n", ret);
0856         goto err_pci_disable_msi;
0857     }
0858 
0859     ret = ath11k_hal_srng_init(ab);
0860     if (ret)
0861         goto err_mhi_unregister;
0862 
0863     ret = ath11k_ce_alloc_pipes(ab);
0864     if (ret) {
0865         ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
0866         goto err_hal_srng_deinit;
0867     }
0868 
0869     ath11k_pci_init_qmi_ce_config(ab);
0870 
0871     ret = ath11k_pcic_config_irq(ab);
0872     if (ret) {
0873         ath11k_err(ab, "failed to config irq: %d\n", ret);
0874         goto err_ce_free;
0875     }
0876 
0877     ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0));
0878     if (ret) {
0879         ath11k_err(ab, "failed to set irq affinity %d\n", ret);
0880         goto err_free_irq;
0881     }
0882 
0883     /* kernel may allocate a dummy vector before request_irq and
0884      * then allocate a real vector when request_irq is called.
0885      * So get msi_data here again to avoid spurious interrupt
0886      * as msi_data will configured to srngs.
0887      */
0888     ret = ath11k_pci_config_msi_data(ab_pci);
0889     if (ret) {
0890         ath11k_err(ab, "failed to config msi_data: %d\n", ret);
0891         goto err_irq_affinity_cleanup;
0892     }
0893 
0894     ret = ath11k_core_init(ab);
0895     if (ret) {
0896         ath11k_err(ab, "failed to init core: %d\n", ret);
0897         goto err_irq_affinity_cleanup;
0898     }
0899     return 0;
0900 
0901 err_irq_affinity_cleanup:
0902     ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
0903 
0904 err_free_irq:
0905     ath11k_pcic_free_irq(ab);
0906 
0907 err_ce_free:
0908     ath11k_ce_free_pipes(ab);
0909 
0910 err_hal_srng_deinit:
0911     ath11k_hal_srng_deinit(ab);
0912 
0913 err_mhi_unregister:
0914     ath11k_mhi_unregister(ab_pci);
0915 
0916 err_pci_disable_msi:
0917     ath11k_pci_free_msi(ab_pci);
0918 
0919 err_pci_free_region:
0920     ath11k_pci_free_region(ab_pci);
0921 
0922 err_free_core:
0923     ath11k_core_free(ab);
0924 
0925     return ret;
0926 }
0927 
0928 static void ath11k_pci_remove(struct pci_dev *pdev)
0929 {
0930     struct ath11k_base *ab = pci_get_drvdata(pdev);
0931     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0932 
0933     ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
0934 
0935     if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
0936         ath11k_pci_power_down(ab);
0937         ath11k_debugfs_soc_destroy(ab);
0938         ath11k_qmi_deinit_service(ab);
0939         goto qmi_fail;
0940     }
0941 
0942     set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
0943 
0944     ath11k_core_deinit(ab);
0945 
0946 qmi_fail:
0947     ath11k_mhi_unregister(ab_pci);
0948 
0949     ath11k_pcic_free_irq(ab);
0950     ath11k_pci_free_msi(ab_pci);
0951     ath11k_pci_free_region(ab_pci);
0952 
0953     ath11k_hal_srng_deinit(ab);
0954     ath11k_ce_free_pipes(ab);
0955     ath11k_core_free(ab);
0956 }
0957 
0958 static void ath11k_pci_shutdown(struct pci_dev *pdev)
0959 {
0960     struct ath11k_base *ab = pci_get_drvdata(pdev);
0961     struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
0962 
0963     ath11k_pci_set_irq_affinity_hint(ab_pci, NULL);
0964     ath11k_pci_power_down(ab);
0965 }
0966 
0967 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
0968 {
0969     struct ath11k_base *ab = dev_get_drvdata(dev);
0970     int ret;
0971 
0972     if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
0973         ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n");
0974         return 0;
0975     }
0976 
0977     ret = ath11k_core_suspend(ab);
0978     if (ret)
0979         ath11k_warn(ab, "failed to suspend core: %d\n", ret);
0980 
0981     return ret;
0982 }
0983 
0984 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
0985 {
0986     struct ath11k_base *ab = dev_get_drvdata(dev);
0987     int ret;
0988 
0989     if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
0990         ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n");
0991         return 0;
0992     }
0993 
0994     ret = ath11k_core_resume(ab);
0995     if (ret)
0996         ath11k_warn(ab, "failed to resume core: %d\n", ret);
0997 
0998     return ret;
0999 }
1000 
1001 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops,
1002              ath11k_pci_pm_suspend,
1003              ath11k_pci_pm_resume);
1004 
1005 static struct pci_driver ath11k_pci_driver = {
1006     .name = "ath11k_pci",
1007     .id_table = ath11k_pci_id_table,
1008     .probe = ath11k_pci_probe,
1009     .remove = ath11k_pci_remove,
1010     .shutdown = ath11k_pci_shutdown,
1011 #ifdef CONFIG_PM
1012     .driver.pm = &ath11k_pci_pm_ops,
1013 #endif
1014 };
1015 
1016 static int ath11k_pci_init(void)
1017 {
1018     int ret;
1019 
1020     ret = pci_register_driver(&ath11k_pci_driver);
1021     if (ret)
1022         pr_err("failed to register ath11k pci driver: %d\n",
1023                ret);
1024 
1025     return ret;
1026 }
1027 module_init(ath11k_pci_init);
1028 
1029 static void ath11k_pci_exit(void)
1030 {
1031     pci_unregister_driver(&ath11k_pci_driver);
1032 }
1033 
1034 module_exit(ath11k_pci_exit);
1035 
1036 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices");
1037 MODULE_LICENSE("Dual BSD/GPL");
1038 
1039 /* QCA639x 2.0 firmware files */
1040 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE);
1041 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE);
1042 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE);
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