ath/ath11k/mhi.c

0001 // SPDX-License-Identifier: BSD-3-Clause-Clear
0002 /*
0003  * Copyright (c) 2020 The Linux Foundation. All rights reserved.
0004  * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
0005  */
0006
0007 #include <linux/msi.h>
0008 #include <linux/pci.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/ioport.h>
0012
0013 #include "core.h"
0014 #include "debug.h"
0015 #include "mhi.h"
0016 #include "pci.h"
0017 #include "pcic.h"
0018
0019 #define MHI_TIMEOUT_DEFAULT_MS  90000
0020 #define RDDM_DUMP_SIZE  0x420000
0021
0022 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
0023     {
0024         .num = 0,
0025         .name = "LOOPBACK",
0026         .num_elements = 32,
0027         .event_ring = 0,
0028         .dir = DMA_TO_DEVICE,
0029         .ee_mask = 0x4,
0030         .pollcfg = 0,
0031         .doorbell = MHI_DB_BRST_DISABLE,
0032         .lpm_notify = false,
0033         .offload_channel = false,
0034         .doorbell_mode_switch = false,
0035         .auto_queue = false,
0036     },
0037     {
0038         .num = 1,
0039         .name = "LOOPBACK",
0040         .num_elements = 32,
0041         .event_ring = 0,
0042         .dir = DMA_FROM_DEVICE,
0043         .ee_mask = 0x4,
0044         .pollcfg = 0,
0045         .doorbell = MHI_DB_BRST_DISABLE,
0046         .lpm_notify = false,
0047         .offload_channel = false,
0048         .doorbell_mode_switch = false,
0049         .auto_queue = false,
0050     },
0051     {
0052         .num = 20,
0053         .name = "IPCR",
0054         .num_elements = 64,
0055         .event_ring = 1,
0056         .dir = DMA_TO_DEVICE,
0057         .ee_mask = 0x4,
0058         .pollcfg = 0,
0059         .doorbell = MHI_DB_BRST_DISABLE,
0060         .lpm_notify = false,
0061         .offload_channel = false,
0062         .doorbell_mode_switch = false,
0063         .auto_queue = false,
0064     },
0065     {
0066         .num = 21,
0067         .name = "IPCR",
0068         .num_elements = 64,
0069         .event_ring = 1,
0070         .dir = DMA_FROM_DEVICE,
0071         .ee_mask = 0x4,
0072         .pollcfg = 0,
0073         .doorbell = MHI_DB_BRST_DISABLE,
0074         .lpm_notify = false,
0075         .offload_channel = false,
0076         .doorbell_mode_switch = false,
0077         .auto_queue = true,
0078     },
0079 };
0080
0081 static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
0082     {
0083         .num_elements = 32,
0084         .irq_moderation_ms = 0,
0085         .irq = 1,
0086         .mode = MHI_DB_BRST_DISABLE,
0087         .data_type = MHI_ER_CTRL,
0088         .hardware_event = false,
0089         .client_managed = false,
0090         .offload_channel = false,
0091     },
0092     {
0093         .num_elements = 256,
0094         .irq_moderation_ms = 1,
0095         .irq = 2,
0096         .mode = MHI_DB_BRST_DISABLE,
0097         .priority = 1,
0098         .hardware_event = false,
0099         .client_managed = false,
0100         .offload_channel = false,
0101     },
0102 };
0103
0104 static struct mhi_controller_config ath11k_mhi_config_qca6390 = {
0105     .max_channels = 128,
0106     .timeout_ms = 2000,
0107     .use_bounce_buf = false,
0108     .buf_len = 0,
0109     .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
0110     .ch_cfg = ath11k_mhi_channels_qca6390,
0111     .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
0112     .event_cfg = ath11k_mhi_events_qca6390,
0113 };
0114
0115 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
0116     {
0117         .num = 0,
0118         .name = "LOOPBACK",
0119         .num_elements = 32,
0120         .event_ring = 1,
0121         .dir = DMA_TO_DEVICE,
0122         .ee_mask = 0x14,
0123         .pollcfg = 0,
0124         .doorbell = MHI_DB_BRST_DISABLE,
0125         .lpm_notify = false,
0126         .offload_channel = false,
0127         .doorbell_mode_switch = false,
0128         .auto_queue = false,
0129     },
0130     {
0131         .num = 1,
0132         .name = "LOOPBACK",
0133         .num_elements = 32,
0134         .event_ring = 1,
0135         .dir = DMA_FROM_DEVICE,
0136         .ee_mask = 0x14,
0137         .pollcfg = 0,
0138         .doorbell = MHI_DB_BRST_DISABLE,
0139         .lpm_notify = false,
0140         .offload_channel = false,
0141         .doorbell_mode_switch = false,
0142         .auto_queue = false,
0143     },
0144     {
0145         .num = 20,
0146         .name = "IPCR",
0147         .num_elements = 32,
0148         .event_ring = 1,
0149         .dir = DMA_TO_DEVICE,
0150         .ee_mask = 0x14,
0151         .pollcfg = 0,
0152         .doorbell = MHI_DB_BRST_DISABLE,
0153         .lpm_notify = false,
0154         .offload_channel = false,
0155         .doorbell_mode_switch = false,
0156         .auto_queue = false,
0157     },
0158     {
0159         .num = 21,
0160         .name = "IPCR",
0161         .num_elements = 32,
0162         .event_ring = 1,
0163         .dir = DMA_FROM_DEVICE,
0164         .ee_mask = 0x14,
0165         .pollcfg = 0,
0166         .doorbell = MHI_DB_BRST_DISABLE,
0167         .lpm_notify = false,
0168         .offload_channel = false,
0169         .doorbell_mode_switch = false,
0170         .auto_queue = true,
0171     },
0172 };
0173
0174 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
0175     {
0176         .num_elements = 32,
0177         .irq_moderation_ms = 0,
0178         .irq = 1,
0179         .data_type = MHI_ER_CTRL,
0180         .mode = MHI_DB_BRST_DISABLE,
0181         .hardware_event = false,
0182         .client_managed = false,
0183         .offload_channel = false,
0184     },
0185     {
0186         .num_elements = 256,
0187         .irq_moderation_ms = 1,
0188         .irq = 2,
0189         .mode = MHI_DB_BRST_DISABLE,
0190         .priority = 1,
0191         .hardware_event = false,
0192         .client_managed = false,
0193         .offload_channel = false,
0194     },
0195 };
0196
0197 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
0198     .max_channels = 30,
0199     .timeout_ms = 10000,
0200     .use_bounce_buf = false,
0201     .buf_len = 0,
0202     .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
0203     .ch_cfg = ath11k_mhi_channels_qcn9074,
0204     .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
0205     .event_cfg = ath11k_mhi_events_qcn9074,
0206 };
0207
0208 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
0209 {
0210     u32 val;
0211
0212     val = ath11k_pcic_read32(ab, MHISTATUS);
0213
0214     ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val);
0215
0216     /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS
0217      * has SYSERR bit set and thus need to set MHICTRL_RESET
0218      * to clear SYSERR.
0219      */
0220     ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
0221
0222     mdelay(10);
0223 }
0224
0225 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab)
0226 {
0227     ath11k_pcic_write32(ab, PCIE_TXVECDB, 0);
0228 }
0229
0230 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab)
0231 {
0232     ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0);
0233 }
0234
0235 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab)
0236 {
0237     ath11k_pcic_write32(ab, PCIE_RXVECDB, 0);
0238 }
0239
0240 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab)
0241 {
0242     ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0);
0243 }
0244
0245 void ath11k_mhi_clear_vector(struct ath11k_base *ab)
0246 {
0247     ath11k_mhi_reset_txvecdb(ab);
0248     ath11k_mhi_reset_txvecstatus(ab);
0249     ath11k_mhi_reset_rxvecdb(ab);
0250     ath11k_mhi_reset_rxvecstatus(ab);
0251 }
0252
0253 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
0254 {
0255     struct ath11k_base *ab = ab_pci->ab;
0256     u32 user_base_data, base_vector;
0257     int ret, num_vectors, i;
0258     int *irq;
0259     unsigned int msi_data;
0260
0261     ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors,
0262                           &user_base_data, &base_vector);
0263     if (ret)
0264         return ret;
0265
0266     ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n",
0267            num_vectors, base_vector);
0268
0269     irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL);
0270     if (!irq)
0271         return -ENOMEM;
0272
0273     for (i = 0; i < num_vectors; i++) {
0274         msi_data = base_vector;
0275
0276         if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
0277             msi_data += i;
0278
0279         irq[i] = ath11k_pci_get_msi_irq(ab, msi_data);
0280     }
0281
0282     ab_pci->mhi_ctrl->irq = irq;
0283     ab_pci->mhi_ctrl->nr_irqs = num_vectors;
0284
0285     return 0;
0286 }
0287
0288 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
0289 {
0290     return 0;
0291 }
0292
0293 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
0294 {
0295 }
0296
0297 static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason)
0298 {
0299     switch (reason) {
0300     case MHI_CB_IDLE:
0301         return "MHI_CB_IDLE";
0302     case MHI_CB_PENDING_DATA:
0303         return "MHI_CB_PENDING_DATA";
0304     case MHI_CB_LPM_ENTER:
0305         return "MHI_CB_LPM_ENTER";
0306     case MHI_CB_LPM_EXIT:
0307         return "MHI_CB_LPM_EXIT";
0308     case MHI_CB_EE_RDDM:
0309         return "MHI_CB_EE_RDDM";
0310     case MHI_CB_EE_MISSION_MODE:
0311         return "MHI_CB_EE_MISSION_MODE";
0312     case MHI_CB_SYS_ERROR:
0313         return "MHI_CB_SYS_ERROR";
0314     case MHI_CB_FATAL_ERROR:
0315         return "MHI_CB_FATAL_ERROR";
0316     case MHI_CB_BW_REQ:
0317         return "MHI_CB_BW_REQ";
0318     default:
0319         return "UNKNOWN";
0320     }
0321 };
0322
0323 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
0324                     enum mhi_callback cb)
0325 {
0326     struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
0327
0328     ath11k_dbg(ab, ATH11K_DBG_BOOT, "mhi notify status reason %s\n",
0329            ath11k_mhi_op_callback_to_str(cb));
0330
0331     switch (cb) {
0332     case MHI_CB_SYS_ERROR:
0333         ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
0334         break;
0335     case MHI_CB_EE_RDDM:
0336         if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags)))
0337             queue_work(ab->workqueue_aux, &ab->reset_work);
0338         break;
0339     default:
0340         break;
0341     }
0342 }
0343
0344 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
0345                   void __iomem *addr,
0346                   u32 *out)
0347 {
0348     *out = readl(addr);
0349
0350     return 0;
0351 }
0352
0353 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
0354                     void __iomem *addr,
0355                     u32 val)
0356 {
0357     writel(val, addr);
0358 }
0359
0360 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
0361 {
0362     struct device_node *np;
0363     struct resource res;
0364     int ret;
0365
0366     np = of_find_node_by_type(NULL, "memory");
0367     if (!np)
0368         return -ENOENT;
0369
0370     ret = of_address_to_resource(np, 0, &res);
0371     of_node_put(np);
0372     if (ret)
0373         return ret;
0374
0375     mhi_ctrl->iova_start = res.start + 0x1000000;
0376     mhi_ctrl->iova_stop = res.end;
0377
0378     return 0;
0379 }
0380
0381 int ath11k_mhi_register(struct ath11k_pci *ab_pci)
0382 {
0383     struct ath11k_base *ab = ab_pci->ab;
0384     struct mhi_controller *mhi_ctrl;
0385     struct mhi_controller_config *ath11k_mhi_config;
0386     int ret;
0387
0388     mhi_ctrl = mhi_alloc_controller();
0389     if (!mhi_ctrl)
0390         return -ENOMEM;
0391
0392     ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE,
0393                      ab_pci->amss_path,
0394                      sizeof(ab_pci->amss_path));
0395
0396     ab_pci->mhi_ctrl = mhi_ctrl;
0397     mhi_ctrl->cntrl_dev = ab->dev;
0398     mhi_ctrl->fw_image = ab_pci->amss_path;
0399     mhi_ctrl->regs = ab->mem;
0400     mhi_ctrl->reg_len = ab->mem_len;
0401
0402     ret = ath11k_mhi_get_msi(ab_pci);
0403     if (ret) {
0404         ath11k_err(ab, "failed to get msi for mhi\n");
0405         mhi_free_controller(mhi_ctrl);
0406         return ret;
0407     }
0408
0409     if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
0410         mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
0411
0412     if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) {
0413         ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl);
0414         if (ret < 0)
0415             return ret;
0416     } else {
0417         mhi_ctrl->iova_start = 0;
0418         mhi_ctrl->iova_stop = 0xFFFFFFFF;
0419     }
0420
0421     mhi_ctrl->rddm_size = RDDM_DUMP_SIZE;
0422     mhi_ctrl->sbl_size = SZ_512K;
0423     mhi_ctrl->seg_len = SZ_512K;
0424     mhi_ctrl->fbc_download = true;
0425     mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get;
0426     mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put;
0427     mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
0428     mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
0429     mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
0430
0431     switch (ab->hw_rev) {
0432     case ATH11K_HW_QCN9074_HW10:
0433         ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
0434         break;
0435     case ATH11K_HW_QCA6390_HW20:
0436     case ATH11K_HW_WCN6855_HW20:
0437     case ATH11K_HW_WCN6855_HW21:
0438         ath11k_mhi_config = &ath11k_mhi_config_qca6390;
0439         break;
0440     default:
0441         ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n",
0442                ab->hw_rev);
0443         mhi_free_controller(mhi_ctrl);
0444         return -EINVAL;
0445     }
0446
0447     ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
0448     if (ret) {
0449         ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
0450         mhi_free_controller(mhi_ctrl);
0451         return ret;
0452     }
0453
0454     return 0;
0455 }
0456
0457 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci)
0458 {
0459     struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
0460
0461     mhi_unregister_controller(mhi_ctrl);
0462     kfree(mhi_ctrl->irq);
0463     mhi_free_controller(mhi_ctrl);
0464 }
0465
0466 int ath11k_mhi_start(struct ath11k_pci *ab_pci)
0467 {
0468     struct ath11k_base *ab = ab_pci->ab;
0469     int ret;
0470
0471     ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
0472
0473     ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
0474     if (ret) {
0475         ath11k_warn(ab, "failed to prepare mhi: %d", ret);
0476         return ret;
0477     }
0478
0479     ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
0480     if (ret) {
0481         ath11k_warn(ab, "failed to power up mhi: %d", ret);
0482         return ret;
0483     }
0484
0485     return 0;
0486 }
0487
0488 void ath11k_mhi_stop(struct ath11k_pci *ab_pci)
0489 {
0490     mhi_power_down(ab_pci->mhi_ctrl, true);
0491     mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
0492 }
0493
0494 int ath11k_mhi_suspend(struct ath11k_pci *ab_pci)
0495 {
0496     struct ath11k_base *ab = ab_pci->ab;
0497     int ret;
0498
0499     ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
0500     if (ret) {
0501         ath11k_warn(ab, "failed to suspend mhi: %d", ret);
0502         return ret;
0503     }
0504
0505     return 0;
0506 }
0507
0508 int ath11k_mhi_resume(struct ath11k_pci *ab_pci)
0509 {
0510     struct ath11k_base *ab = ab_pci->ab;
0511     int ret;
0512
0513     /* Do force MHI resume as some devices like QCA6390, WCN6855
0514      * are not in M3 state but they are functional. So just ignore
0515      * the MHI state while resuming.
0516      */
0517     ret = mhi_pm_resume_force(ab_pci->mhi_ctrl);
0518     if (ret) {
0519         ath11k_warn(ab, "failed to resume mhi: %d", ret);
0520         return ret;
0521     }
0522
0523     return 0;
0524 }