ath/ath11k/mac.h

0001 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
0002 /*
0003  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef ATH11K_MAC_H
0007 #define ATH11K_MAC_H
0008
0009 #include <net/mac80211.h>
0010 #include <net/cfg80211.h>
0011 #include "wmi.h"
0012
0013 struct ath11k;
0014 struct ath11k_base;
0015
0016 struct ath11k_generic_iter {
0017     struct ath11k *ar;
0018     int ret;
0019 };
0020
0021 /* number of failed packets (20 packets with 16 sw reties each) */
0022 #define ATH11K_KICKOUT_THRESHOLD        (20 * 16)
0023
0024 /* Use insanely high numbers to make sure that the firmware implementation
0025  * won't start, we have the same functionality already in hostapd. Unit
0026  * is seconds.
0027  */
0028 #define ATH11K_KEEPALIVE_MIN_IDLE       3747
0029 #define ATH11K_KEEPALIVE_MAX_IDLE       3895
0030 #define ATH11K_KEEPALIVE_MAX_UNRESPONSIVE   3900
0031
0032 #define WMI_HOST_RC_DS_FLAG         0x01
0033 #define WMI_HOST_RC_CW40_FLAG           0x02
0034 #define WMI_HOST_RC_SGI_FLAG            0x04
0035 #define WMI_HOST_RC_HT_FLAG         0x08
0036 #define WMI_HOST_RC_RTSCTS_FLAG         0x10
0037 #define WMI_HOST_RC_TX_STBC_FLAG        0x20
0038 #define WMI_HOST_RC_RX_STBC_FLAG        0xC0
0039 #define WMI_HOST_RC_RX_STBC_FLAG_S      6
0040 #define WMI_HOST_RC_WEP_TKIP_FLAG       0x100
0041 #define WMI_HOST_RC_TS_FLAG         0x200
0042 #define WMI_HOST_RC_UAPSD_FLAG          0x400
0043
0044 #define WMI_HT_CAP_ENABLED          0x0001
0045 #define WMI_HT_CAP_HT20_SGI         0x0002
0046 #define WMI_HT_CAP_DYNAMIC_SMPS         0x0004
0047 #define WMI_HT_CAP_TX_STBC          0x0008
0048 #define WMI_HT_CAP_TX_STBC_MASK_SHIFT       3
0049 #define WMI_HT_CAP_RX_STBC          0x0030
0050 #define WMI_HT_CAP_RX_STBC_MASK_SHIFT       4
0051 #define WMI_HT_CAP_LDPC             0x0040
0052 #define WMI_HT_CAP_L_SIG_TXOP_PROT      0x0080
0053 #define WMI_HT_CAP_MPDU_DENSITY         0x0700
0054 #define WMI_HT_CAP_MPDU_DENSITY_MASK_SHIFT  8
0055 #define WMI_HT_CAP_HT40_SGI         0x0800
0056 #define WMI_HT_CAP_RX_LDPC          0x1000
0057 #define WMI_HT_CAP_TX_LDPC          0x2000
0058 #define WMI_HT_CAP_IBF_BFER         0x4000
0059
0060 /* These macros should be used when we wish to advertise STBC support for
0061  * only 1SS or 2SS or 3SS.
0062  */
0063 #define WMI_HT_CAP_RX_STBC_1SS          0x0010
0064 #define WMI_HT_CAP_RX_STBC_2SS          0x0020
0065 #define WMI_HT_CAP_RX_STBC_3SS          0x0030
0066
0067 #define WMI_HT_CAP_DEFAULT_ALL (WMI_HT_CAP_ENABLED    | \
0068                 WMI_HT_CAP_HT20_SGI   | \
0069                 WMI_HT_CAP_HT40_SGI   | \
0070                 WMI_HT_CAP_TX_STBC    | \
0071                 WMI_HT_CAP_RX_STBC    | \
0072                 WMI_HT_CAP_LDPC)
0073
0074 #define WMI_VHT_CAP_MAX_MPDU_LEN_MASK       0x00000003
0075 #define WMI_VHT_CAP_RX_LDPC         0x00000010
0076 #define WMI_VHT_CAP_SGI_80MHZ           0x00000020
0077 #define WMI_VHT_CAP_SGI_160MHZ          0x00000040
0078 #define WMI_VHT_CAP_TX_STBC         0x00000080
0079 #define WMI_VHT_CAP_RX_STBC_MASK        0x00000300
0080 #define WMI_VHT_CAP_RX_STBC_MASK_SHIFT      8
0081 #define WMI_VHT_CAP_SU_BFER         0x00000800
0082 #define WMI_VHT_CAP_SU_BFEE         0x00001000
0083 #define WMI_VHT_CAP_MAX_CS_ANT_MASK     0x0000E000
0084 #define WMI_VHT_CAP_MAX_CS_ANT_MASK_SHIFT   13
0085 #define WMI_VHT_CAP_MAX_SND_DIM_MASK        0x00070000
0086 #define WMI_VHT_CAP_MAX_SND_DIM_MASK_SHIFT  16
0087 #define WMI_VHT_CAP_MU_BFER         0x00080000
0088 #define WMI_VHT_CAP_MU_BFEE         0x00100000
0089 #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP       0x03800000
0090 #define WMI_VHT_CAP_MAX_AMPDU_LEN_EXP_SHIT  23
0091 #define WMI_VHT_CAP_RX_FIXED_ANT        0x10000000
0092 #define WMI_VHT_CAP_TX_FIXED_ANT        0x20000000
0093
0094 #define WMI_VHT_CAP_MAX_MPDU_LEN_11454      0x00000002
0095
0096 /* These macros should be used when we wish to advertise STBC support for
0097  * only 1SS or 2SS or 3SS.
0098  */
0099 #define WMI_VHT_CAP_RX_STBC_1SS         0x00000100
0100 #define WMI_VHT_CAP_RX_STBC_2SS         0x00000200
0101 #define WMI_VHT_CAP_RX_STBC_3SS         0x00000300
0102
0103 #define WMI_VHT_CAP_DEFAULT_ALL (WMI_VHT_CAP_MAX_MPDU_LEN_11454  | \
0104                  WMI_VHT_CAP_SGI_80MHZ      |       \
0105                  WMI_VHT_CAP_TX_STBC        |       \
0106                  WMI_VHT_CAP_RX_STBC_MASK   |       \
0107                  WMI_VHT_CAP_RX_LDPC        |       \
0108                  WMI_VHT_CAP_MAX_AMPDU_LEN_EXP   |  \
0109                  WMI_VHT_CAP_RX_FIXED_ANT   |       \
0110                  WMI_VHT_CAP_TX_FIXED_ANT)
0111
0112 /* FIXME: should these be in ieee80211.h? */
0113 #define IEEE80211_VHT_MCS_SUPPORT_0_11_MASK GENMASK(23, 16)
0114 #define IEEE80211_DISABLE_VHT_MCS_SUPPORT_0_11  BIT(24)
0115
0116 #define WMI_MAX_SPATIAL_STREAM          3
0117
0118 #define ATH11K_CHAN_WIDTH_NUM           8
0119 #define ATH11K_BW_NSS_MAP_ENABLE        BIT(31)
0120 #define ATH11K_PEER_RX_NSS_160MHZ       GENMASK(2, 0)
0121 #define ATH11K_PEER_RX_NSS_80_80MHZ     GENMASK(5, 3)
0122
0123 #define ATH11K_OBSS_PD_MAX_THRESHOLD            -82
0124 #define ATH11K_OBSS_PD_NON_SRG_MAX_THRESHOLD        -62
0125 #define ATH11K_OBSS_PD_THRESHOLD_IN_DBM         BIT(29)
0126 #define ATH11K_OBSS_PD_SRG_EN               BIT(30)
0127 #define ATH11K_OBSS_PD_NON_SRG_EN           BIT(31)
0128
0129 extern const struct htt_rx_ring_tlv_filter ath11k_mac_mon_status_filter_default;
0130
0131 #define ATH11K_SCAN_11D_INTERVAL        600000
0132 #define ATH11K_11D_INVALID_VDEV_ID      0xFFFF
0133
0134 void ath11k_mac_11d_scan_start(struct ath11k *ar, u32 vdev_id);
0135 void ath11k_mac_11d_scan_stop(struct ath11k *ar);
0136 void ath11k_mac_11d_scan_stop_all(struct ath11k_base *ab);
0137
0138 void ath11k_mac_destroy(struct ath11k_base *ab);
0139 void ath11k_mac_unregister(struct ath11k_base *ab);
0140 int ath11k_mac_register(struct ath11k_base *ab);
0141 int ath11k_mac_allocate(struct ath11k_base *ab);
0142 int ath11k_mac_hw_ratecode_to_legacy_rate(u8 hw_rc, u8 preamble, u8 *rateidx,
0143                       u16 *rate);
0144 u8 ath11k_mac_bitrate_to_idx(const struct ieee80211_supported_band *sband,
0145                  u32 bitrate);
0146 u8 ath11k_mac_hw_rate_to_idx(const struct ieee80211_supported_band *sband,
0147                  u8 hw_rate, bool cck);
0148
0149 void __ath11k_mac_scan_finish(struct ath11k *ar);
0150 void ath11k_mac_scan_finish(struct ath11k *ar);
0151
0152 struct ath11k_vif *ath11k_mac_get_arvif(struct ath11k *ar, u32 vdev_id);
0153 struct ath11k_vif *ath11k_mac_get_arvif_by_vdev_id(struct ath11k_base *ab,
0154                            u32 vdev_id);
0155 u8 ath11k_mac_get_target_pdev_id(struct ath11k *ar);
0156 u8 ath11k_mac_get_target_pdev_id_from_vif(struct ath11k_vif *arvif);
0157 struct ath11k_vif *ath11k_mac_get_vif_up(struct ath11k_base *ab);
0158
0159 struct ath11k *ath11k_mac_get_ar_by_vdev_id(struct ath11k_base *ab, u32 vdev_id);
0160 struct ath11k *ath11k_mac_get_ar_by_pdev_id(struct ath11k_base *ab, u32 pdev_id);
0161
0162 void ath11k_mac_drain_tx(struct ath11k *ar);
0163 void ath11k_mac_peer_cleanup_all(struct ath11k *ar);
0164 int ath11k_mac_tx_mgmt_pending_free(int buf_id, void *skb, void *ctx);
0165 u8 ath11k_mac_bw_to_mac80211_bw(u8 bw);
0166 u32 ath11k_mac_he_gi_to_nl80211_he_gi(u8 sgi);
0167 enum nl80211_he_ru_alloc ath11k_mac_phy_he_ru_to_nl80211_he_ru_alloc(u16 ru_phy);
0168 enum nl80211_he_ru_alloc ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones);
0169 enum ath11k_supported_bw ath11k_mac_mac80211_bw_to_ath11k_bw(enum rate_info_bw bw);
0170 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher);
0171 void ath11k_mac_handle_beacon(struct ath11k *ar, struct sk_buff *skb);
0172 void ath11k_mac_handle_beacon_miss(struct ath11k *ar, u32 vdev_id);
0173 void ath11k_mac_bcn_tx_event(struct ath11k_vif *arvif);
0174 int ath11k_mac_wait_tx_complete(struct ath11k *ar);
0175 int ath11k_mac_vif_set_keepalive(struct ath11k_vif *arvif,
0176                  enum wmi_sta_keepalive_method method,
0177                  u32 interval);
0178 #endif