ath/ath11k/hw.h

0001 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
0002 /*
0003  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
0004  * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
0005  */
0006
0007 #ifndef ATH11K_HW_H
0008 #define ATH11K_HW_H
0009
0010 #include "hal.h"
0011 #include "wmi.h"
0012
0013 /* Target configuration defines */
0014
0015 /* Num VDEVS per radio */
0016 #define TARGET_NUM_VDEVS(ab)    (ab->hw_params.num_vdevs)
0017
0018 #define TARGET_NUM_PEERS_PDEV(ab) (ab->hw_params.num_peers + TARGET_NUM_VDEVS(ab))
0019
0020 /* Num of peers for Single Radio mode */
0021 #define TARGET_NUM_PEERS_SINGLE(ab) (TARGET_NUM_PEERS_PDEV(ab))
0022
0023 /* Num of peers for DBS */
0024 #define TARGET_NUM_PEERS_DBS(ab) (2 * TARGET_NUM_PEERS_PDEV(ab))
0025
0026 /* Num of peers for DBS_SBS */
0027 #define TARGET_NUM_PEERS_DBS_SBS(ab)    (3 * TARGET_NUM_PEERS_PDEV(ab))
0028
0029 /* Max num of stations (per radio) */
0030 #define TARGET_NUM_STATIONS(ab) (ab->hw_params.num_peers)
0031
0032 #define TARGET_NUM_PEERS(ab, x) TARGET_NUM_PEERS_##x(ab)
0033 #define TARGET_NUM_PEER_KEYS    2
0034 #define TARGET_NUM_TIDS(ab, x)  (2 * TARGET_NUM_PEERS(ab, x) +  \
0035                  4 * TARGET_NUM_VDEVS(ab) + 8)
0036
0037 #define TARGET_AST_SKID_LIMIT   16
0038 #define TARGET_NUM_OFFLD_PEERS  4
0039 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
0040
0041 #define TARGET_TX_CHAIN_MASK    (BIT(0) | BIT(1) | BIT(2) | BIT(4))
0042 #define TARGET_RX_CHAIN_MASK    (BIT(0) | BIT(1) | BIT(2) | BIT(4))
0043 #define TARGET_RX_TIMEOUT_LO_PRI    100
0044 #define TARGET_RX_TIMEOUT_HI_PRI    40
0045
0046 #define TARGET_DECAP_MODE_RAW       0
0047 #define TARGET_DECAP_MODE_NATIVE_WIFI   1
0048 #define TARGET_DECAP_MODE_ETH       2
0049
0050 #define TARGET_SCAN_MAX_PENDING_REQS    4
0051 #define TARGET_BMISS_OFFLOAD_MAX_VDEV   3
0052 #define TARGET_ROAM_OFFLOAD_MAX_VDEV    3
0053 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
0054 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
0055 #define TARGET_NUM_MCAST_GROUPS     12
0056 #define TARGET_NUM_MCAST_TABLE_ELEMS    64
0057 #define TARGET_MCAST2UCAST_MODE     2
0058 #define TARGET_TX_DBG_LOG_SIZE      1024
0059 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
0060 #define TARGET_VOW_CONFIG       0
0061 #define TARGET_NUM_MSDU_DESC        (2500)
0062 #define TARGET_MAX_FRAG_ENTRIES     6
0063 #define TARGET_MAX_BCN_OFFLD        16
0064 #define TARGET_NUM_WDS_ENTRIES      32
0065 #define TARGET_DMA_BURST_SIZE       1
0066 #define TARGET_RX_BATCHMODE     1
0067
0068 #define ATH11K_HW_MAX_QUEUES        4
0069 #define ATH11K_QUEUE_LEN        4096
0070
0071 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK  0x4
0072
0073 #define ATH11K_FW_DIR           "ath11k"
0074
0075 #define ATH11K_BOARD_MAGIC      "QCA-ATH11K-BOARD"
0076 #define ATH11K_BOARD_API2_FILE      "board-2.bin"
0077 #define ATH11K_DEFAULT_BOARD_FILE   "board.bin"
0078 #define ATH11K_DEFAULT_CAL_FILE     "caldata.bin"
0079 #define ATH11K_AMSS_FILE        "amss.bin"
0080 #define ATH11K_M3_FILE          "m3.bin"
0081 #define ATH11K_REGDB_FILE_NAME      "regdb.bin"
0082
0083 enum ath11k_hw_rate_cck {
0084     ATH11K_HW_RATE_CCK_LP_11M = 0,
0085     ATH11K_HW_RATE_CCK_LP_5_5M,
0086     ATH11K_HW_RATE_CCK_LP_2M,
0087     ATH11K_HW_RATE_CCK_LP_1M,
0088     ATH11K_HW_RATE_CCK_SP_11M,
0089     ATH11K_HW_RATE_CCK_SP_5_5M,
0090     ATH11K_HW_RATE_CCK_SP_2M,
0091 };
0092
0093 enum ath11k_hw_rate_ofdm {
0094     ATH11K_HW_RATE_OFDM_48M = 0,
0095     ATH11K_HW_RATE_OFDM_24M,
0096     ATH11K_HW_RATE_OFDM_12M,
0097     ATH11K_HW_RATE_OFDM_6M,
0098     ATH11K_HW_RATE_OFDM_54M,
0099     ATH11K_HW_RATE_OFDM_36M,
0100     ATH11K_HW_RATE_OFDM_18M,
0101     ATH11K_HW_RATE_OFDM_9M,
0102 };
0103
0104 enum ath11k_bus {
0105     ATH11K_BUS_AHB,
0106     ATH11K_BUS_PCI,
0107 };
0108
0109 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
0110
0111 struct hal_rx_desc;
0112 struct hal_tcl_data_cmd;
0113
0114 struct ath11k_hw_ring_mask {
0115     u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0116     u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0117     u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0118     u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0119     u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0120     u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0121     u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0122     u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];
0123 };
0124
0125 struct ath11k_hw_hal_params {
0126     enum hal_rx_buf_return_buf_manager rx_buf_rbm;
0127 };
0128
0129 struct ath11k_hw_params {
0130     const char *name;
0131     u16 hw_rev;
0132     u8 max_radios;
0133     u32 bdf_addr;
0134
0135     struct {
0136         const char *dir;
0137         size_t board_size;
0138         size_t cal_offset;
0139     } fw;
0140
0141     const struct ath11k_hw_ops *hw_ops;
0142     const struct ath11k_hw_ring_mask *ring_mask;
0143
0144     bool internal_sleep_clock;
0145
0146     const struct ath11k_hw_regs *regs;
0147     u32 qmi_service_ins_id;
0148     const struct ce_attr *host_ce_config;
0149     u32 ce_count;
0150     const struct ce_pipe_config *target_ce_config;
0151     u32 target_ce_count;
0152     const struct service_to_pipe *svc_to_ce_map;
0153     u32 svc_to_ce_map_len;
0154
0155     bool single_pdev_only;
0156
0157     bool rxdma1_enable;
0158     int num_rxmda_per_pdev;
0159     bool rx_mac_buf_ring;
0160     bool vdev_start_delay;
0161     bool htt_peer_map_v2;
0162
0163     struct {
0164         u8 fft_sz;
0165         u8 fft_pad_sz;
0166         u8 summary_pad_sz;
0167         u8 fft_hdr_len;
0168         u16 max_fft_bins;
0169     } spectral;
0170
0171     u16 interface_modes;
0172     bool supports_monitor;
0173     bool full_monitor_mode;
0174     bool supports_shadow_regs;
0175     bool idle_ps;
0176     bool supports_sta_ps;
0177     bool cold_boot_calib;
0178     int fw_mem_mode;
0179     u32 num_vdevs;
0180     u32 num_peers;
0181     bool supports_suspend;
0182     u32 hal_desc_sz;
0183     bool supports_regdb;
0184     bool fix_l1ss;
0185     bool credit_flow;
0186     u8 max_tx_ring;
0187     const struct ath11k_hw_hal_params *hal_params;
0188     bool supports_dynamic_smps_6ghz;
0189     bool alloc_cacheable_memory;
0190     bool supports_rssi_stats;
0191     bool fw_wmi_diag_event;
0192     bool current_cc_support;
0193     bool dbr_debug_support;
0194     bool global_reset;
0195     const struct cfg80211_sar_capa *bios_sar_capa;
0196     bool m3_fw_support;
0197     bool fixed_bdf_addr;
0198     bool fixed_mem_region;
0199     bool static_window_map;
0200     bool hybrid_bus_type;
0201     bool fixed_fw_mem;
0202     bool support_off_channel_tx;
0203 };
0204
0205 struct ath11k_hw_ops {
0206     u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
0207     void (*wmi_init_config)(struct ath11k_base *ab,
0208                 struct target_resource_config *config);
0209     int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);
0210     int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
0211     void (*tx_mesh_enable)(struct ath11k_base *ab,
0212                    struct hal_tcl_data_cmd *tcl_cmd);
0213     bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
0214     bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
0215     u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
0216     u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
0217     bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
0218     u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
0219     u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
0220     u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
0221     bool (*rx_desc_get_ldpc_support)(struct hal_rx_desc *desc);
0222     bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
0223     bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
0224     u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
0225     u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
0226     u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
0227     u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
0228     u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
0229     u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
0230     u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
0231     u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
0232     u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
0233     u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
0234     void (*rx_desc_copy_attn_end_tlv)(struct hal_rx_desc *fdesc,
0235                       struct hal_rx_desc *ldesc);
0236     u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
0237     u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
0238     void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
0239     struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
0240     u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
0241     void (*reo_setup)(struct ath11k_base *ab);
0242     u16 (*mpdu_info_get_peerid)(u8 *tlv_data);
0243     bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
0244     u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
0245 };
0246
0247 extern const struct ath11k_hw_ops ipq8074_ops;
0248 extern const struct ath11k_hw_ops ipq6018_ops;
0249 extern const struct ath11k_hw_ops qca6390_ops;
0250 extern const struct ath11k_hw_ops qcn9074_ops;
0251 extern const struct ath11k_hw_ops wcn6855_ops;
0252 extern const struct ath11k_hw_ops wcn6750_ops;
0253
0254 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
0255 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
0256 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074;
0257
0258 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074;
0259 extern const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390;
0260
0261 static inline
0262 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
0263                    int pdev_idx)
0264 {
0265     if (hw->hw_ops->get_hw_mac_from_pdev_id)
0266         return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
0267
0268     return 0;
0269 }
0270
0271 static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw,
0272                           int mac_id)
0273 {
0274     if (hw->hw_ops->mac_id_to_pdev_id)
0275         return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
0276
0277     return 0;
0278 }
0279
0280 static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw,
0281                           int mac_id)
0282 {
0283     if (hw->hw_ops->mac_id_to_srng_id)
0284         return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
0285
0286     return 0;
0287 }
0288
0289 struct ath11k_fw_ie {
0290     __le32 id;
0291     __le32 len;
0292     u8 data[];
0293 };
0294
0295 enum ath11k_bd_ie_board_type {
0296     ATH11K_BD_IE_BOARD_NAME = 0,
0297     ATH11K_BD_IE_BOARD_DATA = 1,
0298 };
0299
0300 enum ath11k_bd_ie_regdb_type {
0301     ATH11K_BD_IE_REGDB_NAME = 0,
0302     ATH11K_BD_IE_REGDB_DATA = 1,
0303 };
0304
0305 enum ath11k_bd_ie_type {
0306     /* contains sub IEs of enum ath11k_bd_ie_board_type */
0307     ATH11K_BD_IE_BOARD = 0,
0308     /* contains sub IEs of enum ath11k_bd_ie_regdb_type */
0309     ATH11K_BD_IE_REGDB = 1,
0310 };
0311
0312 struct ath11k_hw_regs {
0313     u32 hal_tcl1_ring_base_lsb;
0314     u32 hal_tcl1_ring_base_msb;
0315     u32 hal_tcl1_ring_id;
0316     u32 hal_tcl1_ring_misc;
0317     u32 hal_tcl1_ring_tp_addr_lsb;
0318     u32 hal_tcl1_ring_tp_addr_msb;
0319     u32 hal_tcl1_ring_consumer_int_setup_ix0;
0320     u32 hal_tcl1_ring_consumer_int_setup_ix1;
0321     u32 hal_tcl1_ring_msi1_base_lsb;
0322     u32 hal_tcl1_ring_msi1_base_msb;
0323     u32 hal_tcl1_ring_msi1_data;
0324     u32 hal_tcl2_ring_base_lsb;
0325     u32 hal_tcl_ring_base_lsb;
0326
0327     u32 hal_tcl_status_ring_base_lsb;
0328
0329     u32 hal_reo1_ring_base_lsb;
0330     u32 hal_reo1_ring_base_msb;
0331     u32 hal_reo1_ring_id;
0332     u32 hal_reo1_ring_misc;
0333     u32 hal_reo1_ring_hp_addr_lsb;
0334     u32 hal_reo1_ring_hp_addr_msb;
0335     u32 hal_reo1_ring_producer_int_setup;
0336     u32 hal_reo1_ring_msi1_base_lsb;
0337     u32 hal_reo1_ring_msi1_base_msb;
0338     u32 hal_reo1_ring_msi1_data;
0339     u32 hal_reo2_ring_base_lsb;
0340     u32 hal_reo1_aging_thresh_ix_0;
0341     u32 hal_reo1_aging_thresh_ix_1;
0342     u32 hal_reo1_aging_thresh_ix_2;
0343     u32 hal_reo1_aging_thresh_ix_3;
0344
0345     u32 hal_reo1_ring_hp;
0346     u32 hal_reo1_ring_tp;
0347     u32 hal_reo2_ring_hp;
0348
0349     u32 hal_reo_tcl_ring_base_lsb;
0350     u32 hal_reo_tcl_ring_hp;
0351
0352     u32 hal_reo_status_ring_base_lsb;
0353     u32 hal_reo_status_hp;
0354
0355     u32 hal_reo_cmd_ring_base_lsb;
0356     u32 hal_reo_cmd_ring_hp;
0357
0358     u32 hal_sw2reo_ring_base_lsb;
0359     u32 hal_sw2reo_ring_hp;
0360
0361     u32 hal_seq_wcss_umac_ce0_src_reg;
0362     u32 hal_seq_wcss_umac_ce0_dst_reg;
0363     u32 hal_seq_wcss_umac_ce1_src_reg;
0364     u32 hal_seq_wcss_umac_ce1_dst_reg;
0365
0366     u32 hal_wbm_idle_link_ring_base_lsb;
0367     u32 hal_wbm_idle_link_ring_misc;
0368
0369     u32 hal_wbm_release_ring_base_lsb;
0370
0371     u32 hal_wbm0_release_ring_base_lsb;
0372     u32 hal_wbm1_release_ring_base_lsb;
0373
0374     u32 pcie_qserdes_sysclk_en_sel;
0375     u32 pcie_pcs_osc_dtct_config_base;
0376
0377     u32 hal_shadow_base_addr;
0378     u32 hal_reo1_misc_ctl;
0379 };
0380
0381 extern const struct ath11k_hw_regs ipq8074_regs;
0382 extern const struct ath11k_hw_regs qca6390_regs;
0383 extern const struct ath11k_hw_regs qcn9074_regs;
0384 extern const struct ath11k_hw_regs wcn6855_regs;
0385 extern const struct ath11k_hw_regs wcn6750_regs;
0386
0387 static inline const char *ath11k_bd_ie_type_str(enum ath11k_bd_ie_type type)
0388 {
0389     switch (type) {
0390     case ATH11K_BD_IE_BOARD:
0391         return "board data";
0392     case ATH11K_BD_IE_REGDB:
0393         return "regdb data";
0394     }
0395
0396     return "unknown";
0397 }
0398
0399 extern const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855;
0400 #endif