ath/ath11k/hal_tx.c

0001 // SPDX-License-Identifier: BSD-3-Clause-Clear
0002 /*
0003  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
0004  */
0005
0006 #include "hal_desc.h"
0007 #include "hal.h"
0008 #include "hal_tx.h"
0009 #include "hif.h"
0010
0011 #define DSCP_TID_MAP_TBL_ENTRY_SIZE 64
0012
0013 /* dscp_tid_map - Default DSCP-TID mapping
0014  *
0015  * DSCP        TID
0016  * 000000      0
0017  * 001000      1
0018  * 010000      2
0019  * 011000      3
0020  * 100000      4
0021  * 101000      5
0022  * 110000      6
0023  * 111000      7
0024  */
0025 static const u8 dscp_tid_map[DSCP_TID_MAP_TBL_ENTRY_SIZE] = {
0026     0, 0, 0, 0, 0, 0, 0, 0,
0027     1, 1, 1, 1, 1, 1, 1, 1,
0028     2, 2, 2, 2, 2, 2, 2, 2,
0029     3, 3, 3, 3, 3, 3, 3, 3,
0030     4, 4, 4, 4, 4, 4, 4, 4,
0031     5, 5, 5, 5, 5, 5, 5, 5,
0032     6, 6, 6, 6, 6, 6, 6, 6,
0033     7, 7, 7, 7, 7, 7, 7, 7,
0034 };
0035
0036 void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd,
0037                   struct hal_tx_info *ti)
0038 {
0039     struct hal_tcl_data_cmd *tcl_cmd = (struct hal_tcl_data_cmd *)cmd;
0040
0041     tcl_cmd->buf_addr_info.info0 =
0042         FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr);
0043     tcl_cmd->buf_addr_info.info1 =
0044         FIELD_PREP(BUFFER_ADDR_INFO1_ADDR,
0045                ((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT));
0046     tcl_cmd->buf_addr_info.info1 |=
0047         FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR,
0048                (ti->ring_id + HAL_RX_BUF_RBM_SW0_BM)) |
0049         FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id);
0050
0051     tcl_cmd->info0 =
0052         FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) |
0053         FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) |
0054         FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE,
0055                ti->encrypt_type) |
0056         FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE,
0057                ti->search_type) |
0058         FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN,
0059                ti->addr_search_flags) |
0060         FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM,
0061                ti->meta_data_flags);
0062
0063     tcl_cmd->info1 = ti->flags0 |
0064         FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_DATA_LEN, ti->data_len) |
0065         FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET, ti->pkt_offset);
0066
0067     tcl_cmd->info2 = ti->flags1 |
0068         FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID, ti->tid) |
0069         FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_LMAC_ID, ti->lmac_id);
0070
0071     tcl_cmd->info3 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX,
0072                     ti->dscp_tid_tbl_idx) |
0073              FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX,
0074                     ti->bss_ast_idx) |
0075              FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM,
0076                     ti->bss_ast_hash);
0077     tcl_cmd->info4 = 0;
0078
0079     if (ti->enable_mesh)
0080         ab->hw_params.hw_ops->tx_mesh_enable(ab, tcl_cmd);
0081 }
0082
0083 void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id)
0084 {
0085     u32 ctrl_reg_val;
0086     u32 addr;
0087     u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE];
0088     int i;
0089     u32 value;
0090     int cnt = 0;
0091
0092     ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
0093                      HAL_TCL1_RING_CMN_CTRL_REG);
0094     /* Enable read/write access */
0095     ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
0096     ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
0097                HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val);
0098
0099     addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +
0100            (4 * id * (HAL_DSCP_TID_TBL_SIZE / 4));
0101
0102     /* Configure each DSCP-TID mapping in three bits there by configure
0103      * three bytes in an iteration.
0104      */
0105     for (i = 0; i < DSCP_TID_MAP_TBL_ENTRY_SIZE; i += 8) {
0106         value = FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP0,
0107                    dscp_tid_map[i]) |
0108             FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1,
0109                    dscp_tid_map[i + 1]) |
0110             FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2,
0111                    dscp_tid_map[i + 2]) |
0112             FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3,
0113                    dscp_tid_map[i + 3]) |
0114             FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP4,
0115                    dscp_tid_map[i + 4]) |
0116             FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP5,
0117                    dscp_tid_map[i + 5]) |
0118             FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP6,
0119                    dscp_tid_map[i + 6]) |
0120             FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP7,
0121                    dscp_tid_map[i + 7]);
0122         memcpy(&hw_map_val[cnt], (u8 *)&value, 3);
0123         cnt += 3;
0124     }
0125
0126     for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) {
0127         ath11k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]);
0128         addr += 4;
0129     }
0130
0131     /* Disable read/write access */
0132     ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
0133                      HAL_TCL1_RING_CMN_CTRL_REG);
0134     ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
0135     ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
0136                HAL_TCL1_RING_CMN_CTRL_REG,
0137                ctrl_reg_val);
0138 }
0139
0140 void ath11k_hal_tx_init_data_ring(struct ath11k_base *ab, struct hal_srng *srng)
0141 {
0142     struct hal_srng_params params;
0143     struct hal_tlv_hdr *tlv;
0144     int i, entry_size;
0145     u8 *desc;
0146
0147     memset(&params, 0, sizeof(params));
0148
0149     entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_TCL_DATA);
0150     ath11k_hal_srng_get_params(ab, srng, &params);
0151     desc = (u8 *)params.ring_base_vaddr;
0152
0153     for (i = 0; i < params.num_entries; i++) {
0154         tlv = (struct hal_tlv_hdr *)desc;
0155         tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_TCL_DATA_CMD) |
0156               FIELD_PREP(HAL_TLV_HDR_LEN,
0157                      sizeof(struct hal_tcl_data_cmd));
0158         desc += entry_size;
0159     }
0160 }