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0006 #ifndef ATH11K_HAL_RX_H
0007 #define ATH11K_HAL_RX_H
0008
0009 struct hal_rx_wbm_rel_info {
0010 u32 cookie;
0011 enum hal_wbm_rel_src_module err_rel_src;
0012 enum hal_reo_dest_ring_push_reason push_reason;
0013 u32 err_code;
0014 bool first_msdu;
0015 bool last_msdu;
0016 };
0017
0018 #define HAL_INVALID_PEERID 0xffff
0019 #define VHT_SIG_SU_NSS_MASK 0x7
0020
0021 #define HAL_RX_MAX_MCS 12
0022 #define HAL_RX_MAX_NSS 8
0023
0024 struct hal_rx_mon_status_tlv_hdr {
0025 u32 hdr;
0026 u8 value[];
0027 };
0028
0029 enum hal_rx_su_mu_coding {
0030 HAL_RX_SU_MU_CODING_BCC,
0031 HAL_RX_SU_MU_CODING_LDPC,
0032 HAL_RX_SU_MU_CODING_MAX,
0033 };
0034
0035 enum hal_rx_gi {
0036 HAL_RX_GI_0_8_US,
0037 HAL_RX_GI_0_4_US,
0038 HAL_RX_GI_1_6_US,
0039 HAL_RX_GI_3_2_US,
0040 HAL_RX_GI_MAX,
0041 };
0042
0043 enum hal_rx_bw {
0044 HAL_RX_BW_20MHZ,
0045 HAL_RX_BW_40MHZ,
0046 HAL_RX_BW_80MHZ,
0047 HAL_RX_BW_160MHZ,
0048 HAL_RX_BW_MAX,
0049 };
0050
0051 enum hal_rx_preamble {
0052 HAL_RX_PREAMBLE_11A,
0053 HAL_RX_PREAMBLE_11B,
0054 HAL_RX_PREAMBLE_11N,
0055 HAL_RX_PREAMBLE_11AC,
0056 HAL_RX_PREAMBLE_11AX,
0057 HAL_RX_PREAMBLE_MAX,
0058 };
0059
0060 enum hal_rx_reception_type {
0061 HAL_RX_RECEPTION_TYPE_SU,
0062 HAL_RX_RECEPTION_TYPE_MU_MIMO,
0063 HAL_RX_RECEPTION_TYPE_MU_OFDMA,
0064 HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
0065 HAL_RX_RECEPTION_TYPE_MAX,
0066 };
0067
0068 #define HAL_RX_FCS_LEN 4
0069
0070 enum hal_rx_mon_status {
0071 HAL_RX_MON_STATUS_PPDU_NOT_DONE,
0072 HAL_RX_MON_STATUS_PPDU_DONE,
0073 HAL_RX_MON_STATUS_BUF_DONE,
0074 };
0075
0076 struct hal_rx_user_status {
0077 u32 mcs:4,
0078 nss:3,
0079 ofdma_info_valid:1,
0080 dl_ofdma_ru_start_index:7,
0081 dl_ofdma_ru_width:7,
0082 dl_ofdma_ru_size:8;
0083 u32 ul_ofdma_user_v0_word0;
0084 u32 ul_ofdma_user_v0_word1;
0085 u32 ast_index;
0086 u32 tid;
0087 u16 tcp_msdu_count;
0088 u16 udp_msdu_count;
0089 u16 other_msdu_count;
0090 u16 frame_control;
0091 u8 frame_control_info_valid;
0092 u8 data_sequence_control_info_valid;
0093 u16 first_data_seq_ctrl;
0094 u32 preamble_type;
0095 u16 ht_flags;
0096 u16 vht_flags;
0097 u16 he_flags;
0098 u8 rs_flags;
0099 u32 mpdu_cnt_fcs_ok;
0100 u32 mpdu_cnt_fcs_err;
0101 u32 mpdu_fcs_ok_bitmap[8];
0102 u32 mpdu_ok_byte_count;
0103 u32 mpdu_err_byte_count;
0104 };
0105
0106 #define HAL_TLV_STATUS_PPDU_NOT_DONE HAL_RX_MON_STATUS_PPDU_NOT_DONE
0107 #define HAL_TLV_STATUS_PPDU_DONE HAL_RX_MON_STATUS_PPDU_DONE
0108 #define HAL_TLV_STATUS_BUF_DONE HAL_RX_MON_STATUS_BUF_DONE
0109
0110 struct hal_sw_mon_ring_entries {
0111 dma_addr_t mon_dst_paddr;
0112 dma_addr_t mon_status_paddr;
0113 u32 mon_dst_sw_cookie;
0114 u32 mon_status_sw_cookie;
0115 void *dst_buf_addr_info;
0116 void *status_buf_addr_info;
0117 u16 ppdu_id;
0118 u8 status_buf_count;
0119 u8 msdu_cnt;
0120 bool end_of_ppdu;
0121 bool drop_ppdu;
0122 };
0123
0124 struct hal_rx_mon_ppdu_info {
0125 u32 ppdu_id;
0126 u32 ppdu_ts;
0127 u32 num_mpdu_fcs_ok;
0128 u32 num_mpdu_fcs_err;
0129 u32 preamble_type;
0130 u16 chan_num;
0131 u16 tcp_msdu_count;
0132 u16 tcp_ack_msdu_count;
0133 u16 udp_msdu_count;
0134 u16 other_msdu_count;
0135 u16 peer_id;
0136 u8 rate;
0137 u8 mcs;
0138 u8 nss;
0139 u8 bw;
0140 u8 vht_flag_values1;
0141 u8 vht_flag_values2;
0142 u8 vht_flag_values3[4];
0143 u8 vht_flag_values4;
0144 u8 vht_flag_values5;
0145 u16 vht_flag_values6;
0146 u8 is_stbc;
0147 u8 gi;
0148 u8 ldpc;
0149 u8 beamformed;
0150 u8 rssi_comb;
0151 u8 rssi_chain_pri20[HAL_RX_MAX_NSS];
0152 u8 tid;
0153 u16 ht_flags;
0154 u16 vht_flags;
0155 u16 he_flags;
0156 u16 he_mu_flags;
0157 u8 dcm;
0158 u8 ru_alloc;
0159 u8 reception_type;
0160 u64 tsft;
0161 u64 rx_duration;
0162 u16 frame_control;
0163 u32 ast_index;
0164 u8 rs_fcs_err;
0165 u8 rs_flags;
0166 u8 cck_flag;
0167 u8 ofdm_flag;
0168 u8 ulofdma_flag;
0169 u8 frame_control_info_valid;
0170 u16 he_per_user_1;
0171 u16 he_per_user_2;
0172 u8 he_per_user_position;
0173 u8 he_per_user_known;
0174 u16 he_flags1;
0175 u16 he_flags2;
0176 u8 he_RU[4];
0177 u16 he_data1;
0178 u16 he_data2;
0179 u16 he_data3;
0180 u16 he_data4;
0181 u16 he_data5;
0182 u16 he_data6;
0183 u32 ppdu_len;
0184 u32 prev_ppdu_id;
0185 u32 device_id;
0186 u16 first_data_seq_ctrl;
0187 u8 monitor_direct_used;
0188 u8 data_sequence_control_info_valid;
0189 u8 ltf_size;
0190 u8 rxpcu_filter_pass;
0191 char rssi_chain[8][8];
0192 struct hal_rx_user_status userstats;
0193 };
0194
0195 #define HAL_RX_PPDU_START_INFO0_PPDU_ID GENMASK(15, 0)
0196
0197 struct hal_rx_ppdu_start {
0198 __le32 info0;
0199 __le32 chan_num;
0200 __le32 ppdu_start_ts;
0201 } __packed;
0202
0203 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR GENMASK(25, 16)
0204
0205 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK GENMASK(8, 0)
0206 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID BIT(9)
0207 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID BIT(10)
0208 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID BIT(11)
0209 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE GENMASK(23, 20)
0210
0211 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX GENMASK(15, 0)
0212 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL GENMASK(31, 16)
0213
0214 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL GENMASK(31, 16)
0215
0216 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT GENMASK(15, 0)
0217 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT GENMASK(31, 16)
0218
0219 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT GENMASK(15, 0)
0220 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT GENMASK(31, 16)
0221
0222 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP GENMASK(15, 0)
0223 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP GENMASK(31, 16)
0224
0225 #define HAL_RX_PPDU_END_USER_STATS_RSVD2_6_MPDU_OK_BYTE_COUNT GENMASK(24, 0)
0226 #define HAL_RX_PPDU_END_USER_STATS_RSVD2_8_MPDU_ERR_BYTE_COUNT GENMASK(24, 0)
0227
0228 struct hal_rx_ppdu_end_user_stats {
0229 __le32 rsvd0[2];
0230 __le32 info0;
0231 __le32 info1;
0232 __le32 info2;
0233 __le32 info3;
0234 __le32 ht_ctrl;
0235 __le32 rsvd1[2];
0236 __le32 info4;
0237 __le32 info5;
0238 __le32 info6;
0239 __le32 rsvd2[11];
0240 } __packed;
0241
0242 struct hal_rx_ppdu_end_user_stats_ext {
0243 u32 info0;
0244 u32 info1;
0245 u32 info2;
0246 u32 info3;
0247 u32 info4;
0248 u32 info5;
0249 u32 info6;
0250 } __packed;
0251
0252 #define HAL_RX_HT_SIG_INFO_INFO0_MCS GENMASK(6, 0)
0253 #define HAL_RX_HT_SIG_INFO_INFO0_BW BIT(7)
0254
0255 #define HAL_RX_HT_SIG_INFO_INFO1_STBC GENMASK(5, 4)
0256 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING BIT(6)
0257 #define HAL_RX_HT_SIG_INFO_INFO1_GI BIT(7)
0258
0259 struct hal_rx_ht_sig_info {
0260 __le32 info0;
0261 __le32 info1;
0262 } __packed;
0263
0264 #define HAL_RX_LSIG_B_INFO_INFO0_RATE GENMASK(3, 0)
0265 #define HAL_RX_LSIG_B_INFO_INFO0_LEN GENMASK(15, 4)
0266
0267 struct hal_rx_lsig_b_info {
0268 __le32 info0;
0269 } __packed;
0270
0271 #define HAL_RX_LSIG_A_INFO_INFO0_RATE GENMASK(3, 0)
0272 #define HAL_RX_LSIG_A_INFO_INFO0_LEN GENMASK(16, 5)
0273 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE GENMASK(27, 24)
0274
0275 struct hal_rx_lsig_a_info {
0276 __le32 info0;
0277 } __packed;
0278
0279 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW GENMASK(1, 0)
0280 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC BIT(3)
0281 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID GENMASK(9, 4)
0282 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS GENMASK(21, 10)
0283
0284 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING GENMASK(1, 0)
0285 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING BIT(2)
0286 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS GENMASK(7, 4)
0287 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED BIT(8)
0288
0289 struct hal_rx_vht_sig_a_info {
0290 __le32 info0;
0291 __le32 info1;
0292 } __packed;
0293
0294 enum hal_rx_vht_sig_a_gi_setting {
0295 HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
0296 HAL_RX_VHT_SIG_A_SHORT_GI = 1,
0297 HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
0298 };
0299
0300 #define HAL_RX_SU_MU_CODING_LDPC 0x01
0301
0302 #define HE_GI_0_8 0
0303 #define HE_GI_0_4 1
0304 #define HE_GI_1_6 2
0305 #define HE_GI_3_2 3
0306
0307 #define HE_LTF_1_X 0
0308 #define HE_LTF_2_X 1
0309 #define HE_LTF_4_X 2
0310 #define HE_LTF_UNKNOWN 3
0311
0312 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS GENMASK(6, 3)
0313 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM BIT(7)
0314 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW GENMASK(20, 19)
0315 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE GENMASK(22, 21)
0316 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS GENMASK(25, 23)
0317 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR GENMASK(13, 8)
0318 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE GENMASK(18, 15)
0319 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND BIT(0)
0320 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE BIT(1)
0321 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG BIT(2)
0322
0323 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
0324 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING BIT(7)
0325 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA BIT(8)
0326 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC BIT(9)
0327 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF BIT(10)
0328 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR GENMASK(12, 11)
0329 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM BIT(13)
0330 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND BIT(15)
0331
0332 struct hal_rx_he_sig_a_su_info {
0333 __le32 info0;
0334 __le32 info1;
0335 } __packed;
0336
0337 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_UL_FLAG BIT(1)
0338 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_MCS_OF_SIGB GENMASK(3, 1)
0339 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DCM_OF_SIGB BIT(4)
0340 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_BSS_COLOR GENMASK(10, 5)
0341 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_SPATIAL_REUSE GENMASK(14, 11)
0342 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW GENMASK(17, 15)
0343 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_NUM_SIGB_SYMB GENMASK(21, 18)
0344 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_COMP_MODE_SIGB BIT(22)
0345 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE GENMASK(24, 23)
0346 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_DOPPLER_INDICATION BIT(25)
0347
0348 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXOP_DURATION GENMASK(6, 0)
0349 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_CODING BIT(7)
0350 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_NUM_LTF_SYMB GENMASK(10, 8)
0351 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_LDPC_EXTRA BIT(11)
0352 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC BIT(12)
0353 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_TXBF BIT(10)
0354 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_FACTOR GENMASK(14, 13)
0355 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_PKT_EXT_PE_DISAM BIT(15)
0356
0357 struct hal_rx_he_sig_a_mu_dl_info {
0358 __le32 info0;
0359 __le32 info1;
0360 } __packed;
0361
0362 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION GENMASK(7, 0)
0363
0364 struct hal_rx_he_sig_b1_mu_info {
0365 __le32 info0;
0366 } __packed;
0367
0368 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID GENMASK(10, 0)
0369 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS GENMASK(18, 15)
0370 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING BIT(20)
0371 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS GENMASK(31, 29)
0372
0373 struct hal_rx_he_sig_b2_mu_info {
0374 __le32 info0;
0375 } __packed;
0376
0377 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID GENMASK(10, 0)
0378 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS GENMASK(13, 11)
0379 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF BIT(19)
0380 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS GENMASK(18, 15)
0381 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM BIT(19)
0382 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING BIT(20)
0383
0384 struct hal_rx_he_sig_b2_ofdma_info {
0385 __le32 info0;
0386 } __packed;
0387
0388 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB GENMASK(15, 8)
0389
0390 #define HAL_RX_PHYRX_RSSI_PREAMBLE_PRI20 GENMASK(7, 0)
0391
0392 struct hal_rx_phyrx_chain_rssi {
0393 __le32 rssi_2040;
0394 __le32 rssi_80;
0395 } __packed;
0396
0397 struct hal_rx_phyrx_rssi_legacy_info {
0398 __le32 rsvd[3];
0399 struct hal_rx_phyrx_chain_rssi pre_rssi[HAL_RX_MAX_NSS];
0400 struct hal_rx_phyrx_chain_rssi preamble[HAL_RX_MAX_NSS];
0401 __le32 info0;
0402 } __packed;
0403
0404 #define HAL_RX_MPDU_INFO_INFO0_PEERID GENMASK(31, 16)
0405 #define HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855 GENMASK(15, 0)
0406 #define HAL_RX_MPDU_INFO_INFO1_MPDU_LEN GENMASK(13, 0)
0407
0408 struct hal_rx_mpdu_info {
0409 __le32 rsvd0;
0410 __le32 info0;
0411 __le32 rsvd1[11];
0412 __le32 info1;
0413 __le32 rsvd2[9];
0414 } __packed;
0415
0416 struct hal_rx_mpdu_info_wcn6855 {
0417 __le32 rsvd0[8];
0418 __le32 info0;
0419 __le32 rsvd1[14];
0420 } __packed;
0421
0422 #define HAL_RX_PPDU_END_DURATION GENMASK(23, 0)
0423 struct hal_rx_ppdu_end_duration {
0424 __le32 rsvd0[9];
0425 __le32 info0;
0426 __le32 rsvd1[4];
0427 } __packed;
0428
0429 struct hal_rx_rxpcu_classification_overview {
0430 u32 rsvd0;
0431 } __packed;
0432
0433 struct hal_rx_msdu_desc_info {
0434 u32 msdu_flags;
0435 u16 msdu_len;
0436 };
0437
0438 #define HAL_RX_NUM_MSDU_DESC 6
0439 struct hal_rx_msdu_list {
0440 struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
0441 u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
0442 u8 rbm[HAL_RX_NUM_MSDU_DESC];
0443 };
0444
0445 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
0446 struct hal_reo_status *status);
0447 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
0448 struct hal_reo_status *status);
0449 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
0450 struct hal_reo_status *status);
0451 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
0452 struct hal_reo_status *status);
0453 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
0454 struct hal_reo_status *status);
0455 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
0456 u32 *reo_desc,
0457 struct hal_reo_status *status);
0458 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
0459 u32 *reo_desc,
0460 struct hal_reo_status *status);
0461 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
0462 u32 *reo_desc,
0463 struct hal_reo_status *status);
0464 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status);
0465 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
0466 u32 *msdu_cookies,
0467 enum hal_rx_buf_return_buf_manager *rbm);
0468 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
0469 void *link_desc,
0470 enum hal_wbm_rel_bm_act action);
0471 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
0472 u32 cookie, u8 manager);
0473 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
0474 u32 *cookie, u8 *rbm);
0475 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
0476 dma_addr_t *paddr, u32 *desc_bank);
0477 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
0478 struct hal_rx_wbm_rel_info *rel_info);
0479 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
0480 dma_addr_t *paddr, u32 *desc_bank);
0481 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
0482 dma_addr_t *paddr, u32 *sw_cookie,
0483 void **pp_buf_addr_info, u8 *rbm,
0484 u32 *msdu_cnt);
0485 void
0486 ath11k_hal_rx_sw_mon_ring_buf_paddr_get(void *rx_desc,
0487 struct hal_sw_mon_ring_entries *sw_mon_ent);
0488 enum hal_rx_mon_status
0489 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
0490 struct hal_rx_mon_ppdu_info *ppdu_info,
0491 struct sk_buff *skb);
0492
0493 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
0494 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
0495 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
0496 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
0497 #endif
