Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
0002 /*
0003  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
0004  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
0005  */
0006 
0007 #ifndef ATH11K_HAL_H
0008 #define ATH11K_HAL_H
0009 
0010 #include "hal_desc.h"
0011 #include "rx_desc.h"
0012 
0013 struct ath11k_base;
0014 
0015 #define HAL_LINK_DESC_SIZE          (32 << 2)
0016 #define HAL_LINK_DESC_ALIGN         128
0017 #define HAL_NUM_MPDUS_PER_LINK_DESC     6
0018 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC      7
0019 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC      6
0020 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC   12
0021 #define HAL_MAX_AVAIL_BLK_RES           3
0022 
0023 #define HAL_RING_BASE_ALIGN 8
0024 
0025 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX   32704
0026 /* TODO: Check with hw team on the supported scatter buf size */
0027 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE  8
0028 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
0029                        HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE)
0030 
0031 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX    48
0032 #define HAL_DSCP_TID_TBL_SIZE           24
0033 
0034 /* calculate the register address from bar0 of shadow register x */
0035 #define HAL_SHADOW_BASE_ADDR(ab)        ab->hw_params.regs->hal_shadow_base_addr
0036 #define HAL_SHADOW_NUM_REGS         36
0037 #define HAL_HP_OFFSET_IN_REG_START      1
0038 #define HAL_OFFSET_FROM_HP_TO_TP        4
0039 
0040 #define HAL_SHADOW_REG(ab, x) (HAL_SHADOW_BASE_ADDR(ab) + (4 * (x)))
0041 
0042 /* WCSS Relative address */
0043 #define HAL_SEQ_WCSS_UMAC_OFFSET        0x00a00000
0044 #define HAL_SEQ_WCSS_UMAC_REO_REG       0x00a38000
0045 #define HAL_SEQ_WCSS_UMAC_TCL_REG       0x00a44000
0046 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \
0047         (ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)
0048 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) \
0049         (ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)
0050 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) \
0051         (ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)
0052 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) \
0053         (ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)
0054 #define HAL_SEQ_WCSS_UMAC_WBM_REG       0x00a34000
0055 
0056 #define HAL_CE_WFSS_CE_REG_BASE         0x01b80000
0057 #define HAL_WLAON_REG_BASE          0x01f80000
0058 
0059 /* SW2TCL(x) R0 ring configuration address */
0060 #define HAL_TCL1_RING_CMN_CTRL_REG      0x00000014
0061 #define HAL_TCL1_RING_DSCP_TID_MAP      0x0000002c
0062 #define HAL_TCL1_RING_BASE_LSB(ab)      ab->hw_params.regs->hal_tcl1_ring_base_lsb
0063 #define HAL_TCL1_RING_BASE_MSB(ab)      ab->hw_params.regs->hal_tcl1_ring_base_msb
0064 #define HAL_TCL1_RING_ID(ab)            ab->hw_params.regs->hal_tcl1_ring_id
0065 #define HAL_TCL1_RING_MISC(ab)          ab->hw_params.regs->hal_tcl1_ring_misc
0066 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \
0067     ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb
0068 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \
0069     ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb
0070 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \
0071     ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0
0072 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \
0073     ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1
0074 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \
0075     ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb
0076 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \
0077     ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb
0078 #define HAL_TCL1_RING_MSI1_DATA(ab) \
0079     ab->hw_params.regs->hal_tcl1_ring_msi1_data
0080 #define HAL_TCL2_RING_BASE_LSB(ab)      ab->hw_params.regs->hal_tcl2_ring_base_lsb
0081 #define HAL_TCL_RING_BASE_LSB(ab)       ab->hw_params.regs->hal_tcl_ring_base_lsb
0082 
0083 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab)              \
0084     (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0085 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab)              \
0086     (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0087 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab)              \
0088     (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0089 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab)               \
0090     (HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0091 #define HAL_TCL1_RING_ID_OFFSET(ab)             \
0092     (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0093 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab)            \
0094     (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0095 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \
0096         (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0097 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \
0098         (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0099 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \
0100         (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0101 #define HAL_TCL1_RING_MISC_OFFSET(ab) \
0102         (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab))
0103 
0104 /* SW2TCL(x) R2 ring pointers (head/tail) address */
0105 #define HAL_TCL1_RING_HP            0x00002000
0106 #define HAL_TCL1_RING_TP            0x00002004
0107 #define HAL_TCL2_RING_HP            0x00002008
0108 #define HAL_TCL_RING_HP             0x00002018
0109 
0110 #define HAL_TCL1_RING_TP_OFFSET \
0111         (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
0112 
0113 /* TCL STATUS ring address */
0114 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \
0115     ab->hw_params.regs->hal_tcl_status_ring_base_lsb
0116 #define HAL_TCL_STATUS_RING_HP          0x00002030
0117 
0118 /* REO2SW(x) R0 ring configuration address */
0119 #define HAL_REO1_GEN_ENABLE         0x00000000
0120 #define HAL_REO1_DEST_RING_CTRL_IX_0        0x00000004
0121 #define HAL_REO1_DEST_RING_CTRL_IX_1        0x00000008
0122 #define HAL_REO1_DEST_RING_CTRL_IX_2        0x0000000c
0123 #define HAL_REO1_DEST_RING_CTRL_IX_3        0x00000010
0124 #define HAL_REO1_MISC_CTL(ab)           ab->hw_params.regs->hal_reo1_misc_ctl
0125 #define HAL_REO1_RING_BASE_LSB(ab)      ab->hw_params.regs->hal_reo1_ring_base_lsb
0126 #define HAL_REO1_RING_BASE_MSB(ab)      ab->hw_params.regs->hal_reo1_ring_base_msb
0127 #define HAL_REO1_RING_ID(ab)            ab->hw_params.regs->hal_reo1_ring_id
0128 #define HAL_REO1_RING_MISC(ab)          ab->hw_params.regs->hal_reo1_ring_misc
0129 #define HAL_REO1_RING_HP_ADDR_LSB(ab) \
0130     ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb
0131 #define HAL_REO1_RING_HP_ADDR_MSB(ab) \
0132     ab->hw_params.regs->hal_reo1_ring_hp_addr_msb
0133 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \
0134     ab->hw_params.regs->hal_reo1_ring_producer_int_setup
0135 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \
0136     ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb
0137 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \
0138     ab->hw_params.regs->hal_reo1_ring_msi1_base_msb
0139 #define HAL_REO1_RING_MSI1_DATA(ab) \
0140     ab->hw_params.regs->hal_reo1_ring_msi1_data
0141 #define HAL_REO2_RING_BASE_LSB(ab)      ab->hw_params.regs->hal_reo2_ring_base_lsb
0142 #define HAL_REO1_AGING_THRESH_IX_0(ab) \
0143     ab->hw_params.regs->hal_reo1_aging_thresh_ix_0
0144 #define HAL_REO1_AGING_THRESH_IX_1(ab) \
0145     ab->hw_params.regs->hal_reo1_aging_thresh_ix_1
0146 #define HAL_REO1_AGING_THRESH_IX_2(ab) \
0147     ab->hw_params.regs->hal_reo1_aging_thresh_ix_2
0148 #define HAL_REO1_AGING_THRESH_IX_3(ab) \
0149     ab->hw_params.regs->hal_reo1_aging_thresh_ix_3
0150 
0151 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) \
0152         (HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
0153 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) \
0154         (HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
0155 #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) \
0156         (HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab))
0157 #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) \
0158         (HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
0159 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab))
0160 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) \
0161         (HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab))
0162 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) \
0163         (HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
0164 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) \
0165         (HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
0166 #define HAL_REO1_RING_MISC_OFFSET(ab) \
0167     (HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab))
0168 
0169 /* REO2SW(x) R2 ring pointers (head/tail) address */
0170 #define HAL_REO1_RING_HP(ab)            ab->hw_params.regs->hal_reo1_ring_hp
0171 #define HAL_REO1_RING_TP(ab)            ab->hw_params.regs->hal_reo1_ring_tp
0172 #define HAL_REO2_RING_HP(ab)            ab->hw_params.regs->hal_reo2_ring_hp
0173 
0174 #define HAL_REO1_RING_TP_OFFSET(ab) (HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab))
0175 
0176 /* REO2TCL R0 ring configuration address */
0177 #define HAL_REO_TCL_RING_BASE_LSB(ab) \
0178     ab->hw_params.regs->hal_reo_tcl_ring_base_lsb
0179 
0180 /* REO2TCL R2 ring pointer (head/tail) address */
0181 #define HAL_REO_TCL_RING_HP(ab)         ab->hw_params.regs->hal_reo_tcl_ring_hp
0182 
0183 /* REO CMD R0 address */
0184 #define HAL_REO_CMD_RING_BASE_LSB(ab) \
0185     ab->hw_params.regs->hal_reo_cmd_ring_base_lsb
0186 
0187 /* REO CMD R2 address */
0188 #define HAL_REO_CMD_HP(ab)          ab->hw_params.regs->hal_reo_cmd_ring_hp
0189 
0190 /* SW2REO R0 address */
0191 #define HAL_SW2REO_RING_BASE_LSB(ab) \
0192     ab->hw_params.regs->hal_sw2reo_ring_base_lsb
0193 
0194 /* SW2REO R2 address */
0195 #define HAL_SW2REO_RING_HP(ab)          ab->hw_params.regs->hal_sw2reo_ring_hp
0196 
0197 /* CE ring R0 address */
0198 #define HAL_CE_DST_RING_BASE_LSB        0x00000000
0199 #define HAL_CE_DST_STATUS_RING_BASE_LSB     0x00000058
0200 #define HAL_CE_DST_RING_CTRL            0x000000b0
0201 
0202 /* CE ring R2 address */
0203 #define HAL_CE_DST_RING_HP          0x00000400
0204 #define HAL_CE_DST_STATUS_RING_HP       0x00000408
0205 
0206 /* REO status address */
0207 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \
0208     ab->hw_params.regs->hal_reo_status_ring_base_lsb
0209 #define HAL_REO_STATUS_HP(ab)           ab->hw_params.regs->hal_reo_status_hp
0210 
0211 /* WBM Idle R0 address */
0212 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \
0213         (ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)
0214 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \
0215         (ab->hw_params.regs->hal_wbm_idle_link_ring_misc)
0216 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR   0x00000048
0217 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR      0x0000004c
0218 #define HAL_WBM_SCATTERED_RING_BASE_LSB     0x00000058
0219 #define HAL_WBM_SCATTERED_RING_BASE_MSB     0x0000005c
0220 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068
0221 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c
0222 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078
0223 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c
0224 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR   0x00000084
0225 
0226 /* WBM Idle R2 address */
0227 #define HAL_WBM_IDLE_LINK_RING_HP       0x000030b0
0228 
0229 /* SW2WBM R0 release address */
0230 #define HAL_WBM_RELEASE_RING_BASE_LSB(x) \
0231         (ab->hw_params.regs->hal_wbm_release_ring_base_lsb)
0232 
0233 /* SW2WBM R2 release address */
0234 #define HAL_WBM_RELEASE_RING_HP         0x00003018
0235 
0236 /* WBM2SW R0 release address */
0237 #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \
0238         (ab->hw_params.regs->hal_wbm0_release_ring_base_lsb)
0239 #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \
0240         (ab->hw_params.regs->hal_wbm1_release_ring_base_lsb)
0241 
0242 /* WBM2SW R2 release address */
0243 #define HAL_WBM0_RELEASE_RING_HP        0x000030c0
0244 #define HAL_WBM1_RELEASE_RING_HP        0x000030c8
0245 
0246 /* TCL ring feild mask and offset */
0247 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE        GENMASK(27, 8)
0248 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB   GENMASK(7, 0)
0249 #define HAL_TCL1_RING_ID_ENTRY_SIZE         GENMASK(7, 0)
0250 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE      BIT(1)
0251 #define HAL_TCL1_RING_MISC_MSI_SWAP         BIT(3)
0252 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP         BIT(4)
0253 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP        BIT(5)
0254 #define HAL_TCL1_RING_MISC_SRNG_ENABLE          BIT(6)
0255 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD   GENMASK(31, 16)
0256 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
0257 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
0258 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE     BIT(8)
0259 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR        GENMASK(7, 0)
0260 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17)
0261 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP        GENMASK(31, 0)
0262 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0       GENMASK(2, 0)
0263 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1       GENMASK(5, 3)
0264 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2       GENMASK(8, 6)
0265 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3       GENMASK(11, 9)
0266 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4       GENMASK(14, 12)
0267 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5       GENMASK(17, 15)
0268 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6       GENMASK(20, 18)
0269 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7       GENMASK(23, 21)
0270 
0271 /* REO ring feild mask and offset */
0272 #define HAL_REO1_RING_BASE_MSB_RING_SIZE        GENMASK(27, 8)
0273 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB   GENMASK(7, 0)
0274 #define HAL_REO1_RING_ID_RING_ID            GENMASK(15, 8)
0275 #define HAL_REO1_RING_ID_ENTRY_SIZE         GENMASK(7, 0)
0276 #define HAL_REO1_RING_MISC_MSI_SWAP         BIT(3)
0277 #define HAL_REO1_RING_MISC_HOST_FW_SWAP         BIT(4)
0278 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP        BIT(5)
0279 #define HAL_REO1_RING_MISC_SRNG_ENABLE          BIT(6)
0280 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16)
0281 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
0282 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE     BIT(8)
0283 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR        GENMASK(7, 0)
0284 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING       GENMASK(25, 23)
0285 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE       BIT(2)
0286 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE      BIT(3)
0287 #define HAL_REO1_MISC_CTL_FRAGMENT_DST_RING     GENMASK(20, 17)
0288 
0289 /* CE ring bit field mask and shift */
0290 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN         GENMASK(15, 0)
0291 
0292 #define HAL_ADDR_LSB_REG_MASK               0xffffffff
0293 
0294 #define HAL_ADDR_MSB_REG_SHIFT              32
0295 
0296 /* WBM ring bit field mask and shift */
0297 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE        BIT(1)
0298 #define HAL_WBM_SCATTER_BUFFER_SIZE         GENMASK(10, 2)
0299 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)
0300 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32  GENMASK(7, 0)
0301 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG  GENMASK(31, 8)
0302 
0303 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1    GENMASK(20, 8)
0304 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1    GENMASK(20, 8)
0305 
0306 #define BASE_ADDR_MATCH_TAG_VAL 0x5
0307 
0308 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE     0x000fffff
0309 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE     0x000fffff
0310 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE      0x0000ffff
0311 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE     0x0000ffff
0312 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE      0x0000ffff
0313 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE     0x000fffff
0314 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE     0x000fffff
0315 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE      0x0000ffff
0316 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE      0x0000ffff
0317 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE      0x0000ffff
0318 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE   0x0000ffff
0319 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE   0x0000ffff
0320 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE  0x0000ffff
0321 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE  0x000fffff
0322 #define HAL_RXDMA_RING_MAX_SIZE             0x0000ffff
0323 
0324 /* Add any other errors here and return them in
0325  * ath11k_hal_rx_desc_get_err().
0326  */
0327 
0328 enum hal_srng_ring_id {
0329     HAL_SRNG_RING_ID_REO2SW1 = 0,
0330     HAL_SRNG_RING_ID_REO2SW2,
0331     HAL_SRNG_RING_ID_REO2SW3,
0332     HAL_SRNG_RING_ID_REO2SW4,
0333     HAL_SRNG_RING_ID_REO2TCL,
0334     HAL_SRNG_RING_ID_SW2REO,
0335 
0336     HAL_SRNG_RING_ID_REO_CMD = 8,
0337     HAL_SRNG_RING_ID_REO_STATUS,
0338 
0339     HAL_SRNG_RING_ID_SW2TCL1 = 16,
0340     HAL_SRNG_RING_ID_SW2TCL2,
0341     HAL_SRNG_RING_ID_SW2TCL3,
0342     HAL_SRNG_RING_ID_SW2TCL4,
0343 
0344     HAL_SRNG_RING_ID_SW2TCL_CMD = 24,
0345     HAL_SRNG_RING_ID_TCL_STATUS,
0346 
0347     HAL_SRNG_RING_ID_CE0_SRC = 32,
0348     HAL_SRNG_RING_ID_CE1_SRC,
0349     HAL_SRNG_RING_ID_CE2_SRC,
0350     HAL_SRNG_RING_ID_CE3_SRC,
0351     HAL_SRNG_RING_ID_CE4_SRC,
0352     HAL_SRNG_RING_ID_CE5_SRC,
0353     HAL_SRNG_RING_ID_CE6_SRC,
0354     HAL_SRNG_RING_ID_CE7_SRC,
0355     HAL_SRNG_RING_ID_CE8_SRC,
0356     HAL_SRNG_RING_ID_CE9_SRC,
0357     HAL_SRNG_RING_ID_CE10_SRC,
0358     HAL_SRNG_RING_ID_CE11_SRC,
0359 
0360     HAL_SRNG_RING_ID_CE0_DST = 56,
0361     HAL_SRNG_RING_ID_CE1_DST,
0362     HAL_SRNG_RING_ID_CE2_DST,
0363     HAL_SRNG_RING_ID_CE3_DST,
0364     HAL_SRNG_RING_ID_CE4_DST,
0365     HAL_SRNG_RING_ID_CE5_DST,
0366     HAL_SRNG_RING_ID_CE6_DST,
0367     HAL_SRNG_RING_ID_CE7_DST,
0368     HAL_SRNG_RING_ID_CE8_DST,
0369     HAL_SRNG_RING_ID_CE9_DST,
0370     HAL_SRNG_RING_ID_CE10_DST,
0371     HAL_SRNG_RING_ID_CE11_DST,
0372 
0373     HAL_SRNG_RING_ID_CE0_DST_STATUS = 80,
0374     HAL_SRNG_RING_ID_CE1_DST_STATUS,
0375     HAL_SRNG_RING_ID_CE2_DST_STATUS,
0376     HAL_SRNG_RING_ID_CE3_DST_STATUS,
0377     HAL_SRNG_RING_ID_CE4_DST_STATUS,
0378     HAL_SRNG_RING_ID_CE5_DST_STATUS,
0379     HAL_SRNG_RING_ID_CE6_DST_STATUS,
0380     HAL_SRNG_RING_ID_CE7_DST_STATUS,
0381     HAL_SRNG_RING_ID_CE8_DST_STATUS,
0382     HAL_SRNG_RING_ID_CE9_DST_STATUS,
0383     HAL_SRNG_RING_ID_CE10_DST_STATUS,
0384     HAL_SRNG_RING_ID_CE11_DST_STATUS,
0385 
0386     HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104,
0387     HAL_SRNG_RING_ID_WBM_SW_RELEASE,
0388     HAL_SRNG_RING_ID_WBM2SW0_RELEASE,
0389     HAL_SRNG_RING_ID_WBM2SW1_RELEASE,
0390     HAL_SRNG_RING_ID_WBM2SW2_RELEASE,
0391     HAL_SRNG_RING_ID_WBM2SW3_RELEASE,
0392 
0393     HAL_SRNG_RING_ID_UMAC_ID_END = 127,
0394     HAL_SRNG_RING_ID_LMAC1_ID_START,
0395 
0396     HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START,
0397     HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF,
0398     HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF,
0399     HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF,
0400     HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF,
0401     HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
0402     HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1,
0403     HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC,
0404     HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
0405 
0406     HAL_SRNG_RING_ID_LMAC1_ID_END = 143
0407 };
0408 
0409 /* SRNG registers are split into two groups R0 and R2 */
0410 #define HAL_SRNG_REG_GRP_R0 0
0411 #define HAL_SRNG_REG_GRP_R2 1
0412 #define HAL_SRNG_NUM_REG_GRP    2
0413 
0414 #define HAL_SRNG_NUM_LMACS      3
0415 #define HAL_SRNG_REO_EXCEPTION  HAL_SRNG_RING_ID_REO2SW1
0416 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \
0417                  HAL_SRNG_RING_ID_LMAC1_ID_START)
0418 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC)
0419 #define HAL_SRNG_RING_ID_MAX    (HAL_SRNG_RING_ID_UMAC_ID_END + \
0420                  HAL_SRNG_NUM_LMAC_RINGS)
0421 
0422 enum hal_ring_type {
0423     HAL_REO_DST,
0424     HAL_REO_EXCEPTION,
0425     HAL_REO_REINJECT,
0426     HAL_REO_CMD,
0427     HAL_REO_STATUS,
0428     HAL_TCL_DATA,
0429     HAL_TCL_CMD,
0430     HAL_TCL_STATUS,
0431     HAL_CE_SRC,
0432     HAL_CE_DST,
0433     HAL_CE_DST_STATUS,
0434     HAL_WBM_IDLE_LINK,
0435     HAL_SW2WBM_RELEASE,
0436     HAL_WBM2SW_RELEASE,
0437     HAL_RXDMA_BUF,
0438     HAL_RXDMA_DST,
0439     HAL_RXDMA_MONITOR_BUF,
0440     HAL_RXDMA_MONITOR_STATUS,
0441     HAL_RXDMA_MONITOR_DST,
0442     HAL_RXDMA_MONITOR_DESC,
0443     HAL_RXDMA_DIR_BUF,
0444     HAL_MAX_RING_TYPES,
0445 };
0446 
0447 #define HAL_RX_MAX_BA_WINDOW    256
0448 
0449 #define HAL_DEFAULT_REO_TIMEOUT_USEC        (40 * 1000)
0450 
0451 /**
0452  * enum hal_reo_cmd_type: Enum for REO command type
0453  * @CMD_GET_QUEUE_STATS: Get REO queue status/stats
0454  * @CMD_FLUSH_QUEUE: Flush all frames in REO queue
0455  * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
0456  * @CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked
0457  *      earlier with a 'REO_FLUSH_CACHE' command
0458  * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
0459  * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
0460  */
0461 enum hal_reo_cmd_type {
0462     HAL_REO_CMD_GET_QUEUE_STATS     = 0,
0463     HAL_REO_CMD_FLUSH_QUEUE         = 1,
0464     HAL_REO_CMD_FLUSH_CACHE         = 2,
0465     HAL_REO_CMD_UNBLOCK_CACHE       = 3,
0466     HAL_REO_CMD_FLUSH_TIMEOUT_LIST  = 4,
0467     HAL_REO_CMD_UPDATE_RX_QUEUE     = 5,
0468 };
0469 
0470 /**
0471  * enum hal_reo_cmd_status: Enum for execution status of REO command
0472  * @HAL_REO_CMD_SUCCESS: Command has successfully executed
0473  * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue
0474  *           or cache was blocked
0475  * @HAL_REO_CMD_FAILED: Command execution failed, could be due to
0476  *          invalid queue desc
0477  * @HAL_REO_CMD_RESOURCE_BLOCKED:
0478  * @HAL_REO_CMD_DRAIN:
0479  */
0480 enum hal_reo_cmd_status {
0481     HAL_REO_CMD_SUCCESS     = 0,
0482     HAL_REO_CMD_BLOCKED     = 1,
0483     HAL_REO_CMD_FAILED      = 2,
0484     HAL_REO_CMD_RESOURCE_BLOCKED    = 3,
0485     HAL_REO_CMD_DRAIN       = 0xff,
0486 };
0487 
0488 struct hal_wbm_idle_scatter_list {
0489     dma_addr_t paddr;
0490     struct hal_wbm_link_desc *vaddr;
0491 };
0492 
0493 struct hal_srng_params {
0494     dma_addr_t ring_base_paddr;
0495     u32 *ring_base_vaddr;
0496     int num_entries;
0497     u32 intr_batch_cntr_thres_entries;
0498     u32 intr_timer_thres_us;
0499     u32 flags;
0500     u32 max_buffer_len;
0501     u32 low_threshold;
0502     dma_addr_t msi_addr;
0503     u32 msi_data;
0504 
0505     /* Add more params as needed */
0506 };
0507 
0508 enum hal_srng_dir {
0509     HAL_SRNG_DIR_SRC,
0510     HAL_SRNG_DIR_DST
0511 };
0512 
0513 /* srng flags */
0514 #define HAL_SRNG_FLAGS_MSI_SWAP         0x00000008
0515 #define HAL_SRNG_FLAGS_RING_PTR_SWAP        0x00000010
0516 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP        0x00000020
0517 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN   0x00010000
0518 #define HAL_SRNG_FLAGS_MSI_INTR         0x00020000
0519 #define HAL_SRNG_FLAGS_CACHED                   0x20000000
0520 #define HAL_SRNG_FLAGS_LMAC_RING        0x80000000
0521 
0522 #define HAL_SRNG_TLV_HDR_TAG        GENMASK(9, 1)
0523 #define HAL_SRNG_TLV_HDR_LEN        GENMASK(25, 10)
0524 
0525 /* Common SRNG ring structure for source and destination rings */
0526 struct hal_srng {
0527     /* Unique SRNG ring ID */
0528     u8 ring_id;
0529 
0530     /* Ring initialization done */
0531     u8 initialized;
0532 
0533     /* Interrupt/MSI value assigned to this ring */
0534     int irq;
0535 
0536     /* Physical base address of the ring */
0537     dma_addr_t ring_base_paddr;
0538 
0539     /* Virtual base address of the ring */
0540     u32 *ring_base_vaddr;
0541 
0542     /* Number of entries in ring */
0543     u32 num_entries;
0544 
0545     /* Ring size */
0546     u32 ring_size;
0547 
0548     /* Ring size mask */
0549     u32 ring_size_mask;
0550 
0551     /* Size of ring entry */
0552     u32 entry_size;
0553 
0554     /* Interrupt timer threshold - in micro seconds */
0555     u32 intr_timer_thres_us;
0556 
0557     /* Interrupt batch counter threshold - in number of ring entries */
0558     u32 intr_batch_cntr_thres_entries;
0559 
0560     /* MSI Address */
0561     dma_addr_t msi_addr;
0562 
0563     /* MSI data */
0564     u32 msi_data;
0565 
0566     /* Misc flags */
0567     u32 flags;
0568 
0569     /* Lock for serializing ring index updates */
0570     spinlock_t lock;
0571 
0572     /* Start offset of SRNG register groups for this ring
0573      * TBD: See if this is required - register address can be derived
0574      * from ring ID
0575      */
0576     u32 hwreg_base[HAL_SRNG_NUM_REG_GRP];
0577 
0578     u64 timestamp;
0579 
0580     /* Source or Destination ring */
0581     enum hal_srng_dir ring_dir;
0582 
0583     union {
0584         struct {
0585             /* SW tail pointer */
0586             u32 tp;
0587 
0588             /* Shadow head pointer location to be updated by HW */
0589             volatile u32 *hp_addr;
0590 
0591             /* Cached head pointer */
0592             u32 cached_hp;
0593 
0594             /* Tail pointer location to be updated by SW - This
0595              * will be a register address and need not be
0596              * accessed through SW structure
0597              */
0598             u32 *tp_addr;
0599 
0600             /* Current SW loop cnt */
0601             u32 loop_cnt;
0602 
0603             /* max transfer size */
0604             u16 max_buffer_length;
0605 
0606             /* head pointer at access end */
0607             u32 last_hp;
0608         } dst_ring;
0609 
0610         struct {
0611             /* SW head pointer */
0612             u32 hp;
0613 
0614             /* SW reap head pointer */
0615             u32 reap_hp;
0616 
0617             /* Shadow tail pointer location to be updated by HW */
0618             u32 *tp_addr;
0619 
0620             /* Cached tail pointer */
0621             u32 cached_tp;
0622 
0623             /* Head pointer location to be updated by SW - This
0624              * will be a register address and need not be accessed
0625              * through SW structure
0626              */
0627             u32 *hp_addr;
0628 
0629             /* Low threshold - in number of ring entries */
0630             u32 low_threshold;
0631 
0632             /* tail pointer at access end */
0633             u32 last_tp;
0634         } src_ring;
0635     } u;
0636 };
0637 
0638 /* Interrupt mitigation - Batch threshold in terms of numer of frames */
0639 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256
0640 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128
0641 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1
0642 
0643 /* Interrupt mitigation - timer threshold in us */
0644 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000
0645 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500
0646 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256
0647 
0648 /* HW SRNG configuration table */
0649 struct hal_srng_config {
0650     int start_ring_id;
0651     u16 max_rings;
0652     u16 entry_size;
0653     u32 reg_start[HAL_SRNG_NUM_REG_GRP];
0654     u16 reg_size[HAL_SRNG_NUM_REG_GRP];
0655     u8 lmac_ring;
0656     enum hal_srng_dir ring_dir;
0657     u32 max_size;
0658 };
0659 
0660 /**
0661  * enum hal_rx_buf_return_buf_manager
0662  *
0663  * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
0664  * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
0665  *  descriptor list.
0666  * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
0667  * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
0668  * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
0669  * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
0670  * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
0671  */
0672 
0673 enum hal_rx_buf_return_buf_manager {
0674     HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST,
0675     HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST,
0676     HAL_RX_BUF_RBM_FW_BM,
0677     HAL_RX_BUF_RBM_SW0_BM,
0678     HAL_RX_BUF_RBM_SW1_BM,
0679     HAL_RX_BUF_RBM_SW2_BM,
0680     HAL_RX_BUF_RBM_SW3_BM,
0681 };
0682 
0683 #define HAL_SRNG_DESC_LOOP_CNT      0xf0000000
0684 
0685 #define HAL_REO_CMD_FLG_NEED_STATUS     BIT(0)
0686 #define HAL_REO_CMD_FLG_STATS_CLEAR     BIT(1)
0687 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER   BIT(2)
0688 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING  BIT(3)
0689 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL      BIT(4)
0690 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5)
0691 #define HAL_REO_CMD_FLG_FLUSH_ALL       BIT(6)
0692 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE      BIT(7)
0693 #define HAL_REO_CMD_FLG_UNBLK_CACHE     BIT(8)
0694 
0695 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */
0696 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM       BIT(8)
0697 #define HAL_REO_CMD_UPD0_VLD            BIT(9)
0698 #define HAL_REO_CMD_UPD0_ALDC           BIT(10)
0699 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION  BIT(11)
0700 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN    BIT(12)
0701 #define HAL_REO_CMD_UPD0_AC         BIT(13)
0702 #define HAL_REO_CMD_UPD0_BAR            BIT(14)
0703 #define HAL_REO_CMD_UPD0_RETRY          BIT(15)
0704 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE      BIT(16)
0705 #define HAL_REO_CMD_UPD0_OOR_MODE       BIT(17)
0706 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE     BIT(18)
0707 #define HAL_REO_CMD_UPD0_PN_CHECK       BIT(19)
0708 #define HAL_REO_CMD_UPD0_EVEN_PN        BIT(20)
0709 #define HAL_REO_CMD_UPD0_UNEVEN_PN      BIT(21)
0710 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE   BIT(22)
0711 #define HAL_REO_CMD_UPD0_PN_SIZE        BIT(23)
0712 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG   BIT(24)
0713 #define HAL_REO_CMD_UPD0_SVLD           BIT(25)
0714 #define HAL_REO_CMD_UPD0_SSN            BIT(26)
0715 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR     BIT(27)
0716 #define HAL_REO_CMD_UPD0_PN_ERR         BIT(28)
0717 #define HAL_REO_CMD_UPD0_PN_VALID       BIT(29)
0718 #define HAL_REO_CMD_UPD0_PN         BIT(30)
0719 
0720 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */
0721 #define HAL_REO_CMD_UPD1_VLD            BIT(16)
0722 #define HAL_REO_CMD_UPD1_ALDC           GENMASK(18, 17)
0723 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION  BIT(19)
0724 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN    BIT(20)
0725 #define HAL_REO_CMD_UPD1_AC         GENMASK(22, 21)
0726 #define HAL_REO_CMD_UPD1_BAR            BIT(23)
0727 #define HAL_REO_CMD_UPD1_RETRY          BIT(24)
0728 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE      BIT(25)
0729 #define HAL_REO_CMD_UPD1_OOR_MODE       BIT(26)
0730 #define HAL_REO_CMD_UPD1_PN_CHECK       BIT(27)
0731 #define HAL_REO_CMD_UPD1_EVEN_PN        BIT(28)
0732 #define HAL_REO_CMD_UPD1_UNEVEN_PN      BIT(29)
0733 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE   BIT(30)
0734 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG   BIT(31)
0735 
0736 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */
0737 #define HAL_REO_CMD_UPD2_SVLD           BIT(10)
0738 #define HAL_REO_CMD_UPD2_SSN            GENMASK(22, 11)
0739 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR     BIT(23)
0740 #define HAL_REO_CMD_UPD2_PN_ERR         BIT(24)
0741 
0742 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP    GENMASK(31, 8)
0743 
0744 struct ath11k_hal_reo_cmd {
0745     u32 addr_lo;
0746     u32 flag;
0747     u32 upd0;
0748     u32 upd1;
0749     u32 upd2;
0750     u32 pn[4];
0751     u16 rx_queue_num;
0752     u16 min_rel;
0753     u16 min_fwd;
0754     u8 addr_hi;
0755     u8 ac_list;
0756     u8 blocking_idx;
0757     u16 ba_window_size;
0758     u8 pn_size;
0759 };
0760 
0761 enum hal_pn_type {
0762     HAL_PN_TYPE_NONE,
0763     HAL_PN_TYPE_WPA,
0764     HAL_PN_TYPE_WAPI_EVEN,
0765     HAL_PN_TYPE_WAPI_UNEVEN,
0766 };
0767 
0768 enum hal_ce_desc {
0769     HAL_CE_DESC_SRC,
0770     HAL_CE_DESC_DST,
0771     HAL_CE_DESC_DST_STATUS,
0772 };
0773 
0774 #define HAL_HASH_ROUTING_RING_TCL 0
0775 #define HAL_HASH_ROUTING_RING_SW1 1
0776 #define HAL_HASH_ROUTING_RING_SW2 2
0777 #define HAL_HASH_ROUTING_RING_SW3 3
0778 #define HAL_HASH_ROUTING_RING_SW4 4
0779 #define HAL_HASH_ROUTING_RING_REL 5
0780 #define HAL_HASH_ROUTING_RING_FW  6
0781 
0782 struct hal_reo_status_header {
0783     u16 cmd_num;
0784     enum hal_reo_cmd_status cmd_status;
0785     u16 cmd_exe_time;
0786     u32 timestamp;
0787 };
0788 
0789 struct hal_reo_status_queue_stats {
0790     u16 ssn;
0791     u16 curr_idx;
0792     u32 pn[4];
0793     u32 last_rx_queue_ts;
0794     u32 last_rx_dequeue_ts;
0795     u32 rx_bitmap[8]; /* Bitmap from 0-255 */
0796     u32 curr_mpdu_cnt;
0797     u32 curr_msdu_cnt;
0798     u16 fwd_due_to_bar_cnt;
0799     u16 dup_cnt;
0800     u32 frames_in_order_cnt;
0801     u32 num_mpdu_processed_cnt;
0802     u32 num_msdu_processed_cnt;
0803     u32 total_num_processed_byte_cnt;
0804     u32 late_rx_mpdu_cnt;
0805     u32 reorder_hole_cnt;
0806     u8 timeout_cnt;
0807     u8 bar_rx_cnt;
0808     u8 num_window_2k_jump_cnt;
0809 };
0810 
0811 struct hal_reo_status_flush_queue {
0812     bool err_detected;
0813 };
0814 
0815 enum hal_reo_status_flush_cache_err_code {
0816     HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS,
0817     HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE,
0818     HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND,
0819 };
0820 
0821 struct hal_reo_status_flush_cache {
0822     bool err_detected;
0823     enum hal_reo_status_flush_cache_err_code err_code;
0824     bool cache_controller_flush_status_hit;
0825     u8 cache_controller_flush_status_desc_type;
0826     u8 cache_controller_flush_status_client_id;
0827     u8 cache_controller_flush_status_err;
0828     u8 cache_controller_flush_status_cnt;
0829 };
0830 
0831 enum hal_reo_status_unblock_cache_type {
0832     HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE,
0833     HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE,
0834 };
0835 
0836 struct hal_reo_status_unblock_cache {
0837     bool err_detected;
0838     enum hal_reo_status_unblock_cache_type unblock_type;
0839 };
0840 
0841 struct hal_reo_status_flush_timeout_list {
0842     bool err_detected;
0843     bool list_empty;
0844     u16 release_desc_cnt;
0845     u16 fwd_buf_cnt;
0846 };
0847 
0848 enum hal_reo_threshold_idx {
0849     HAL_REO_THRESHOLD_IDX_DESC_COUNTER0,
0850     HAL_REO_THRESHOLD_IDX_DESC_COUNTER1,
0851     HAL_REO_THRESHOLD_IDX_DESC_COUNTER2,
0852     HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM,
0853 };
0854 
0855 struct hal_reo_status_desc_thresh_reached {
0856     enum hal_reo_threshold_idx threshold_idx;
0857     u32 link_desc_counter0;
0858     u32 link_desc_counter1;
0859     u32 link_desc_counter2;
0860     u32 link_desc_counter_sum;
0861 };
0862 
0863 struct hal_reo_status {
0864     struct hal_reo_status_header uniform_hdr;
0865     u8 loop_cnt;
0866     union {
0867         struct hal_reo_status_queue_stats queue_stats;
0868         struct hal_reo_status_flush_queue flush_queue;
0869         struct hal_reo_status_flush_cache flush_cache;
0870         struct hal_reo_status_unblock_cache unblock_cache;
0871         struct hal_reo_status_flush_timeout_list timeout_list;
0872         struct hal_reo_status_desc_thresh_reached desc_thresh_reached;
0873     } u;
0874 };
0875 
0876 /**
0877  * HAL context to be used to access SRNG APIs (currently used by data path
0878  * and transport (CE) modules)
0879  */
0880 struct ath11k_hal {
0881     /* HAL internal state for all SRNG rings.
0882      */
0883     struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX];
0884 
0885     /* SRNG configuration table */
0886     struct hal_srng_config *srng_config;
0887 
0888     /* Remote pointer memory for HW/FW updates */
0889     struct {
0890         u32 *vaddr;
0891         dma_addr_t paddr;
0892     } rdp;
0893 
0894     /* Shared memory for ring pointer updates from host to FW */
0895     struct {
0896         u32 *vaddr;
0897         dma_addr_t paddr;
0898     } wrp;
0899 
0900     /* Available REO blocking resources bitmap */
0901     u8 avail_blk_resource;
0902 
0903     u8 current_blk_index;
0904 
0905     /* shadow register configuration */
0906     u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS];
0907     int num_shadow_reg_configured;
0908 
0909     struct lock_class_key srng_key[HAL_SRNG_RING_ID_MAX];
0910 };
0911 
0912 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid);
0913 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
0914                 u32 start_seq, enum hal_pn_type type);
0915 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
0916                   struct hal_srng *srng);
0917 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
0918                      struct hal_wbm_idle_scatter_list *sbuf,
0919                      u32 nsbufs, u32 tot_link_desc,
0920                      u32 end_offset);
0921 
0922 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab,
0923                        struct hal_srng *srng);
0924 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab,
0925                        struct hal_srng *srng);
0926 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie,
0927                    dma_addr_t paddr);
0928 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type);
0929 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id,
0930                 u8 byte_swap_data);
0931 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr);
0932 u32 ath11k_hal_ce_dst_status_get_length(void *buf);
0933 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type);
0934 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type);
0935 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng,
0936                 struct hal_srng_params *params);
0937 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab,
0938                     struct hal_srng *srng);
0939 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng);
0940 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng,
0941                  bool sync_hw_ptr);
0942 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng);
0943 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab,
0944                      struct hal_srng *srng);
0945 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab,
0946                    struct hal_srng *srng);
0947 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab,
0948                     struct hal_srng *srng);
0949 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng,
0950                  bool sync_hw_ptr);
0951 void ath11k_hal_srng_access_begin(struct ath11k_base *ab,
0952                   struct hal_srng *srng);
0953 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng);
0954 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
0955               int ring_num, int mac_id,
0956               struct hal_srng_params *params);
0957 int ath11k_hal_srng_init(struct ath11k_base *ath11k);
0958 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k);
0959 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab);
0960 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab,
0961                        u32 **cfg, u32 *len);
0962 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab,
0963                      enum hal_ring_type ring_type,
0964                     int ring_num);
0965 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab);
0966 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab,
0967                      struct hal_srng *srng);
0968 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!