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0001 // SPDX-License-Identifier: BSD-3-Clause-Clear
0002 /*
0003  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include "core.h"
0007 #include "dp_tx.h"
0008 #include "debug.h"
0009 #include "debugfs_sta.h"
0010 #include "hw.h"
0011 #include "peer.h"
0012 #include "mac.h"
0013 
0014 static enum hal_tcl_encap_type
0015 ath11k_dp_tx_get_encap_type(struct ath11k_vif *arvif, struct sk_buff *skb)
0016 {
0017     struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
0018     struct ath11k_base *ab = arvif->ar->ab;
0019 
0020     if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags))
0021         return HAL_TCL_ENCAP_TYPE_RAW;
0022 
0023     if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
0024         return HAL_TCL_ENCAP_TYPE_ETHERNET;
0025 
0026     return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
0027 }
0028 
0029 static void ath11k_dp_tx_encap_nwifi(struct sk_buff *skb)
0030 {
0031     struct ieee80211_hdr *hdr = (void *)skb->data;
0032     u8 *qos_ctl;
0033 
0034     if (!ieee80211_is_data_qos(hdr->frame_control))
0035         return;
0036 
0037     qos_ctl = ieee80211_get_qos_ctl(hdr);
0038     memmove(skb->data + IEEE80211_QOS_CTL_LEN,
0039         skb->data, (void *)qos_ctl - (void *)skb->data);
0040     skb_pull(skb, IEEE80211_QOS_CTL_LEN);
0041 
0042     hdr = (void *)skb->data;
0043     hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
0044 }
0045 
0046 static u8 ath11k_dp_tx_get_tid(struct sk_buff *skb)
0047 {
0048     struct ieee80211_hdr *hdr = (void *)skb->data;
0049     struct ath11k_skb_cb *cb = ATH11K_SKB_CB(skb);
0050 
0051     if (cb->flags & ATH11K_SKB_HW_80211_ENCAP)
0052         return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
0053     else if (!ieee80211_is_data_qos(hdr->frame_control))
0054         return HAL_DESC_REO_NON_QOS_TID;
0055     else
0056         return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
0057 }
0058 
0059 enum hal_encrypt_type ath11k_dp_tx_get_encrypt_type(u32 cipher)
0060 {
0061     switch (cipher) {
0062     case WLAN_CIPHER_SUITE_WEP40:
0063         return HAL_ENCRYPT_TYPE_WEP_40;
0064     case WLAN_CIPHER_SUITE_WEP104:
0065         return HAL_ENCRYPT_TYPE_WEP_104;
0066     case WLAN_CIPHER_SUITE_TKIP:
0067         return HAL_ENCRYPT_TYPE_TKIP_MIC;
0068     case WLAN_CIPHER_SUITE_CCMP:
0069         return HAL_ENCRYPT_TYPE_CCMP_128;
0070     case WLAN_CIPHER_SUITE_CCMP_256:
0071         return HAL_ENCRYPT_TYPE_CCMP_256;
0072     case WLAN_CIPHER_SUITE_GCMP:
0073         return HAL_ENCRYPT_TYPE_GCMP_128;
0074     case WLAN_CIPHER_SUITE_GCMP_256:
0075         return HAL_ENCRYPT_TYPE_AES_GCMP_256;
0076     default:
0077         return HAL_ENCRYPT_TYPE_OPEN;
0078     }
0079 }
0080 
0081 int ath11k_dp_tx(struct ath11k *ar, struct ath11k_vif *arvif,
0082          struct ath11k_sta *arsta, struct sk_buff *skb)
0083 {
0084     struct ath11k_base *ab = ar->ab;
0085     struct ath11k_dp *dp = &ab->dp;
0086     struct hal_tx_info ti = {0};
0087     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
0088     struct ath11k_skb_cb *skb_cb = ATH11K_SKB_CB(skb);
0089     struct hal_srng *tcl_ring;
0090     struct ieee80211_hdr *hdr = (void *)skb->data;
0091     struct dp_tx_ring *tx_ring;
0092     void *hal_tcl_desc;
0093     u8 pool_id;
0094     u8 hal_ring_id;
0095     int ret;
0096     u8 ring_selector = 0, ring_map = 0;
0097     bool tcl_ring_retry;
0098 
0099     if (unlikely(test_bit(ATH11K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)))
0100         return -ESHUTDOWN;
0101 
0102     if (unlikely(!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
0103              !ieee80211_is_data(hdr->frame_control)))
0104         return -ENOTSUPP;
0105 
0106     pool_id = skb_get_queue_mapping(skb) & (ATH11K_HW_MAX_QUEUES - 1);
0107 
0108     /* Let the default ring selection be based on current processor
0109      * number, where one of the 3 tcl rings are selected based on
0110      * the smp_processor_id(). In case that ring
0111      * is full/busy, we resort to other available rings.
0112      * If all rings are full, we drop the packet.
0113      * //TODO Add throttling logic when all rings are full
0114      */
0115     ring_selector = smp_processor_id();
0116 
0117 tcl_ring_sel:
0118     tcl_ring_retry = false;
0119 
0120     ti.ring_id = ring_selector % ab->hw_params.max_tx_ring;
0121 
0122     ring_map |= BIT(ti.ring_id);
0123 
0124     tx_ring = &dp->tx_ring[ti.ring_id];
0125 
0126     spin_lock_bh(&tx_ring->tx_idr_lock);
0127     ret = idr_alloc(&tx_ring->txbuf_idr, skb, 0,
0128             DP_TX_IDR_SIZE - 1, GFP_ATOMIC);
0129     spin_unlock_bh(&tx_ring->tx_idr_lock);
0130 
0131     if (unlikely(ret < 0)) {
0132         if (ring_map == (BIT(ab->hw_params.max_tx_ring) - 1)) {
0133             atomic_inc(&ab->soc_stats.tx_err.misc_fail);
0134             return -ENOSPC;
0135         }
0136 
0137         /* Check if the next ring is available */
0138         ring_selector++;
0139         goto tcl_ring_sel;
0140     }
0141 
0142     ti.desc_id = FIELD_PREP(DP_TX_DESC_ID_MAC_ID, ar->pdev_idx) |
0143              FIELD_PREP(DP_TX_DESC_ID_MSDU_ID, ret) |
0144              FIELD_PREP(DP_TX_DESC_ID_POOL_ID, pool_id);
0145     ti.encap_type = ath11k_dp_tx_get_encap_type(arvif, skb);
0146 
0147     if (ieee80211_has_a4(hdr->frame_control) &&
0148         is_multicast_ether_addr(hdr->addr3) && arsta &&
0149         arsta->use_4addr_set) {
0150         ti.meta_data_flags = arsta->tcl_metadata;
0151         ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TO_FW, 1);
0152     } else {
0153         ti.meta_data_flags = arvif->tcl_metadata;
0154     }
0155 
0156     if (unlikely(ti.encap_type == HAL_TCL_ENCAP_TYPE_RAW)) {
0157         if (skb_cb->flags & ATH11K_SKB_CIPHER_SET) {
0158             ti.encrypt_type =
0159                 ath11k_dp_tx_get_encrypt_type(skb_cb->cipher);
0160 
0161             if (ieee80211_has_protected(hdr->frame_control))
0162                 skb_put(skb, IEEE80211_CCMP_MIC_LEN);
0163         } else {
0164             ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
0165         }
0166     }
0167 
0168     ti.addr_search_flags = arvif->hal_addr_search_flags;
0169     ti.search_type = arvif->search_type;
0170     ti.type = HAL_TCL_DESC_TYPE_BUFFER;
0171     ti.pkt_offset = 0;
0172     ti.lmac_id = ar->lmac_id;
0173     ti.bss_ast_hash = arvif->ast_hash;
0174     ti.bss_ast_idx = arvif->ast_idx;
0175     ti.dscp_tid_tbl_idx = 0;
0176 
0177     if (likely(skb->ip_summed == CHECKSUM_PARTIAL &&
0178            ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW)) {
0179         ti.flags0 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN, 1) |
0180                  FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN, 1) |
0181                  FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN, 1) |
0182                  FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN, 1) |
0183                  FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN, 1);
0184     }
0185 
0186     if (ieee80211_vif_is_mesh(arvif->vif))
0187         ti.enable_mesh = true;
0188 
0189     ti.flags1 |= FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE, 1);
0190 
0191     ti.tid = ath11k_dp_tx_get_tid(skb);
0192 
0193     switch (ti.encap_type) {
0194     case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
0195         ath11k_dp_tx_encap_nwifi(skb);
0196         break;
0197     case HAL_TCL_ENCAP_TYPE_RAW:
0198         if (!test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) {
0199             ret = -EINVAL;
0200             goto fail_remove_idr;
0201         }
0202         break;
0203     case HAL_TCL_ENCAP_TYPE_ETHERNET:
0204         /* no need to encap */
0205         break;
0206     case HAL_TCL_ENCAP_TYPE_802_3:
0207     default:
0208         /* TODO: Take care of other encap modes as well */
0209         ret = -EINVAL;
0210         atomic_inc(&ab->soc_stats.tx_err.misc_fail);
0211         goto fail_remove_idr;
0212     }
0213 
0214     ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
0215     if (unlikely(dma_mapping_error(ab->dev, ti.paddr))) {
0216         atomic_inc(&ab->soc_stats.tx_err.misc_fail);
0217         ath11k_warn(ab, "failed to DMA map data Tx buffer\n");
0218         ret = -ENOMEM;
0219         goto fail_remove_idr;
0220     }
0221 
0222     ti.data_len = skb->len;
0223     skb_cb->paddr = ti.paddr;
0224     skb_cb->vif = arvif->vif;
0225     skb_cb->ar = ar;
0226 
0227     hal_ring_id = tx_ring->tcl_data_ring.ring_id;
0228     tcl_ring = &ab->hal.srng_list[hal_ring_id];
0229 
0230     spin_lock_bh(&tcl_ring->lock);
0231 
0232     ath11k_hal_srng_access_begin(ab, tcl_ring);
0233 
0234     hal_tcl_desc = (void *)ath11k_hal_srng_src_get_next_entry(ab, tcl_ring);
0235     if (unlikely(!hal_tcl_desc)) {
0236         /* NOTE: It is highly unlikely we'll be running out of tcl_ring
0237          * desc because the desc is directly enqueued onto hw queue.
0238          */
0239         ath11k_hal_srng_access_end(ab, tcl_ring);
0240         ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
0241         spin_unlock_bh(&tcl_ring->lock);
0242         ret = -ENOMEM;
0243 
0244         /* Checking for available tcl descritors in another ring in
0245          * case of failure due to full tcl ring now, is better than
0246          * checking this ring earlier for each pkt tx.
0247          * Restart ring selection if some rings are not checked yet.
0248          */
0249         if (unlikely(ring_map != (BIT(ab->hw_params.max_tx_ring)) - 1) &&
0250             ab->hw_params.max_tx_ring > 1) {
0251             tcl_ring_retry = true;
0252             ring_selector++;
0253         }
0254 
0255         goto fail_unmap_dma;
0256     }
0257 
0258     ath11k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc +
0259                      sizeof(struct hal_tlv_hdr), &ti);
0260 
0261     ath11k_hal_srng_access_end(ab, tcl_ring);
0262 
0263     ath11k_dp_shadow_start_timer(ab, tcl_ring, &dp->tx_ring_timer[ti.ring_id]);
0264 
0265     spin_unlock_bh(&tcl_ring->lock);
0266 
0267     ath11k_dbg_dump(ab, ATH11K_DBG_DP_TX, NULL, "dp tx msdu: ",
0268             skb->data, skb->len);
0269 
0270     atomic_inc(&ar->dp.num_tx_pending);
0271 
0272     return 0;
0273 
0274 fail_unmap_dma:
0275     dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
0276 
0277 fail_remove_idr:
0278     spin_lock_bh(&tx_ring->tx_idr_lock);
0279     idr_remove(&tx_ring->txbuf_idr,
0280            FIELD_GET(DP_TX_DESC_ID_MSDU_ID, ti.desc_id));
0281     spin_unlock_bh(&tx_ring->tx_idr_lock);
0282 
0283     if (tcl_ring_retry)
0284         goto tcl_ring_sel;
0285 
0286     return ret;
0287 }
0288 
0289 static void ath11k_dp_tx_free_txbuf(struct ath11k_base *ab, u8 mac_id,
0290                     int msdu_id,
0291                     struct dp_tx_ring *tx_ring)
0292 {
0293     struct ath11k *ar;
0294     struct sk_buff *msdu;
0295     struct ath11k_skb_cb *skb_cb;
0296 
0297     spin_lock(&tx_ring->tx_idr_lock);
0298     msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
0299     spin_unlock(&tx_ring->tx_idr_lock);
0300 
0301     if (unlikely(!msdu)) {
0302         ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
0303                 msdu_id);
0304         return;
0305     }
0306 
0307     skb_cb = ATH11K_SKB_CB(msdu);
0308 
0309     dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
0310     dev_kfree_skb_any(msdu);
0311 
0312     ar = ab->pdevs[mac_id].ar;
0313     if (atomic_dec_and_test(&ar->dp.num_tx_pending))
0314         wake_up(&ar->dp.tx_empty_waitq);
0315 }
0316 
0317 static void
0318 ath11k_dp_tx_htt_tx_complete_buf(struct ath11k_base *ab,
0319                  struct dp_tx_ring *tx_ring,
0320                  struct ath11k_dp_htt_wbm_tx_status *ts)
0321 {
0322     struct sk_buff *msdu;
0323     struct ieee80211_tx_info *info;
0324     struct ath11k_skb_cb *skb_cb;
0325     struct ath11k *ar;
0326 
0327     spin_lock(&tx_ring->tx_idr_lock);
0328     msdu = idr_remove(&tx_ring->txbuf_idr, ts->msdu_id);
0329     spin_unlock(&tx_ring->tx_idr_lock);
0330 
0331     if (unlikely(!msdu)) {
0332         ath11k_warn(ab, "htt tx completion for unknown msdu_id %d\n",
0333                 ts->msdu_id);
0334         return;
0335     }
0336 
0337     skb_cb = ATH11K_SKB_CB(msdu);
0338     info = IEEE80211_SKB_CB(msdu);
0339 
0340     ar = skb_cb->ar;
0341 
0342     if (atomic_dec_and_test(&ar->dp.num_tx_pending))
0343         wake_up(&ar->dp.tx_empty_waitq);
0344 
0345     dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
0346 
0347     memset(&info->status, 0, sizeof(info->status));
0348 
0349     if (ts->acked) {
0350         if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
0351             info->flags |= IEEE80211_TX_STAT_ACK;
0352             info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
0353                           ts->ack_rssi;
0354             info->status.flags |=
0355                 IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
0356         } else {
0357             info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
0358         }
0359     }
0360 
0361     ieee80211_tx_status(ar->hw, msdu);
0362 }
0363 
0364 static void
0365 ath11k_dp_tx_process_htt_tx_complete(struct ath11k_base *ab,
0366                      void *desc, u8 mac_id,
0367                      u32 msdu_id, struct dp_tx_ring *tx_ring)
0368 {
0369     struct htt_tx_wbm_completion *status_desc;
0370     struct ath11k_dp_htt_wbm_tx_status ts = {0};
0371     enum hal_wbm_htt_tx_comp_status wbm_status;
0372 
0373     status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
0374 
0375     wbm_status = FIELD_GET(HTT_TX_WBM_COMP_INFO0_STATUS,
0376                    status_desc->info0);
0377     switch (wbm_status) {
0378     case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
0379     case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
0380     case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
0381         ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
0382         ts.msdu_id = msdu_id;
0383         ts.ack_rssi = FIELD_GET(HTT_TX_WBM_COMP_INFO1_ACK_RSSI,
0384                     status_desc->info1);
0385         ath11k_dp_tx_htt_tx_complete_buf(ab, tx_ring, &ts);
0386         break;
0387     case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
0388     case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
0389         ath11k_dp_tx_free_txbuf(ab, mac_id, msdu_id, tx_ring);
0390         break;
0391     case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
0392         /* This event is to be handled only when the driver decides to
0393          * use WDS offload functionality.
0394          */
0395         break;
0396     default:
0397         ath11k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
0398         break;
0399     }
0400 }
0401 
0402 static void ath11k_dp_tx_cache_peer_stats(struct ath11k *ar,
0403                       struct sk_buff *msdu,
0404                       struct hal_tx_status *ts)
0405 {
0406     struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
0407 
0408     if (ts->try_cnt > 1) {
0409         peer_stats->retry_pkts += ts->try_cnt - 1;
0410         peer_stats->retry_bytes += (ts->try_cnt - 1) * msdu->len;
0411 
0412         if (ts->status != HAL_WBM_TQM_REL_REASON_FRAME_ACKED) {
0413             peer_stats->failed_pkts += 1;
0414             peer_stats->failed_bytes += msdu->len;
0415         }
0416     }
0417 }
0418 
0419 void ath11k_dp_tx_update_txcompl(struct ath11k *ar, struct hal_tx_status *ts)
0420 {
0421     struct ath11k_base *ab = ar->ab;
0422     struct ath11k_per_peer_tx_stats *peer_stats = &ar->cached_stats;
0423     enum hal_tx_rate_stats_pkt_type pkt_type;
0424     enum hal_tx_rate_stats_sgi sgi;
0425     enum hal_tx_rate_stats_bw bw;
0426     struct ath11k_peer *peer;
0427     struct ath11k_sta *arsta;
0428     struct ieee80211_sta *sta;
0429     u16 rate, ru_tones;
0430     u8 mcs, rate_idx = 0, ofdma;
0431     int ret;
0432 
0433     spin_lock_bh(&ab->base_lock);
0434     peer = ath11k_peer_find_by_id(ab, ts->peer_id);
0435     if (!peer || !peer->sta) {
0436         ath11k_dbg(ab, ATH11K_DBG_DP_TX,
0437                "failed to find the peer by id %u\n", ts->peer_id);
0438         goto err_out;
0439     }
0440 
0441     sta = peer->sta;
0442     arsta = (struct ath11k_sta *)sta->drv_priv;
0443 
0444     memset(&arsta->txrate, 0, sizeof(arsta->txrate));
0445     pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE,
0446                  ts->rate_stats);
0447     mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS,
0448             ts->rate_stats);
0449     sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI,
0450             ts->rate_stats);
0451     bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, ts->rate_stats);
0452     ru_tones = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, ts->rate_stats);
0453     ofdma = FIELD_GET(HAL_TX_RATE_STATS_INFO0_OFDMA_TX, ts->rate_stats);
0454 
0455     /* This is to prefer choose the real NSS value arsta->last_txrate.nss,
0456      * if it is invalid, then choose the NSS value while assoc.
0457      */
0458     if (arsta->last_txrate.nss)
0459         arsta->txrate.nss = arsta->last_txrate.nss;
0460     else
0461         arsta->txrate.nss = arsta->peer_nss;
0462 
0463     if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11A ||
0464         pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11B) {
0465         ret = ath11k_mac_hw_ratecode_to_legacy_rate(mcs,
0466                                 pkt_type,
0467                                 &rate_idx,
0468                                 &rate);
0469         if (ret < 0)
0470             goto err_out;
0471         arsta->txrate.legacy = rate;
0472     } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11N) {
0473         if (mcs > 7) {
0474             ath11k_warn(ab, "Invalid HT mcs index %d\n", mcs);
0475             goto err_out;
0476         }
0477 
0478         if (arsta->txrate.nss != 0)
0479             arsta->txrate.mcs = mcs + 8 * (arsta->txrate.nss - 1);
0480         arsta->txrate.flags = RATE_INFO_FLAGS_MCS;
0481         if (sgi)
0482             arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
0483     } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AC) {
0484         if (mcs > 9) {
0485             ath11k_warn(ab, "Invalid VHT mcs index %d\n", mcs);
0486             goto err_out;
0487         }
0488 
0489         arsta->txrate.mcs = mcs;
0490         arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS;
0491         if (sgi)
0492             arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
0493     } else if (pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
0494         if (mcs > 11) {
0495             ath11k_warn(ab, "Invalid HE mcs index %d\n", mcs);
0496             goto err_out;
0497         }
0498 
0499         arsta->txrate.mcs = mcs;
0500         arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS;
0501         arsta->txrate.he_gi = ath11k_mac_he_gi_to_nl80211_he_gi(sgi);
0502     }
0503 
0504     arsta->txrate.bw = ath11k_mac_bw_to_mac80211_bw(bw);
0505     if (ofdma && pkt_type == HAL_TX_RATE_STATS_PKT_TYPE_11AX) {
0506         arsta->txrate.bw = RATE_INFO_BW_HE_RU;
0507         arsta->txrate.he_ru_alloc =
0508             ath11k_mac_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
0509     }
0510 
0511     if (ath11k_debugfs_is_extd_tx_stats_enabled(ar))
0512         ath11k_debugfs_sta_add_tx_stats(arsta, peer_stats, rate_idx);
0513 
0514 err_out:
0515     spin_unlock_bh(&ab->base_lock);
0516 }
0517 
0518 static void ath11k_dp_tx_complete_msdu(struct ath11k *ar,
0519                        struct sk_buff *msdu,
0520                        struct hal_tx_status *ts)
0521 {
0522     struct ieee80211_tx_status status = { 0 };
0523     struct ieee80211_rate_status status_rate = { 0 };
0524     struct ath11k_base *ab = ar->ab;
0525     struct ieee80211_tx_info *info;
0526     struct ath11k_skb_cb *skb_cb;
0527     struct ath11k_peer *peer;
0528     struct ath11k_sta *arsta;
0529     struct rate_info rate;
0530 
0531     if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
0532         /* Must not happen */
0533         return;
0534     }
0535 
0536     skb_cb = ATH11K_SKB_CB(msdu);
0537 
0538     dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
0539 
0540     if (unlikely(!rcu_access_pointer(ab->pdevs_active[ar->pdev_idx]))) {
0541         dev_kfree_skb_any(msdu);
0542         return;
0543     }
0544 
0545     if (unlikely(!skb_cb->vif)) {
0546         dev_kfree_skb_any(msdu);
0547         return;
0548     }
0549 
0550     info = IEEE80211_SKB_CB(msdu);
0551     memset(&info->status, 0, sizeof(info->status));
0552 
0553     /* skip tx rate update from ieee80211_status*/
0554     info->status.rates[0].idx = -1;
0555 
0556     if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
0557         !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
0558         info->flags |= IEEE80211_TX_STAT_ACK;
0559         info->status.ack_signal = ATH11K_DEFAULT_NOISE_FLOOR +
0560                       ts->ack_rssi;
0561         info->status.flags |= IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
0562     }
0563 
0564     if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
0565         (info->flags & IEEE80211_TX_CTL_NO_ACK))
0566         info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
0567 
0568     if (unlikely(ath11k_debugfs_is_extd_tx_stats_enabled(ar)) ||
0569         ab->hw_params.single_pdev_only) {
0570         if (ts->flags & HAL_TX_STATUS_FLAGS_FIRST_MSDU) {
0571             if (ar->last_ppdu_id == 0) {
0572                 ar->last_ppdu_id = ts->ppdu_id;
0573             } else if (ar->last_ppdu_id == ts->ppdu_id ||
0574                    ar->cached_ppdu_id == ar->last_ppdu_id) {
0575                 ar->cached_ppdu_id = ar->last_ppdu_id;
0576                 ar->cached_stats.is_ampdu = true;
0577                 ath11k_dp_tx_update_txcompl(ar, ts);
0578                 memset(&ar->cached_stats, 0,
0579                        sizeof(struct ath11k_per_peer_tx_stats));
0580             } else {
0581                 ar->cached_stats.is_ampdu = false;
0582                 ath11k_dp_tx_update_txcompl(ar, ts);
0583                 memset(&ar->cached_stats, 0,
0584                        sizeof(struct ath11k_per_peer_tx_stats));
0585             }
0586             ar->last_ppdu_id = ts->ppdu_id;
0587         }
0588 
0589         ath11k_dp_tx_cache_peer_stats(ar, msdu, ts);
0590     }
0591 
0592     spin_lock_bh(&ab->base_lock);
0593     peer = ath11k_peer_find_by_id(ab, ts->peer_id);
0594     if (!peer || !peer->sta) {
0595         ath11k_dbg(ab, ATH11K_DBG_DATA,
0596                "dp_tx: failed to find the peer with peer_id %d\n",
0597                 ts->peer_id);
0598         spin_unlock_bh(&ab->base_lock);
0599         dev_kfree_skb_any(msdu);
0600         return;
0601     }
0602     arsta = (struct ath11k_sta *)peer->sta->drv_priv;
0603     status.sta = peer->sta;
0604     status.skb = msdu;
0605     status.info = info;
0606     rate = arsta->last_txrate;
0607 
0608     status_rate.rate_idx = rate;
0609     status_rate.try_count = 1;
0610 
0611     status.rates = &status_rate;
0612     status.n_rates = 1;
0613 
0614     spin_unlock_bh(&ab->base_lock);
0615 
0616     ieee80211_tx_status_ext(ar->hw, &status);
0617 }
0618 
0619 static inline void ath11k_dp_tx_status_parse(struct ath11k_base *ab,
0620                          struct hal_wbm_release_ring *desc,
0621                          struct hal_tx_status *ts)
0622 {
0623     ts->buf_rel_source =
0624         FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0);
0625     if (unlikely(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
0626              ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM))
0627         return;
0628 
0629     if (unlikely(ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW))
0630         return;
0631 
0632     ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON,
0633                    desc->info0);
0634     ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER,
0635                 desc->info1);
0636     ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT,
0637                 desc->info1);
0638     ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI,
0639                  desc->info2);
0640     if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU)
0641         ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU;
0642     ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3);
0643     ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3);
0644     if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)
0645         ts->rate_stats = desc->rate_stats.info0;
0646     else
0647         ts->rate_stats = 0;
0648 }
0649 
0650 void ath11k_dp_tx_completion_handler(struct ath11k_base *ab, int ring_id)
0651 {
0652     struct ath11k *ar;
0653     struct ath11k_dp *dp = &ab->dp;
0654     int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
0655     struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
0656     struct sk_buff *msdu;
0657     struct hal_tx_status ts = { 0 };
0658     struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
0659     u32 *desc;
0660     u32 msdu_id;
0661     u8 mac_id;
0662 
0663     spin_lock_bh(&status_ring->lock);
0664 
0665     ath11k_hal_srng_access_begin(ab, status_ring);
0666 
0667     while ((ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) !=
0668         tx_ring->tx_status_tail) &&
0669            (desc = ath11k_hal_srng_dst_get_next_entry(ab, status_ring))) {
0670         memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
0671                desc, sizeof(struct hal_wbm_release_ring));
0672         tx_ring->tx_status_head =
0673             ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head);
0674     }
0675 
0676     if (unlikely((ath11k_hal_srng_dst_peek(ab, status_ring) != NULL) &&
0677              (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_head) ==
0678               tx_ring->tx_status_tail))) {
0679         /* TODO: Process pending tx_status messages when kfifo_is_full() */
0680         ath11k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
0681     }
0682 
0683     ath11k_hal_srng_access_end(ab, status_ring);
0684 
0685     spin_unlock_bh(&status_ring->lock);
0686 
0687     while (ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
0688         struct hal_wbm_release_ring *tx_status;
0689         u32 desc_id;
0690 
0691         tx_ring->tx_status_tail =
0692             ATH11K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
0693         tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
0694         ath11k_dp_tx_status_parse(ab, tx_status, &ts);
0695 
0696         desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
0697                     tx_status->buf_addr_info.info1);
0698         mac_id = FIELD_GET(DP_TX_DESC_ID_MAC_ID, desc_id);
0699         msdu_id = FIELD_GET(DP_TX_DESC_ID_MSDU_ID, desc_id);
0700 
0701         if (unlikely(ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)) {
0702             ath11k_dp_tx_process_htt_tx_complete(ab,
0703                                  (void *)tx_status,
0704                                  mac_id, msdu_id,
0705                                  tx_ring);
0706             continue;
0707         }
0708 
0709         spin_lock(&tx_ring->tx_idr_lock);
0710         msdu = idr_remove(&tx_ring->txbuf_idr, msdu_id);
0711         if (unlikely(!msdu)) {
0712             ath11k_warn(ab, "tx completion for unknown msdu_id %d\n",
0713                     msdu_id);
0714             spin_unlock(&tx_ring->tx_idr_lock);
0715             continue;
0716         }
0717 
0718         spin_unlock(&tx_ring->tx_idr_lock);
0719 
0720         ar = ab->pdevs[mac_id].ar;
0721 
0722         if (atomic_dec_and_test(&ar->dp.num_tx_pending))
0723             wake_up(&ar->dp.tx_empty_waitq);
0724 
0725         ath11k_dp_tx_complete_msdu(ar, msdu, &ts);
0726     }
0727 }
0728 
0729 int ath11k_dp_tx_send_reo_cmd(struct ath11k_base *ab, struct dp_rx_tid *rx_tid,
0730                   enum hal_reo_cmd_type type,
0731                   struct ath11k_hal_reo_cmd *cmd,
0732                   void (*cb)(struct ath11k_dp *, void *,
0733                      enum hal_reo_cmd_status))
0734 {
0735     struct ath11k_dp *dp = &ab->dp;
0736     struct dp_reo_cmd *dp_cmd;
0737     struct hal_srng *cmd_ring;
0738     int cmd_num;
0739 
0740     if (test_bit(ATH11K_FLAG_CRASH_FLUSH, &ab->dev_flags))
0741         return -ESHUTDOWN;
0742 
0743     cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id];
0744     cmd_num = ath11k_hal_reo_cmd_send(ab, cmd_ring, type, cmd);
0745 
0746     /* cmd_num should start from 1, during failure return the error code */
0747     if (cmd_num < 0)
0748         return cmd_num;
0749 
0750     /* reo cmd ring descriptors has cmd_num starting from 1 */
0751     if (cmd_num == 0)
0752         return -EINVAL;
0753 
0754     if (!cb)
0755         return 0;
0756 
0757     /* Can this be optimized so that we keep the pending command list only
0758      * for tid delete command to free up the resoruce on the command status
0759      * indication?
0760      */
0761     dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC);
0762 
0763     if (!dp_cmd)
0764         return -ENOMEM;
0765 
0766     memcpy(&dp_cmd->data, rx_tid, sizeof(struct dp_rx_tid));
0767     dp_cmd->cmd_num = cmd_num;
0768     dp_cmd->handler = cb;
0769 
0770     spin_lock_bh(&dp->reo_cmd_lock);
0771     list_add_tail(&dp_cmd->list, &dp->reo_cmd_list);
0772     spin_unlock_bh(&dp->reo_cmd_lock);
0773 
0774     return 0;
0775 }
0776 
0777 static int
0778 ath11k_dp_tx_get_ring_id_type(struct ath11k_base *ab,
0779                   int mac_id, u32 ring_id,
0780                   enum hal_ring_type ring_type,
0781                   enum htt_srng_ring_type *htt_ring_type,
0782                   enum htt_srng_ring_id *htt_ring_id)
0783 {
0784     int lmac_ring_id_offset = 0;
0785     int ret = 0;
0786 
0787     switch (ring_type) {
0788     case HAL_RXDMA_BUF:
0789         lmac_ring_id_offset = mac_id * HAL_SRNG_RINGS_PER_LMAC;
0790 
0791         /* for QCA6390, host fills rx buffer to fw and fw fills to
0792          * rxbuf ring for each rxdma
0793          */
0794         if (!ab->hw_params.rx_mac_buf_ring) {
0795             if (!(ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF +
0796                       lmac_ring_id_offset) ||
0797                 ring_id == (HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF +
0798                     lmac_ring_id_offset))) {
0799                 ret = -EINVAL;
0800             }
0801             *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
0802             *htt_ring_type = HTT_SW_TO_HW_RING;
0803         } else {
0804             if (ring_id == HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF) {
0805                 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
0806                 *htt_ring_type = HTT_SW_TO_SW_RING;
0807             } else {
0808                 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
0809                 *htt_ring_type = HTT_SW_TO_HW_RING;
0810             }
0811         }
0812         break;
0813     case HAL_RXDMA_DST:
0814         *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
0815         *htt_ring_type = HTT_HW_TO_SW_RING;
0816         break;
0817     case HAL_RXDMA_MONITOR_BUF:
0818         *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
0819         *htt_ring_type = HTT_SW_TO_HW_RING;
0820         break;
0821     case HAL_RXDMA_MONITOR_STATUS:
0822         *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
0823         *htt_ring_type = HTT_SW_TO_HW_RING;
0824         break;
0825     case HAL_RXDMA_MONITOR_DST:
0826         *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
0827         *htt_ring_type = HTT_HW_TO_SW_RING;
0828         break;
0829     case HAL_RXDMA_MONITOR_DESC:
0830         *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
0831         *htt_ring_type = HTT_SW_TO_HW_RING;
0832         break;
0833     default:
0834         ath11k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
0835         ret = -EINVAL;
0836     }
0837     return ret;
0838 }
0839 
0840 int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id,
0841                 int mac_id, enum hal_ring_type ring_type)
0842 {
0843     struct htt_srng_setup_cmd *cmd;
0844     struct hal_srng *srng = &ab->hal.srng_list[ring_id];
0845     struct hal_srng_params params;
0846     struct sk_buff *skb;
0847     u32 ring_entry_sz;
0848     int len = sizeof(*cmd);
0849     dma_addr_t hp_addr, tp_addr;
0850     enum htt_srng_ring_type htt_ring_type;
0851     enum htt_srng_ring_id htt_ring_id;
0852     int ret;
0853 
0854     skb = ath11k_htc_alloc_skb(ab, len);
0855     if (!skb)
0856         return -ENOMEM;
0857 
0858     memset(&params, 0, sizeof(params));
0859     ath11k_hal_srng_get_params(ab, srng, &params);
0860 
0861     hp_addr = ath11k_hal_srng_get_hp_addr(ab, srng);
0862     tp_addr = ath11k_hal_srng_get_tp_addr(ab, srng);
0863 
0864     ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
0865                         ring_type, &htt_ring_type,
0866                         &htt_ring_id);
0867     if (ret)
0868         goto err_free;
0869 
0870     skb_put(skb, len);
0871     cmd = (struct htt_srng_setup_cmd *)skb->data;
0872     cmd->info0 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE,
0873                 HTT_H2T_MSG_TYPE_SRING_SETUP);
0874     if (htt_ring_type == HTT_SW_TO_HW_RING ||
0875         htt_ring_type == HTT_HW_TO_SW_RING)
0876         cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
0877                      DP_SW2HW_MACID(mac_id));
0878     else
0879         cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID,
0880                      mac_id);
0881     cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE,
0882                  htt_ring_type);
0883     cmd->info0 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO0_RING_ID, htt_ring_id);
0884 
0885     cmd->ring_base_addr_lo = params.ring_base_paddr &
0886                  HAL_ADDR_LSB_REG_MASK;
0887 
0888     cmd->ring_base_addr_hi = (u64)params.ring_base_paddr >>
0889                  HAL_ADDR_MSB_REG_SHIFT;
0890 
0891     ret = ath11k_hal_srng_get_entrysize(ab, ring_type);
0892     if (ret < 0)
0893         goto err_free;
0894 
0895     ring_entry_sz = ret;
0896 
0897     ring_entry_sz >>= 2;
0898     cmd->info1 = FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE,
0899                 ring_entry_sz);
0900     cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE,
0901                  params.num_entries * ring_entry_sz);
0902     cmd->info1 |= FIELD_PREP(HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP,
0903                  !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
0904     cmd->info1 |= FIELD_PREP(
0905             HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP,
0906             !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
0907     cmd->info1 |= FIELD_PREP(
0908             HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP,
0909             !!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP));
0910     if (htt_ring_type == HTT_SW_TO_HW_RING)
0911         cmd->info1 |= HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS;
0912 
0913     cmd->ring_head_off32_remote_addr_lo = hp_addr & HAL_ADDR_LSB_REG_MASK;
0914     cmd->ring_head_off32_remote_addr_hi = (u64)hp_addr >>
0915                           HAL_ADDR_MSB_REG_SHIFT;
0916 
0917     cmd->ring_tail_off32_remote_addr_lo = tp_addr & HAL_ADDR_LSB_REG_MASK;
0918     cmd->ring_tail_off32_remote_addr_hi = (u64)tp_addr >>
0919                           HAL_ADDR_MSB_REG_SHIFT;
0920 
0921     cmd->ring_msi_addr_lo = lower_32_bits(params.msi_addr);
0922     cmd->ring_msi_addr_hi = upper_32_bits(params.msi_addr);
0923     cmd->msi_data = params.msi_data;
0924 
0925     cmd->intr_info = FIELD_PREP(
0926             HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH,
0927             params.intr_batch_cntr_thres_entries * ring_entry_sz);
0928     cmd->intr_info |= FIELD_PREP(
0929             HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH,
0930             params.intr_timer_thres_us >> 3);
0931 
0932     cmd->info2 = 0;
0933     if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
0934         cmd->info2 = FIELD_PREP(
0935                 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH,
0936                 params.low_threshold);
0937     }
0938 
0939     ath11k_dbg(ab, ATH11k_DBG_HAL,
0940            "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
0941            __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
0942            cmd->msi_data);
0943 
0944     ath11k_dbg(ab, ATH11k_DBG_HAL,
0945            "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
0946            ring_id, ring_type, cmd->intr_info, cmd->info2);
0947 
0948     ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
0949     if (ret)
0950         goto err_free;
0951 
0952     return 0;
0953 
0954 err_free:
0955     dev_kfree_skb_any(skb);
0956 
0957     return ret;
0958 }
0959 
0960 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
0961 
0962 int ath11k_dp_tx_htt_h2t_ver_req_msg(struct ath11k_base *ab)
0963 {
0964     struct ath11k_dp *dp = &ab->dp;
0965     struct sk_buff *skb;
0966     struct htt_ver_req_cmd *cmd;
0967     int len = sizeof(*cmd);
0968     int ret;
0969 
0970     init_completion(&dp->htt_tgt_version_received);
0971 
0972     skb = ath11k_htc_alloc_skb(ab, len);
0973     if (!skb)
0974         return -ENOMEM;
0975 
0976     skb_put(skb, len);
0977     cmd = (struct htt_ver_req_cmd *)skb->data;
0978     cmd->ver_reg_info = FIELD_PREP(HTT_VER_REQ_INFO_MSG_ID,
0979                        HTT_H2T_MSG_TYPE_VERSION_REQ);
0980 
0981     ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
0982     if (ret) {
0983         dev_kfree_skb_any(skb);
0984         return ret;
0985     }
0986 
0987     ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
0988                       HTT_TARGET_VERSION_TIMEOUT_HZ);
0989     if (ret == 0) {
0990         ath11k_warn(ab, "htt target version request timed out\n");
0991         return -ETIMEDOUT;
0992     }
0993 
0994     if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
0995         ath11k_err(ab, "unsupported htt major version %d supported version is %d\n",
0996                dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
0997         return -ENOTSUPP;
0998     }
0999 
1000     return 0;
1001 }
1002 
1003 int ath11k_dp_tx_htt_h2t_ppdu_stats_req(struct ath11k *ar, u32 mask)
1004 {
1005     struct ath11k_base *ab = ar->ab;
1006     struct ath11k_dp *dp = &ab->dp;
1007     struct sk_buff *skb;
1008     struct htt_ppdu_stats_cfg_cmd *cmd;
1009     int len = sizeof(*cmd);
1010     u8 pdev_mask;
1011     int ret;
1012     int i;
1013 
1014     for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1015         skb = ath11k_htc_alloc_skb(ab, len);
1016         if (!skb)
1017             return -ENOMEM;
1018 
1019         skb_put(skb, len);
1020         cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
1021         cmd->msg = FIELD_PREP(HTT_PPDU_STATS_CFG_MSG_TYPE,
1022                       HTT_H2T_MSG_TYPE_PPDU_STATS_CFG);
1023 
1024         pdev_mask = 1 << (ar->pdev_idx + i);
1025         cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_PDEV_ID, pdev_mask);
1026         cmd->msg |= FIELD_PREP(HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK, mask);
1027 
1028         ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1029         if (ret) {
1030             dev_kfree_skb_any(skb);
1031             return ret;
1032         }
1033     }
1034 
1035     return 0;
1036 }
1037 
1038 int ath11k_dp_tx_htt_rx_filter_setup(struct ath11k_base *ab, u32 ring_id,
1039                      int mac_id, enum hal_ring_type ring_type,
1040                      int rx_buf_size,
1041                      struct htt_rx_ring_tlv_filter *tlv_filter)
1042 {
1043     struct htt_rx_ring_selection_cfg_cmd *cmd;
1044     struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1045     struct hal_srng_params params;
1046     struct sk_buff *skb;
1047     int len = sizeof(*cmd);
1048     enum htt_srng_ring_type htt_ring_type;
1049     enum htt_srng_ring_id htt_ring_id;
1050     int ret;
1051 
1052     skb = ath11k_htc_alloc_skb(ab, len);
1053     if (!skb)
1054         return -ENOMEM;
1055 
1056     memset(&params, 0, sizeof(params));
1057     ath11k_hal_srng_get_params(ab, srng, &params);
1058 
1059     ret = ath11k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1060                         ring_type, &htt_ring_type,
1061                         &htt_ring_id);
1062     if (ret)
1063         goto err_free;
1064 
1065     skb_put(skb, len);
1066     cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
1067     cmd->info0 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE,
1068                 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG);
1069     if (htt_ring_type == HTT_SW_TO_HW_RING ||
1070         htt_ring_type == HTT_HW_TO_SW_RING)
1071         cmd->info0 |=
1072             FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
1073                    DP_SW2HW_MACID(mac_id));
1074     else
1075         cmd->info0 |=
1076             FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID,
1077                    mac_id);
1078     cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID,
1079                  htt_ring_id);
1080     cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS,
1081                  !!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP));
1082     cmd->info0 |= FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS,
1083                  !!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP));
1084 
1085     cmd->info1 = FIELD_PREP(HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE,
1086                 rx_buf_size);
1087     cmd->pkt_type_en_flags0 = tlv_filter->pkt_filter_flags0;
1088     cmd->pkt_type_en_flags1 = tlv_filter->pkt_filter_flags1;
1089     cmd->pkt_type_en_flags2 = tlv_filter->pkt_filter_flags2;
1090     cmd->pkt_type_en_flags3 = tlv_filter->pkt_filter_flags3;
1091     cmd->rx_filter_tlv = tlv_filter->rx_filter;
1092 
1093     ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
1094     if (ret)
1095         goto err_free;
1096 
1097     return 0;
1098 
1099 err_free:
1100     dev_kfree_skb_any(skb);
1101 
1102     return ret;
1103 }
1104 
1105 int
1106 ath11k_dp_tx_htt_h2t_ext_stats_req(struct ath11k *ar, u8 type,
1107                    struct htt_ext_stats_cfg_params *cfg_params,
1108                    u64 cookie)
1109 {
1110     struct ath11k_base *ab = ar->ab;
1111     struct ath11k_dp *dp = &ab->dp;
1112     struct sk_buff *skb;
1113     struct htt_ext_stats_cfg_cmd *cmd;
1114     u32 pdev_id;
1115     int len = sizeof(*cmd);
1116     int ret;
1117 
1118     skb = ath11k_htc_alloc_skb(ab, len);
1119     if (!skb)
1120         return -ENOMEM;
1121 
1122     skb_put(skb, len);
1123 
1124     cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
1125     memset(cmd, 0, sizeof(*cmd));
1126     cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
1127 
1128     if (ab->hw_params.single_pdev_only)
1129         pdev_id = ath11k_mac_get_target_pdev_id(ar);
1130     else
1131         pdev_id = ar->pdev->pdev_id;
1132 
1133     cmd->hdr.pdev_mask = 1 << pdev_id;
1134 
1135     cmd->hdr.stats_type = type;
1136     cmd->cfg_param0 = cfg_params->cfg0;
1137     cmd->cfg_param1 = cfg_params->cfg1;
1138     cmd->cfg_param2 = cfg_params->cfg2;
1139     cmd->cfg_param3 = cfg_params->cfg3;
1140     cmd->cookie_lsb = lower_32_bits(cookie);
1141     cmd->cookie_msb = upper_32_bits(cookie);
1142 
1143     ret = ath11k_htc_send(&ab->htc, dp->eid, skb);
1144     if (ret) {
1145         ath11k_warn(ab, "failed to send htt type stats request: %d",
1146                 ret);
1147         dev_kfree_skb_any(skb);
1148         return ret;
1149     }
1150 
1151     return 0;
1152 }
1153 
1154 int ath11k_dp_tx_htt_monitor_mode_ring_config(struct ath11k *ar, bool reset)
1155 {
1156     struct ath11k_pdev_dp *dp = &ar->dp;
1157     struct ath11k_base *ab = ar->ab;
1158     struct htt_rx_ring_tlv_filter tlv_filter = {0};
1159     int ret = 0, ring_id = 0, i;
1160 
1161     if (ab->hw_params.full_monitor_mode) {
1162         ret = ath11k_dp_tx_htt_rx_full_mon_setup(ab,
1163                              dp->mac_id, !reset);
1164         if (ret < 0) {
1165             ath11k_err(ab, "failed to setup full monitor %d\n", ret);
1166             return ret;
1167         }
1168     }
1169 
1170     ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
1171 
1172     if (!reset) {
1173         tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
1174         tlv_filter.pkt_filter_flags0 =
1175                     HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
1176                     HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
1177         tlv_filter.pkt_filter_flags1 =
1178                     HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
1179                     HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
1180         tlv_filter.pkt_filter_flags2 =
1181                     HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
1182                     HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
1183         tlv_filter.pkt_filter_flags3 =
1184                     HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
1185                     HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
1186                     HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
1187                     HTT_RX_MON_MO_DATA_FILTER_FLASG3;
1188     }
1189 
1190     if (ab->hw_params.rxdma1_enable) {
1191         ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, dp->mac_id,
1192                                HAL_RXDMA_MONITOR_BUF,
1193                                DP_RXDMA_REFILL_RING_SIZE,
1194                                &tlv_filter);
1195     } else if (!reset) {
1196         /* set in monitor mode only */
1197         for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1198             ring_id = dp->rx_mac_buf_ring[i].ring_id;
1199             ret = ath11k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id,
1200                                    dp->mac_id + i,
1201                                    HAL_RXDMA_BUF,
1202                                    1024,
1203                                    &tlv_filter);
1204         }
1205     }
1206 
1207     if (ret)
1208         return ret;
1209 
1210     for (i = 0; i < ab->hw_params.num_rxmda_per_pdev; i++) {
1211         ring_id = dp->rx_mon_status_refill_ring[i].refill_buf_ring.ring_id;
1212         if (!reset) {
1213             tlv_filter.rx_filter =
1214                     HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING;
1215         } else {
1216             tlv_filter = ath11k_mac_mon_status_filter_default;
1217 
1218             if (ath11k_debugfs_is_extd_rx_stats_enabled(ar))
1219                 tlv_filter.rx_filter = ath11k_debugfs_rx_filter(ar);
1220         }
1221 
1222         ret = ath11k_dp_tx_htt_rx_filter_setup(ab, ring_id,
1223                                dp->mac_id + i,
1224                                HAL_RXDMA_MONITOR_STATUS,
1225                                DP_RXDMA_REFILL_RING_SIZE,
1226                                &tlv_filter);
1227     }
1228 
1229     if (!ar->ab->hw_params.rxdma1_enable)
1230         mod_timer(&ar->ab->mon_reap_timer, jiffies +
1231               msecs_to_jiffies(ATH11K_MON_TIMER_INTERVAL));
1232 
1233     return ret;
1234 }
1235 
1236 int ath11k_dp_tx_htt_rx_full_mon_setup(struct ath11k_base *ab, int mac_id,
1237                        bool config)
1238 {
1239     struct htt_rx_full_monitor_mode_cfg_cmd *cmd;
1240     struct sk_buff *skb;
1241     int ret, len = sizeof(*cmd);
1242 
1243     skb = ath11k_htc_alloc_skb(ab, len);
1244     if (!skb)
1245         return -ENOMEM;
1246 
1247     skb_put(skb, len);
1248     cmd = (struct htt_rx_full_monitor_mode_cfg_cmd *)skb->data;
1249     memset(cmd, 0, sizeof(*cmd));
1250     cmd->info0 = FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE,
1251                 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE);
1252 
1253     cmd->info0 |= FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID, mac_id);
1254 
1255     cmd->cfg = HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE |
1256            FIELD_PREP(HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING,
1257                   HTT_RX_MON_RING_SW);
1258     if (config) {
1259         cmd->cfg |= HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END |
1260                 HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END;
1261     }
1262 
1263     ret = ath11k_htc_send(&ab->htc, ab->dp.eid, skb);
1264     if (ret)
1265         goto err_free;
1266 
1267     return 0;
1268 
1269 err_free:
1270     dev_kfree_skb_any(skb);
1271 
1272     return ret;
1273 }
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