ath/ath11k/ce.h

0001 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
0002 /*
0003  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
0004  */
0005
0006 #ifndef ATH11K_CE_H
0007 #define ATH11K_CE_H
0008
0009 #define CE_COUNT_MAX 12
0010
0011 /* Byte swap data words */
0012 #define CE_ATTR_BYTE_SWAP_DATA 2
0013
0014 /* no interrupt on copy completion */
0015 #define CE_ATTR_DIS_INTR        8
0016
0017 /* Host software's Copy Engine configuration. */
0018 #ifdef __BIG_ENDIAN
0019 #define CE_ATTR_FLAGS CE_ATTR_BYTE_SWAP_DATA
0020 #else
0021 #define CE_ATTR_FLAGS 0
0022 #endif
0023
0024 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
0025 #define ATH11K_CE_USAGE_THRESHOLD 32
0026
0027 void ath11k_ce_byte_swap(void *mem, u32 len);
0028
0029 /*
0030  * Directions for interconnect pipe configuration.
0031  * These definitions may be used during configuration and are shared
0032  * between Host and Target.
0033  *
0034  * Pipe Directions are relative to the Host, so PIPEDIR_IN means
0035  * "coming IN over air through Target to Host" as with a WiFi Rx operation.
0036  * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
0037  * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
0038  * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
0039  * over the interconnect.
0040  */
0041 #define PIPEDIR_NONE        0
0042 #define PIPEDIR_IN      1 /* Target-->Host, WiFi Rx direction */
0043 #define PIPEDIR_OUT     2 /* Host->Target, WiFi Tx direction */
0044 #define PIPEDIR_INOUT       3 /* bidirectional */
0045 #define PIPEDIR_INOUT_H2H   4 /* bidirectional, host to host */
0046
0047 /* CE address/mask */
0048 #define CE_HOST_IE_ADDRESS  0x00A1803C
0049 #define CE_HOST_IE_2_ADDRESS    0x00A18040
0050 #define CE_HOST_IE_3_ADDRESS    CE_HOST_IE_ADDRESS
0051
0052 #define CE_HOST_IE_3_SHIFT  0xC
0053
0054 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
0055
0056 #define ATH11K_CE_RX_POST_RETRY_JIFFIES 50
0057
0058 struct ath11k_base;
0059
0060 /*
0061  * Establish a mapping between a service/direction and a pipe.
0062  * Configuration information for a Copy Engine pipe and services.
0063  * Passed from Host to Target through QMI message and must be in
0064  * little endian format.
0065  */
0066 struct service_to_pipe {
0067     __le32 service_id;
0068     __le32 pipedir;
0069     __le32 pipenum;
0070 };
0071
0072 /*
0073  * Configuration information for a Copy Engine pipe.
0074  * Passed from Host to Target through QMI message during startup (one per CE).
0075  *
0076  * NOTE: Structure is shared between Host software and Target firmware!
0077  */
0078 struct ce_pipe_config {
0079     __le32 pipenum;
0080     __le32 pipedir;
0081     __le32 nentries;
0082     __le32 nbytes_max;
0083     __le32 flags;
0084     __le32 reserved;
0085 };
0086
0087 struct ce_attr {
0088     /* CE_ATTR_* values */
0089     unsigned int flags;
0090
0091     /* #entries in source ring - Must be a power of 2 */
0092     unsigned int src_nentries;
0093
0094     /*
0095      * Max source send size for this CE.
0096      * This is also the minimum size of a destination buffer.
0097      */
0098     unsigned int src_sz_max;
0099
0100     /* #entries in destination ring - Must be a power of 2 */
0101     unsigned int dest_nentries;
0102
0103     void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
0104     void (*send_cb)(struct ath11k_base *, struct sk_buff *);
0105 };
0106
0107 #define CE_DESC_RING_ALIGN 8
0108
0109 struct ath11k_ce_ring {
0110     /* Number of entries in this ring; must be power of 2 */
0111     unsigned int nentries;
0112     unsigned int nentries_mask;
0113
0114     /* For dest ring, this is the next index to be processed
0115      * by software after it was/is received into.
0116      *
0117      * For src ring, this is the last descriptor that was sent
0118      * and completion processed by software.
0119      *
0120      * Regardless of src or dest ring, this is an invariant
0121      * (modulo ring size):
0122      *     write index >= read index >= sw_index
0123      */
0124     unsigned int sw_index;
0125     /* cached copy */
0126     unsigned int write_index;
0127
0128     /* Start of DMA-coherent area reserved for descriptors */
0129     /* Host address space */
0130     void *base_addr_owner_space_unaligned;
0131     /* CE address space */
0132     u32 base_addr_ce_space_unaligned;
0133
0134     /* Actual start of descriptors.
0135      * Aligned to descriptor-size boundary.
0136      * Points into reserved DMA-coherent area, above.
0137      */
0138     /* Host address space */
0139     void *base_addr_owner_space;
0140
0141     /* CE address space */
0142     u32 base_addr_ce_space;
0143
0144     /* HAL ring id */
0145     u32 hal_ring_id;
0146
0147     /* keep last */
0148     struct sk_buff *skb[];
0149 };
0150
0151 struct ath11k_ce_pipe {
0152     struct ath11k_base *ab;
0153     u16 pipe_num;
0154     unsigned int attr_flags;
0155     unsigned int buf_sz;
0156     unsigned int rx_buf_needed;
0157
0158     void (*send_cb)(struct ath11k_base *, struct sk_buff *);
0159     void (*recv_cb)(struct ath11k_base *, struct sk_buff *);
0160
0161     struct tasklet_struct intr_tq;
0162     struct ath11k_ce_ring *src_ring;
0163     struct ath11k_ce_ring *dest_ring;
0164     struct ath11k_ce_ring *status_ring;
0165     u64 timestamp;
0166 };
0167
0168 struct ath11k_ce {
0169     struct ath11k_ce_pipe ce_pipe[CE_COUNT_MAX];
0170     /* Protects rings of all ce pipes */
0171     spinlock_t ce_lock;
0172     struct ath11k_hp_update_timer hp_timer[CE_COUNT_MAX];
0173 };
0174
0175 extern const struct ce_attr ath11k_host_ce_config_ipq8074[];
0176 extern const struct ce_attr ath11k_host_ce_config_qca6390[];
0177 extern const struct ce_attr ath11k_host_ce_config_qcn9074[];
0178
0179 void ath11k_ce_cleanup_pipes(struct ath11k_base *ab);
0180 void ath11k_ce_rx_replenish_retry(struct timer_list *t);
0181 void ath11k_ce_per_engine_service(struct ath11k_base *ab, u16 ce_id);
0182 int ath11k_ce_send(struct ath11k_base *ab, struct sk_buff *skb, u8 pipe_id,
0183            u16 transfer_id);
0184 void ath11k_ce_rx_post_buf(struct ath11k_base *ab);
0185 int ath11k_ce_init_pipes(struct ath11k_base *ab);
0186 int ath11k_ce_alloc_pipes(struct ath11k_base *ab);
0187 void ath11k_ce_free_pipes(struct ath11k_base *ab);
0188 int ath11k_ce_get_attr_flags(struct ath11k_base *ab, int ce_id);
0189 void ath11k_ce_poll_send_completed(struct ath11k_base *ab, u8 pipe_id);
0190 int ath11k_ce_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
0191                   u8 *ul_pipe, u8 *dl_pipe);
0192 int ath11k_ce_attr_attach(struct ath11k_base *ab);
0193 void ath11k_ce_get_shadow_config(struct ath11k_base *ab,
0194                  u32 **shadow_cfg, u32 *shadow_cfg_len);
0195 void ath11k_ce_stop_shadow_timers(struct ath11k_base *ab);
0196
0197 #endif