ath/ath10k/targaddrs.h

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (c) 2005-2011 Atheros Communications Inc.
0004  * Copyright (c) 2011-2016 Qualcomm Atheros, Inc.
0005  */
0006
0007 #ifndef __TARGADDRS_H__
0008 #define __TARGADDRS_H__
0009
0010 #include "hw.h"
0011
0012 /*
0013  * xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
0014  * host_interest structure.  It must match the address of the _host_interest
0015  * symbol (see linker script).
0016  *
0017  * Host Interest is shared between Host and Target in order to coordinate
0018  * between the two, and is intended to remain constant (with additions only
0019  * at the end) across software releases.
0020  *
0021  * All addresses are available here so that it's possible to
0022  * write a single binary that works with all Target Types.
0023  * May be used in assembler code as well as C.
0024  */
0025 #define QCA988X_HOST_INTEREST_ADDRESS    0x00400800
0026 #define HOST_INTEREST_MAX_SIZE          0x200
0027
0028 /*
0029  * These are items that the Host may need to access via BMI or via the
0030  * Diagnostic Window. The position of items in this structure must remain
0031  * constant across firmware revisions! Types for each item must be fixed
0032  * size across target and host platforms. More items may be added at the end.
0033  */
0034 struct host_interest {
0035     /*
0036      * Pointer to application-defined area, if any.
0037      * Set by Target application during startup.
0038      */
0039     u32 hi_app_host_interest;           /* 0x00 */
0040
0041     /* Pointer to register dump area, valid after Target crash. */
0042     u32 hi_failure_state;               /* 0x04 */
0043
0044     /* Pointer to debug logging header */
0045     u32 hi_dbglog_hdr;              /* 0x08 */
0046
0047     u32 hi_unused0c;                /* 0x0c */
0048
0049     /*
0050      * General-purpose flag bits, similar to SOC_OPTION_* flags.
0051      * Can be used by application rather than by OS.
0052      */
0053     u32 hi_option_flag;             /* 0x10 */
0054
0055     /*
0056      * Boolean that determines whether or not to
0057      * display messages on the serial port.
0058      */
0059     u32 hi_serial_enable;               /* 0x14 */
0060
0061     /* Start address of DataSet index, if any */
0062     u32 hi_dset_list_head;              /* 0x18 */
0063
0064     /* Override Target application start address */
0065     u32 hi_app_start;               /* 0x1c */
0066
0067     /* Clock and voltage tuning */
0068     u32 hi_skip_clock_init;             /* 0x20 */
0069     u32 hi_core_clock_setting;          /* 0x24 */
0070     u32 hi_cpu_clock_setting;           /* 0x28 */
0071     u32 hi_system_sleep_setting;            /* 0x2c */
0072     u32 hi_xtal_control_setting;            /* 0x30 */
0073     u32 hi_pll_ctrl_setting_24ghz;          /* 0x34 */
0074     u32 hi_pll_ctrl_setting_5ghz;           /* 0x38 */
0075     u32 hi_ref_voltage_trim_setting;        /* 0x3c */
0076     u32 hi_clock_info;              /* 0x40 */
0077
0078     /* Host uses BE CPU or not */
0079     u32 hi_be;                  /* 0x44 */
0080
0081     u32 hi_stack;   /* normal stack */          /* 0x48 */
0082     u32 hi_err_stack; /* error stack */     /* 0x4c */
0083     u32 hi_desired_cpu_speed_hz;            /* 0x50 */
0084
0085     /* Pointer to Board Data  */
0086     u32 hi_board_data;              /* 0x54 */
0087
0088     /*
0089      * Indication of Board Data state:
0090      *    0: board data is not yet initialized.
0091      *    1: board data is initialized; unknown size
0092      *   >1: number of bytes of initialized board data
0093      */
0094     u32 hi_board_data_initialized;          /* 0x58 */
0095
0096     u32 hi_dset_ram_index_table;            /* 0x5c */
0097
0098     u32 hi_desired_baud_rate;           /* 0x60 */
0099     u32 hi_dbglog_config;               /* 0x64 */
0100     u32 hi_end_ram_reserve_sz;          /* 0x68 */
0101     u32 hi_mbox_io_block_sz;            /* 0x6c */
0102
0103     u32 hi_num_bpatch_streams;          /* 0x70 -- unused */
0104     u32 hi_mbox_isr_yield_limit;            /* 0x74 */
0105
0106     u32 hi_refclk_hz;               /* 0x78 */
0107     u32 hi_ext_clk_detected;            /* 0x7c */
0108     u32 hi_dbg_uart_txpin;              /* 0x80 */
0109     u32 hi_dbg_uart_rxpin;              /* 0x84 */
0110     u32 hi_hci_uart_baud;               /* 0x88 */
0111     u32 hi_hci_uart_pin_assignments;        /* 0x8C */
0112
0113     u32 hi_hci_uart_baud_scale_val;         /* 0x90 */
0114     u32 hi_hci_uart_baud_step_val;          /* 0x94 */
0115
0116     u32 hi_allocram_start;              /* 0x98 */
0117     u32 hi_allocram_sz;             /* 0x9c */
0118     u32 hi_hci_bridge_flags;            /* 0xa0 */
0119     u32 hi_hci_uart_support_pins;           /* 0xa4 */
0120
0121     u32 hi_hci_uart_pwr_mgmt_params;        /* 0xa8 */
0122
0123     /*
0124      * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
0125      *        [31:16]: wakeup timeout in ms
0126      */
0127     /* Pointer to extended board Data  */
0128     u32 hi_board_ext_data;              /* 0xac */
0129     u32 hi_board_ext_data_config;           /* 0xb0 */
0130     /*
0131      * Bit [0]  :   valid
0132      * Bit[31:16:   size
0133      */
0134     /*
0135      * hi_reset_flag is used to do some stuff when target reset.
0136      * such as restore app_start after warm reset or
0137      * preserve host Interest area, or preserve ROM data, literals etc.
0138      */
0139     u32  hi_reset_flag;             /* 0xb4 */
0140     /* indicate hi_reset_flag is valid */
0141     u32  hi_reset_flag_valid;           /* 0xb8 */
0142     u32 hi_hci_uart_pwr_mgmt_params_ext;        /* 0xbc */
0143     /* 0xbc - [31:0]: idle timeout in ms */
0144     /* ACS flags */
0145     u32 hi_acs_flags;               /* 0xc0 */
0146     u32 hi_console_flags;               /* 0xc4 */
0147     u32 hi_nvram_state;             /* 0xc8 */
0148     u32 hi_option_flag2;                /* 0xcc */
0149
0150     /* If non-zero, override values sent to Host in WMI_READY event. */
0151     u32 hi_sw_version_override;         /* 0xd0 */
0152     u32 hi_abi_version_override;            /* 0xd4 */
0153
0154     /*
0155      * Percentage of high priority RX traffic to total expected RX traffic
0156      * applicable only to ar6004
0157      */
0158     u32 hi_hp_rx_traffic_ratio;         /* 0xd8 */
0159
0160     /* test applications flags */
0161     u32 hi_test_apps_related;           /* 0xdc */
0162     /* location of test script */
0163     u32 hi_ota_testscript;              /* 0xe0 */
0164     /* location of CAL data */
0165     u32 hi_cal_data;                /* 0xe4 */
0166
0167     /* Number of packet log buffers */
0168     u32 hi_pktlog_num_buffers;          /* 0xe8 */
0169
0170     /* wow extension configuration */
0171     u32 hi_wow_ext_config;              /* 0xec */
0172     u32 hi_pwr_save_flags;              /* 0xf0 */
0173
0174     /* Spatial Multiplexing Power Save (SMPS) options */
0175     u32 hi_smps_options;                /* 0xf4 */
0176
0177     /* Interconnect-specific state */
0178     u32 hi_interconnect_state;          /* 0xf8 */
0179
0180     /* Coex configuration flags */
0181     u32 hi_coex_config;             /* 0xfc */
0182
0183     /* Early allocation support */
0184     u32 hi_early_alloc;             /* 0x100 */
0185     /* FW swap field */
0186     /*
0187      * Bits of this 32bit word will be used to pass specific swap
0188      * instruction to FW
0189      */
0190     /*
0191      * Bit 0 -- AP Nart descriptor no swap. When this bit is set
0192      * FW will not swap TX descriptor. Meaning packets are formed
0193      * on the target processor.
0194      */
0195     /* Bit 1 - unused */
0196     u32 hi_fw_swap;                 /* 0x104 */
0197
0198     /* global arenas pointer address, used by host driver debug */
0199     u32 hi_dynamic_mem_arenas_addr;         /* 0x108 */
0200
0201     /* allocated bytes of DRAM use by allocated */
0202     u32 hi_dynamic_mem_allocated;           /* 0x10C */
0203
0204     /* remaining bytes of DRAM */
0205     u32 hi_dynamic_mem_remaining;           /* 0x110 */
0206
0207     /* memory track count, configured by host */
0208     u32 hi_dynamic_mem_track_max;           /* 0x114 */
0209
0210     /* minidump buffer */
0211     u32 hi_minidump;                /* 0x118 */
0212
0213     /* bdata's sig and key addr */
0214     u32 hi_bd_sig_key;              /* 0x11c */
0215 } __packed;
0216
0217 #define HI_ITEM(item)  offsetof(struct host_interest, item)
0218
0219 /* Bits defined in hi_option_flag */
0220
0221 /* Enable timer workaround */
0222 #define HI_OPTION_TIMER_WAR         0x01
0223 /* Limit BMI command credits */
0224 #define HI_OPTION_BMI_CRED_LIMIT    0x02
0225 /* Relay Dot11 hdr to/from host */
0226 #define HI_OPTION_RELAY_DOT11_HDR   0x04
0227 /* MAC addr method 0-locally administred 1-globally unique addrs */
0228 #define HI_OPTION_MAC_ADDR_METHOD   0x08
0229 /* Firmware Bridging */
0230 #define HI_OPTION_FW_BRIDGE         0x10
0231 /* Enable CPU profiling */
0232 #define HI_OPTION_ENABLE_PROFILE    0x20
0233 /* Disable debug logging */
0234 #define HI_OPTION_DISABLE_DBGLOG    0x40
0235 /* Skip Era Tracking */
0236 #define HI_OPTION_SKIP_ERA_TRACKING 0x80
0237 /* Disable PAPRD (debug) */
0238 #define HI_OPTION_PAPRD_DISABLE     0x100
0239 #define HI_OPTION_NUM_DEV_LSB       0x200
0240 #define HI_OPTION_NUM_DEV_MSB       0x800
0241 #define HI_OPTION_DEV_MODE_LSB      0x1000
0242 #define HI_OPTION_DEV_MODE_MSB      0x8000000
0243 /* Disable LowFreq Timer Stabilization */
0244 #define HI_OPTION_NO_LFT_STBL       0x10000000
0245 /* Skip regulatory scan */
0246 #define HI_OPTION_SKIP_REG_SCAN     0x20000000
0247 /*
0248  * Do regulatory scan during init before
0249  * sending WMI ready event to host
0250  */
0251 #define HI_OPTION_INIT_REG_SCAN     0x40000000
0252
0253 /* REV6: Do not adjust memory map */
0254 #define HI_OPTION_SKIP_MEMMAP       0x80000000
0255
0256 #define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
0257
0258 /* 2 bits of hi_option_flag are used to represent 3 modes */
0259 #define HI_OPTION_FW_MODE_IBSS    0x0 /* IBSS Mode */
0260 #define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
0261 #define HI_OPTION_FW_MODE_AP      0x2 /* AP Mode */
0262 #define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
0263
0264 /* 2 bits of hi_option flag are usedto represent 4 submodes */
0265 #define HI_OPTION_FW_SUBMODE_NONE    0x0  /* Normal mode */
0266 #define HI_OPTION_FW_SUBMODE_P2PDEV  0x1  /* p2p device mode */
0267 #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
0268 #define HI_OPTION_FW_SUBMODE_P2PGO   0x3 /* p2p go mode */
0269
0270 /* Num dev Mask */
0271 #define HI_OPTION_NUM_DEV_MASK    0x7
0272 #define HI_OPTION_NUM_DEV_SHIFT   0x9
0273
0274 /* firmware bridging */
0275 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04
0276
0277 /*
0278  * Fw Mode/SubMode Mask
0279  *-----------------------------------------------------------------------------
0280  *  SUB   |   SUB   |   SUB   |  SUB    |         |         |         |
0281  *MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0]
0282  *  (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)   |   (2)
0283  *-----------------------------------------------------------------------------
0284  */
0285 #define HI_OPTION_FW_MODE_BITS         0x2
0286 #define HI_OPTION_FW_MODE_MASK         0x3
0287 #define HI_OPTION_FW_MODE_SHIFT        0xC
0288 #define HI_OPTION_ALL_FW_MODE_MASK     0xFF
0289
0290 #define HI_OPTION_FW_SUBMODE_BITS      0x2
0291 #define HI_OPTION_FW_SUBMODE_MASK      0x3
0292 #define HI_OPTION_FW_SUBMODE_SHIFT     0x14
0293 #define HI_OPTION_ALL_FW_SUBMODE_MASK  0xFF00
0294 #define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
0295
0296 /* hi_option_flag2 options */
0297 #define HI_OPTION_OFFLOAD_AMSDU     0x01
0298 #define HI_OPTION_DFS_SUPPORT       0x02 /* Enable DFS support */
0299 #define HI_OPTION_ENABLE_RFKILL     0x04 /* RFKill Enable Feature*/
0300 #define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
0301 #define HI_OPTION_EARLY_CFG_DONE    0x10 /* Early configuration is complete */
0302
0303 #define HI_OPTION_RF_KILL_SHIFT     0x2
0304 #define HI_OPTION_RF_KILL_MASK      0x1
0305
0306 /* hi_reset_flag */
0307 /* preserve App Start address */
0308 #define HI_RESET_FLAG_PRESERVE_APP_START         0x01
0309 /* preserve host interest */
0310 #define HI_RESET_FLAG_PRESERVE_HOST_INTEREST     0x02
0311 /* preserve ROM data */
0312 #define HI_RESET_FLAG_PRESERVE_ROMDATA           0x04
0313 #define HI_RESET_FLAG_PRESERVE_NVRAM_STATE       0x08
0314 #define HI_RESET_FLAG_PRESERVE_BOOT_INFO         0x10
0315 #define HI_RESET_FLAG_WARM_RESET    0x20
0316
0317 /* define hi_fw_swap bits */
0318 #define HI_DESC_IN_FW_BIT   0x01
0319
0320 /* indicate the reset flag is valid */
0321 #define HI_RESET_FLAG_IS_VALID  0x12345678
0322
0323 /* ACS is enabled */
0324 #define HI_ACS_FLAGS_ENABLED        (1 << 0)
0325 /* Use physical WWAN device */
0326 #define HI_ACS_FLAGS_USE_WWAN       (1 << 1)
0327 /* Use test VAP */
0328 #define HI_ACS_FLAGS_TEST_VAP       (1 << 2)
0329 /* SDIO/mailbox ACS flag definitions */
0330 #define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_SET       (1 << 0)
0331 #define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_SET    (1 << 1)
0332 #define HI_ACS_FLAGS_ALT_DATA_CREDIT_SIZE        (1 << 2)
0333 #define HI_ACS_FLAGS_SDIO_SWAP_MAILBOX_FW_ACK    (1 << 16)
0334 #define HI_ACS_FLAGS_SDIO_REDUCE_TX_COMPL_FW_ACK (1 << 17)
0335
0336 /*
0337  * If both SDIO_CRASH_DUMP_ENHANCEMENT_HOST and SDIO_CRASH_DUMP_ENHANCEMENT_FW
0338  * flags are set, then crashdump upload will be done using the BMI host/target
0339  * communication channel.
0340  */
0341 /* HOST to support using BMI dump FW memory when hit assert */
0342 #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_HOST 0x400
0343
0344 /* FW to support using BMI dump FW memory when hit assert */
0345 #define HI_OPTION_SDIO_CRASH_DUMP_ENHANCEMENT_FW   0x800
0346
0347 /*
0348  * CONSOLE FLAGS
0349  *
0350  * Bit Range  Meaning
0351  * ---------  --------------------------------
0352  *   2..0     UART ID (0 = Default)
0353  *    3       Baud Select (0 = 9600, 1 = 115200)
0354  *   30..4    Reserved
0355  *    31      Enable Console
0356  *
0357  */
0358
0359 #define HI_CONSOLE_FLAGS_ENABLE       (1 << 31)
0360 #define HI_CONSOLE_FLAGS_UART_MASK    (0x7)
0361 #define HI_CONSOLE_FLAGS_UART_SHIFT   0
0362 #define HI_CONSOLE_FLAGS_BAUD_SELECT  (1 << 3)
0363
0364 /* SM power save options */
0365 #define HI_SMPS_ALLOW_MASK            (0x00000001)
0366 #define HI_SMPS_MODE_MASK             (0x00000002)
0367 #define HI_SMPS_MODE_STATIC           (0x00000000)
0368 #define HI_SMPS_MODE_DYNAMIC          (0x00000002)
0369 #define HI_SMPS_DISABLE_AUTO_MODE     (0x00000004)
0370 #define HI_SMPS_DATA_THRESH_MASK      (0x000007f8)
0371 #define HI_SMPS_DATA_THRESH_SHIFT     (3)
0372 #define HI_SMPS_RSSI_THRESH_MASK      (0x0007f800)
0373 #define HI_SMPS_RSSI_THRESH_SHIFT     (11)
0374 #define HI_SMPS_LOWPWR_CM_MASK        (0x00380000)
0375 #define HI_SMPS_LOWPWR_CM_SHIFT       (15)
0376 #define HI_SMPS_HIPWR_CM_MASK         (0x03c00000)
0377 #define HI_SMPS_HIPWR_CM_SHIFT        (19)
0378
0379 /*
0380  * WOW Extension configuration
0381  *
0382  * Bit Range  Meaning
0383  * ---------  --------------------------------
0384  *   8..0     Size of each WOW pattern (max 511)
0385  *   15..9    Number of patterns per list (max 127)
0386  *   17..16   Number of lists (max 4)
0387  *   30..18   Reserved
0388  *   31       Enabled
0389  *
0390  *  set values (except enable) to zeros for default settings
0391  */
0392
0393 #define HI_WOW_EXT_ENABLED_MASK        (1 << 31)
0394 #define HI_WOW_EXT_NUM_LIST_SHIFT      16
0395 #define HI_WOW_EXT_NUM_LIST_MASK       (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT)
0396 #define HI_WOW_EXT_NUM_PATTERNS_SHIFT  9
0397 #define HI_WOW_EXT_NUM_PATTERNS_MASK   (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT)
0398 #define HI_WOW_EXT_PATTERN_SIZE_SHIFT  0
0399 #define HI_WOW_EXT_PATTERN_SIZE_MASK   (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
0400
0401 #define HI_WOW_EXT_MAKE_CONFIG(num_lists, count, size) \
0402     ((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & \
0403         HI_WOW_EXT_NUM_LIST_MASK) | \
0404     (((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & \
0405         HI_WOW_EXT_NUM_PATTERNS_MASK) | \
0406     (((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & \
0407         HI_WOW_EXT_PATTERN_SIZE_MASK))
0408
0409 #define HI_WOW_EXT_GET_NUM_LISTS(config) \
0410     (((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
0411 #define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
0412     (((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> \
0413         HI_WOW_EXT_NUM_PATTERNS_SHIFT)
0414 #define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
0415     (((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> \
0416         HI_WOW_EXT_PATTERN_SIZE_SHIFT)
0417
0418 /*
0419  * Early allocation configuration
0420  * Support RAM bank configuration before BMI done and this eases the memory
0421  * allocation at very early stage
0422  * Bit Range  Meaning
0423  * ---------  ----------------------------------
0424  * [0:3]      number of bank assigned to be IRAM
0425  * [4:15]     reserved
0426  * [16:31]    magic number
0427  *
0428  * Note:
0429  * 1. target firmware would check magic number and if it's a match, firmware
0430  *    would consider the bits[0:15] are valid and base on that to calculate
0431  *    the end of DRAM. Early allocation would be located at that area and
0432  *    may be reclaimed when necessary
0433  * 2. if no magic number is found, early allocation would happen at "_end"
0434  *    symbol of ROM which is located before the app-data and might NOT be
0435  *    re-claimable. If this is adopted, link script should keep this in
0436  *    mind to avoid data corruption.
0437  */
0438 #define HI_EARLY_ALLOC_MAGIC        0x6d8a
0439 #define HI_EARLY_ALLOC_MAGIC_MASK   0xffff0000
0440 #define HI_EARLY_ALLOC_MAGIC_SHIFT  16
0441 #define HI_EARLY_ALLOC_IRAM_BANKS_MASK  0x0000000f
0442 #define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
0443
0444 #define HI_EARLY_ALLOC_VALID() \
0445     ((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> \
0446     HI_EARLY_ALLOC_MAGIC_SHIFT) == (HI_EARLY_ALLOC_MAGIC))
0447 #define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
0448     (((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) \
0449     >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
0450
0451 /*power save flag bit definitions*/
0452 #define HI_PWR_SAVE_LPL_ENABLED   0x1
0453 /*b1-b3 reserved*/
0454 /*b4-b5 : dev0 LPL type : 0 - none
0455  *            1- Reduce Pwr Search
0456  *            2- Reduce Pwr Listen
0457  */
0458 /*b6-b7 : dev1 LPL type and so on for Max 8 devices*/
0459 #define HI_PWR_SAVE_LPL_DEV0_LSB   4
0460 #define HI_PWR_SAVE_LPL_DEV_MASK   0x3
0461 /*power save related utility macros*/
0462 #define HI_LPL_ENABLED() \
0463     ((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
0464 #define HI_DEV_LPL_TYPE_GET(_devix) \
0465     (HOST_INTEREST->hi_pwr_save_flags & ((HI_PWR_SAVE_LPL_DEV_MASK) << \
0466      (HI_PWR_SAVE_LPL_DEV0_LSB + (_devix) * 2)))
0467
0468 #define HOST_INTEREST_SMPS_IS_ALLOWED() \
0469     ((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
0470
0471 /* Reserve 1024 bytes for extended board data */
0472 #define QCA988X_BOARD_DATA_SZ     7168
0473 #define QCA988X_BOARD_EXT_DATA_SZ 0
0474
0475 #define QCA9887_BOARD_DATA_SZ     7168
0476 #define QCA9887_BOARD_EXT_DATA_SZ 0
0477
0478 #define QCA6174_BOARD_DATA_SZ     8192
0479 #define QCA6174_BOARD_EXT_DATA_SZ 0
0480
0481 #define QCA9377_BOARD_DATA_SZ     QCA6174_BOARD_DATA_SZ
0482 #define QCA9377_BOARD_EXT_DATA_SZ 0
0483
0484 #define QCA99X0_BOARD_DATA_SZ     12288
0485 #define QCA99X0_BOARD_EXT_DATA_SZ 0
0486
0487 /* Dual band extended board data */
0488 #define QCA99X0_EXT_BOARD_DATA_SZ 2048
0489 #define EXT_BOARD_ADDRESS_OFFSET 0x3000
0490
0491 #define QCA4019_BOARD_DATA_SZ     12064
0492 #define QCA4019_BOARD_EXT_DATA_SZ 0
0493
0494 #endif /* __TARGADDRS_H__ */