ath/ath10k/swap.h

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (c) 2015-2016 Qualcomm Atheros, Inc.
0004  */
0005
0006 #ifndef _SWAP_H_
0007 #define _SWAP_H_
0008
0009 #define ATH10K_SWAP_CODE_SEG_BIN_LEN_MAX    (512 * 1024)
0010 #define ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ 12
0011 #define ATH10K_SWAP_CODE_SEG_NUM_MAX        16
0012 /* Currently only one swap segment is supported */
0013 #define ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED  1
0014
0015 struct ath10k_fw_file;
0016
0017 struct ath10k_swap_code_seg_tlv {
0018     __le32 address;
0019     __le32 length;
0020     u8 data[];
0021 } __packed;
0022
0023 struct ath10k_swap_code_seg_tail {
0024     u8 magic_signature[ATH10K_SWAP_CODE_SEG_MAGIC_BYTES_SZ];
0025     __le32 bmi_write_addr;
0026 } __packed;
0027
0028 union ath10k_swap_code_seg_item {
0029     struct ath10k_swap_code_seg_tlv tlv;
0030     struct ath10k_swap_code_seg_tail tail;
0031 } __packed;
0032
0033 struct ath10k_swap_code_seg_hw_info {
0034     /* Swap binary image size */
0035     __le32 swap_size;
0036     __le32 num_segs;
0037
0038     /* Swap data size */
0039     __le32 size;
0040     __le32 size_log2;
0041     __le32 bus_addr[ATH10K_SWAP_CODE_SEG_NUM_MAX];
0042     __le64 reserved[ATH10K_SWAP_CODE_SEG_NUM_MAX];
0043 } __packed;
0044
0045 struct ath10k_swap_code_seg_info {
0046     struct ath10k_swap_code_seg_hw_info seg_hw_info;
0047     void *virt_address[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
0048     u32 target_addr;
0049     dma_addr_t paddr[ATH10K_SWAP_CODE_SEG_NUM_SUPPORTED];
0050 };
0051
0052 int ath10k_swap_code_seg_configure(struct ath10k *ar,
0053                    const struct ath10k_fw_file *fw_file);
0054 void ath10k_swap_code_seg_release(struct ath10k *ar,
0055                   struct ath10k_fw_file *fw_file);
0056 int ath10k_swap_code_seg_init(struct ath10k *ar,
0057                   struct ath10k_fw_file *fw_file);
0058
0059 #endif