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0008 #ifndef _SDIO_H_
0009 #define _SDIO_H_
0010
0011 #define ATH10K_HIF_MBOX_BLOCK_SIZE 256
0012
0013 #define ATH10K_SDIO_MAX_BUFFER_SIZE 4096
0014
0015
0016 #define ATH10K_HIF_MBOX_BASE_ADDR 0x1000
0017 #define ATH10K_HIF_MBOX_WIDTH 0x800
0018
0019 #define ATH10K_HIF_MBOX_TOT_WIDTH \
0020 (ATH10K_HIF_MBOX_NUM_MAX * ATH10K_HIF_MBOX_WIDTH)
0021
0022 #define ATH10K_HIF_MBOX0_EXT_BASE_ADDR 0x5000
0023 #define ATH10K_HIF_MBOX0_EXT_WIDTH (36 * 1024)
0024 #define ATH10K_HIF_MBOX0_EXT_WIDTH_ROME_2_0 (56 * 1024)
0025 #define ATH10K_HIF_MBOX1_EXT_WIDTH (36 * 1024)
0026 #define ATH10K_HIF_MBOX_DUMMY_SPACE_SIZE (2 * 1024)
0027
0028 #define ATH10K_HTC_MBOX_MAX_PAYLOAD_LENGTH \
0029 (ATH10K_SDIO_MAX_BUFFER_SIZE - sizeof(struct ath10k_htc_hdr))
0030
0031 #define ATH10K_HIF_MBOX_NUM_MAX 4
0032 #define ATH10K_SDIO_BUS_REQUEST_MAX_NUM 1024
0033
0034 #define ATH10K_SDIO_HIF_COMMUNICATION_TIMEOUT_HZ (100 * HZ)
0035
0036
0037 #define ATH10K_HTC_MAILBOX 0
0038 #define ATH10K_HTC_MAILBOX_MASK BIT(ATH10K_HTC_MAILBOX)
0039
0040
0041 #define ATH10K_HIF_GMBOX_BASE_ADDR 0x7000
0042 #define ATH10K_HIF_GMBOX_WIDTH 0x4000
0043
0044
0045
0046
0047
0048 #define ATH10K_SDIO_DRIVE_DTSX_MASK \
0049 (SDIO_DRIVE_DTSx_MASK << SDIO_DRIVE_DTSx_SHIFT)
0050
0051 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_B 0
0052 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_A 1
0053 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_C 2
0054 #define ATH10K_SDIO_DRIVE_DTSX_TYPE_D 3
0055
0056
0057 #define CCCR_SDIO_IRQ_MODE_REG 0xF0
0058 #define CCCR_SDIO_IRQ_MODE_REG_SDIO3 0x16
0059
0060 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_ADDR 0xF2
0061
0062 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_A 0x02
0063 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_C 0x04
0064 #define CCCR_SDIO_DRIVER_STRENGTH_ENABLE_D 0x08
0065
0066 #define CCCR_SDIO_ASYNC_INT_DELAY_ADDRESS 0xF0
0067 #define CCCR_SDIO_ASYNC_INT_DELAY_MASK 0xC0
0068
0069
0070 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ BIT(0)
0071 #define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ_SDIO3 BIT(1)
0072
0073 #define ATH10K_SDIO_TARGET_DEBUG_INTR_MASK 0x01
0074
0075
0076
0077
0078
0079
0080
0081
0082
0083
0084
0085
0086 #define ATH10K_SDIO_MAX_RX_MSGS \
0087 (HTC_HOST_MAX_MSG_PER_RX_BUNDLE * 2)
0088
0089 #define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL 0x00000868u
0090 #define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_OFF 0xFFFEFFFF
0091 #define ATH10K_FIFO_TIMEOUT_AND_CHIP_CONTROL_DISABLE_SLEEP_ON 0x10000
0092
0093 enum sdio_mbox_state {
0094 SDIO_MBOX_UNKNOWN_STATE = 0,
0095 SDIO_MBOX_REQUEST_TO_SLEEP_STATE = 1,
0096 SDIO_MBOX_SLEEP_STATE = 2,
0097 SDIO_MBOX_AWAKE_STATE = 3,
0098 };
0099
0100 #define ATH10K_CIS_READ_WAIT_4_RTC_CYCLE_IN_US 125
0101 #define ATH10K_CIS_RTC_STATE_ADDR 0x1138
0102 #define ATH10K_CIS_RTC_STATE_ON 0x01
0103 #define ATH10K_CIS_XTAL_SETTLE_DURATION_IN_US 1500
0104 #define ATH10K_CIS_READ_RETRY 10
0105 #define ATH10K_MIN_SLEEP_INACTIVITY_TIME_MS 50
0106
0107
0108 struct ath10k_sdio_bus_request {
0109 struct list_head list;
0110
0111
0112 u32 address;
0113
0114 struct sk_buff *skb;
0115 enum ath10k_htc_ep_id eid;
0116 int status;
0117
0118
0119
0120
0121 bool htc_msg;
0122
0123
0124
0125 struct completion *comp;
0126 };
0127
0128 struct ath10k_sdio_rx_data {
0129 struct sk_buff *skb;
0130 size_t alloc_len;
0131 size_t act_len;
0132 enum ath10k_htc_ep_id eid;
0133 bool part_of_bundle;
0134 bool last_in_bundle;
0135 bool trailer_only;
0136 };
0137
0138 struct ath10k_sdio_irq_proc_regs {
0139 u8 host_int_status;
0140 u8 cpu_int_status;
0141 u8 error_int_status;
0142 u8 counter_int_status;
0143 u8 mbox_frame;
0144 u8 rx_lookahead_valid;
0145 u8 host_int_status2;
0146 u8 gmbox_rx_avail;
0147 __le32 rx_lookahead[2 * ATH10K_HIF_MBOX_NUM_MAX];
0148 __le32 int_status_enable;
0149 };
0150
0151 struct ath10k_sdio_irq_enable_regs {
0152 u8 int_status_en;
0153 u8 cpu_int_status_en;
0154 u8 err_int_status_en;
0155 u8 cntr_int_status_en;
0156 };
0157
0158 struct ath10k_sdio_irq_data {
0159
0160
0161
0162
0163
0164
0165 struct mutex mtx;
0166 struct ath10k_sdio_irq_proc_regs *irq_proc_reg;
0167 struct ath10k_sdio_irq_enable_regs *irq_en_reg;
0168 };
0169
0170 struct ath10k_mbox_ext_info {
0171 u32 htc_ext_addr;
0172 u32 htc_ext_sz;
0173 };
0174
0175 struct ath10k_mbox_info {
0176 u32 htc_addr;
0177 struct ath10k_mbox_ext_info ext_info[2];
0178 u32 block_size;
0179 u32 block_mask;
0180 u32 gmbox_addr;
0181 u32 gmbox_sz;
0182 };
0183
0184 struct ath10k_sdio {
0185 struct sdio_func *func;
0186
0187 struct ath10k_mbox_info mbox_info;
0188 bool swap_mbox;
0189 u32 mbox_addr[ATH10K_HTC_EP_COUNT];
0190 u32 mbox_size[ATH10K_HTC_EP_COUNT];
0191
0192
0193 struct ath10k_sdio_bus_request bus_req[ATH10K_SDIO_BUS_REQUEST_MAX_NUM];
0194
0195 struct list_head bus_req_freeq;
0196
0197 struct sk_buff_head rx_head;
0198
0199
0200 spinlock_t lock;
0201
0202 struct ath10k_sdio_rx_data rx_pkts[ATH10K_SDIO_MAX_RX_MSGS];
0203 size_t n_rx_pkts;
0204
0205 struct ath10k *ar;
0206 struct ath10k_sdio_irq_data irq_data;
0207
0208
0209
0210
0211
0212
0213 u8 *vsg_buffer;
0214
0215
0216 u8 *bmi_buf;
0217
0218 bool is_disabled;
0219
0220 struct workqueue_struct *workqueue;
0221 struct work_struct wr_async_work;
0222 struct list_head wr_asyncq;
0223
0224 spinlock_t wr_async_lock;
0225
0226 struct work_struct async_work_rx;
0227 struct timer_list sleep_timer;
0228 enum sdio_mbox_state mbox_state;
0229 };
0230
0231 static inline struct ath10k_sdio *ath10k_sdio_priv(struct ath10k *ar)
0232 {
0233 return (struct ath10k_sdio *)ar->drv_priv;
0234 }
0235
0236 #endif