ath/ath10k/pci.h

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (c) 2005-2011 Atheros Communications Inc.
0004  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
0005  */
0006
0007 #ifndef _PCI_H_
0008 #define _PCI_H_
0009
0010 #include <linux/interrupt.h>
0011 #include <linux/mutex.h>
0012
0013 #include "hw.h"
0014 #include "ce.h"
0015 #include "ahb.h"
0016
0017 /*
0018  * maximum number of bytes that can be
0019  * handled atomically by DiagRead/DiagWrite
0020  */
0021 #define DIAG_TRANSFER_LIMIT 2048
0022
0023 struct bmi_xfer {
0024     bool tx_done;
0025     bool rx_done;
0026     bool wait_for_resp;
0027     u32 resp_len;
0028 };
0029
0030 /*
0031  * PCI-specific Target state
0032  *
0033  * NOTE: Structure is shared between Host software and Target firmware!
0034  *
0035  * Much of this may be of interest to the Host so
0036  * HOST_INTEREST->hi_interconnect_state points here
0037  * (and all members are 32-bit quantities in order to
0038  * facilitate Host access). In particular, Host software is
0039  * required to initialize pipe_cfg_addr and svc_to_pipe_map.
0040  */
0041 struct pcie_state {
0042     /* Pipe configuration Target address */
0043     /* NB: ce_pipe_config[CE_COUNT] */
0044     u32 pipe_cfg_addr;
0045
0046     /* Service to pipe map Target address */
0047     /* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
0048     u32 svc_to_pipe_map;
0049
0050     /* number of MSI interrupts requested */
0051     u32 msi_requested;
0052
0053     /* number of MSI interrupts granted */
0054     u32 msi_granted;
0055
0056     /* Message Signalled Interrupt address */
0057     u32 msi_addr;
0058
0059     /* Base data */
0060     u32 msi_data;
0061
0062     /*
0063      * Data for firmware interrupt;
0064      * MSI data for other interrupts are
0065      * in various SoC registers
0066      */
0067     u32 msi_fw_intr_data;
0068
0069     /* PCIE_PWR_METHOD_* */
0070     u32 power_mgmt_method;
0071
0072     /* PCIE_CONFIG_FLAG_* */
0073     u32 config_flags;
0074 };
0075
0076 /* PCIE_CONFIG_FLAG definitions */
0077 #define PCIE_CONFIG_FLAG_ENABLE_L1  0x0000001
0078
0079 /* Per-pipe state. */
0080 struct ath10k_pci_pipe {
0081     /* Handle of underlying Copy Engine */
0082     struct ath10k_ce_pipe *ce_hdl;
0083
0084     /* Our pipe number; facilitiates use of pipe_info ptrs. */
0085     u8 pipe_num;
0086
0087     /* Convenience back pointer to hif_ce_state. */
0088     struct ath10k *hif_ce_state;
0089
0090     size_t buf_sz;
0091
0092     /* protects compl_free and num_send_allowed */
0093     spinlock_t pipe_lock;
0094 };
0095
0096 struct ath10k_pci_supp_chip {
0097     u32 dev_id;
0098     u32 rev_id;
0099 };
0100
0101 enum ath10k_pci_irq_mode {
0102     ATH10K_PCI_IRQ_AUTO = 0,
0103     ATH10K_PCI_IRQ_LEGACY = 1,
0104     ATH10K_PCI_IRQ_MSI = 2,
0105 };
0106
0107 struct ath10k_pci {
0108     struct pci_dev *pdev;
0109     struct device *dev;
0110     struct ath10k *ar;
0111     void __iomem *mem;
0112     size_t mem_len;
0113
0114     /* Operating interrupt mode */
0115     enum ath10k_pci_irq_mode oper_irq_mode;
0116
0117     struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
0118
0119     /* Copy Engine used for Diagnostic Accesses */
0120     struct ath10k_ce_pipe *ce_diag;
0121     /* For protecting ce_diag */
0122     struct mutex ce_diag_mutex;
0123
0124     struct work_struct dump_work;
0125
0126     struct ath10k_ce ce;
0127     struct timer_list rx_post_retry;
0128
0129     /* Due to HW quirks it is recommended to disable ASPM during device
0130      * bootup. To do that the original PCI-E Link Control is stored before
0131      * device bootup is executed and re-programmed later.
0132      */
0133     u16 link_ctl;
0134
0135     /* Protects ps_awake and ps_wake_refcount */
0136     spinlock_t ps_lock;
0137
0138     /* The device has a special powersave-oriented register. When device is
0139      * considered asleep it drains less power and driver is forbidden from
0140      * accessing most MMIO registers. If host were to access them without
0141      * waking up the device might scribble over host memory or return
0142      * 0xdeadbeef readouts.
0143      */
0144     unsigned long ps_wake_refcount;
0145
0146     /* Waking up takes some time (up to 2ms in some cases) so it can be bad
0147      * for latency. To mitigate this the device isn't immediately allowed
0148      * to sleep after all references are undone - instead there's a grace
0149      * period after which the powersave register is updated unless some
0150      * activity to/from device happened in the meantime.
0151      *
0152      * Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
0153      */
0154     struct timer_list ps_timer;
0155
0156     /* MMIO registers are used to communicate with the device. With
0157      * intensive traffic accessing powersave register would be a bit
0158      * wasteful overhead and would needlessly stall CPU. It is far more
0159      * efficient to rely on a variable in RAM and update it only upon
0160      * powersave register state changes.
0161      */
0162     bool ps_awake;
0163
0164     /* pci power save, disable for QCA988X and QCA99X0.
0165      * Writing 'false' to this variable avoids frequent locking
0166      * on MMIO read/write.
0167      */
0168     bool pci_ps;
0169
0170     /* Chip specific pci reset routine used to do a safe reset */
0171     int (*pci_soft_reset)(struct ath10k *ar);
0172
0173     /* Chip specific pci full reset function */
0174     int (*pci_hard_reset)(struct ath10k *ar);
0175
0176     /* chip specific methods for converting target CPU virtual address
0177      * space to CE address space
0178      */
0179     u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
0180
0181     struct ce_attr *attr;
0182     struct ce_pipe_config *pipe_config;
0183     struct ce_service_to_pipe *serv_to_pipe;
0184
0185     /* Keep this entry in the last, memory for struct ath10k_ahb is
0186      * allocated (ahb support enabled case) in the continuation of
0187      * this struct.
0188      */
0189     struct ath10k_ahb ahb[];
0190
0191 };
0192
0193 static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
0194 {
0195     return (struct ath10k_pci *)ar->drv_priv;
0196 }
0197
0198 #define ATH10K_PCI_RX_POST_RETRY_MS 50
0199 #define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
0200 #define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
0201 #define PCIE_WAKE_LATE_US 10000 /* 10ms */
0202
0203 #define BAR_NUM 0
0204
0205 #define CDC_WAR_MAGIC_STR   0xceef0000
0206 #define CDC_WAR_DATA_CE     4
0207
0208 /* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
0209 #define DIAG_ACCESS_CE_TIMEOUT_US 10000 /* 10 ms */
0210 #define DIAG_ACCESS_CE_WAIT_US  50
0211
0212 void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
0213 void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
0214 void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
0215
0216 u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
0217 u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
0218 u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
0219
0220 int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
0221              struct ath10k_hif_sg_item *items, int n_items);
0222 int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
0223                  size_t buf_len);
0224 int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
0225                   const void *data, int nbytes);
0226 int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
0227                     void *resp, u32 *resp_len);
0228 int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
0229                        u8 *ul_pipe, u8 *dl_pipe);
0230 void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
0231                      u8 *dl_pipe);
0232 void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
0233                     int force);
0234 u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
0235 void ath10k_pci_hif_power_down(struct ath10k *ar);
0236 int ath10k_pci_alloc_pipes(struct ath10k *ar);
0237 void ath10k_pci_free_pipes(struct ath10k *ar);
0238 void ath10k_pci_rx_replenish_retry(struct timer_list *t);
0239 void ath10k_pci_ce_deinit(struct ath10k *ar);
0240 void ath10k_pci_init_napi(struct ath10k *ar);
0241 int ath10k_pci_init_pipes(struct ath10k *ar);
0242 int ath10k_pci_init_config(struct ath10k *ar);
0243 void ath10k_pci_rx_post(struct ath10k *ar);
0244 void ath10k_pci_flush(struct ath10k *ar);
0245 void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
0246 bool ath10k_pci_irq_pending(struct ath10k *ar);
0247 void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
0248 void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
0249 int ath10k_pci_wait_for_target_init(struct ath10k *ar);
0250 int ath10k_pci_setup_resource(struct ath10k *ar);
0251 void ath10k_pci_release_resource(struct ath10k *ar);
0252
0253 /* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
0254  * frequently. To avoid this put SoC to sleep after a very conservative grace
0255  * period. Adjust with great care.
0256  */
0257 #define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
0258
0259 #endif /* _PCI_H_ */