ath/ath10k/htt.c

0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (c) 2005-2011 Atheros Communications Inc.
0004  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
0005  */
0006
0007 #include <linux/slab.h>
0008 #include <linux/if_ether.h>
0009
0010 #include "htt.h"
0011 #include "core.h"
0012 #include "debug.h"
0013 #include "hif.h"
0014
0015 static const enum htt_t2h_msg_type htt_main_t2h_msg_types[] = {
0016     [HTT_MAIN_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
0017     [HTT_MAIN_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
0018     [HTT_MAIN_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
0019     [HTT_MAIN_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
0020     [HTT_MAIN_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
0021     [HTT_MAIN_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
0022     [HTT_MAIN_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
0023     [HTT_MAIN_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
0024     [HTT_MAIN_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
0025     [HTT_MAIN_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
0026     [HTT_MAIN_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
0027     [HTT_MAIN_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
0028     [HTT_MAIN_T2H_MSG_TYPE_TX_INSPECT_IND] =
0029         HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
0030     [HTT_MAIN_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
0031         HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
0032     [HTT_MAIN_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
0033         HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
0034     [HTT_MAIN_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
0035     [HTT_MAIN_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
0036         HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
0037     [HTT_MAIN_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
0038 };
0039
0040 static const enum htt_t2h_msg_type htt_10x_t2h_msg_types[] = {
0041     [HTT_10X_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
0042     [HTT_10X_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
0043     [HTT_10X_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
0044     [HTT_10X_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
0045     [HTT_10X_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
0046     [HTT_10X_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
0047     [HTT_10X_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
0048     [HTT_10X_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
0049     [HTT_10X_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
0050     [HTT_10X_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
0051     [HTT_10X_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
0052     [HTT_10X_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
0053     [HTT_10X_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
0054     [HTT_10X_T2H_MSG_TYPE_TX_INSPECT_IND] = HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
0055     [HTT_10X_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
0056     [HTT_10X_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
0057     [HTT_10X_T2H_MSG_TYPE_AGGR_CONF] = HTT_T2H_MSG_TYPE_AGGR_CONF,
0058     [HTT_10X_T2H_MSG_TYPE_STATS_NOUPLOAD] = HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
0059     [HTT_10X_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
0060         HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
0061 };
0062
0063 static const enum htt_t2h_msg_type htt_tlv_t2h_msg_types[] = {
0064     [HTT_TLV_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
0065     [HTT_TLV_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
0066     [HTT_TLV_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
0067     [HTT_TLV_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
0068     [HTT_TLV_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
0069     [HTT_TLV_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
0070     [HTT_TLV_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
0071     [HTT_TLV_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
0072     [HTT_TLV_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
0073     [HTT_TLV_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
0074     [HTT_TLV_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
0075     [HTT_TLV_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
0076     [HTT_TLV_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
0077     [HTT_TLV_T2H_MSG_TYPE_TX_INSPECT_IND] = HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
0078     [HTT_TLV_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
0079         HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
0080     [HTT_TLV_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
0081         HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
0082     [HTT_TLV_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
0083     [HTT_TLV_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
0084         HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
0085     [HTT_TLV_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND] =
0086         HTT_T2H_MSG_TYPE_RX_IN_ORD_PADDR_IND,
0087     [HTT_TLV_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE] =
0088         HTT_T2H_MSG_TYPE_WDI_IPA_OP_RESPONSE,
0089     [HTT_TLV_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
0090     [HTT_TLV_T2H_MSG_TYPE_RX_OFLD_PKT_ERR] =
0091         HTT_T2H_MSG_TYPE_RX_OFLD_PKT_ERR,
0092     [HTT_TLV_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
0093 };
0094
0095 static const enum htt_t2h_msg_type htt_10_4_t2h_msg_types[] = {
0096     [HTT_10_4_T2H_MSG_TYPE_VERSION_CONF] = HTT_T2H_MSG_TYPE_VERSION_CONF,
0097     [HTT_10_4_T2H_MSG_TYPE_RX_IND] = HTT_T2H_MSG_TYPE_RX_IND,
0098     [HTT_10_4_T2H_MSG_TYPE_RX_FLUSH] = HTT_T2H_MSG_TYPE_RX_FLUSH,
0099     [HTT_10_4_T2H_MSG_TYPE_PEER_MAP] = HTT_T2H_MSG_TYPE_PEER_MAP,
0100     [HTT_10_4_T2H_MSG_TYPE_PEER_UNMAP] = HTT_T2H_MSG_TYPE_PEER_UNMAP,
0101     [HTT_10_4_T2H_MSG_TYPE_RX_ADDBA] = HTT_T2H_MSG_TYPE_RX_ADDBA,
0102     [HTT_10_4_T2H_MSG_TYPE_RX_DELBA] = HTT_T2H_MSG_TYPE_RX_DELBA,
0103     [HTT_10_4_T2H_MSG_TYPE_TX_COMPL_IND] = HTT_T2H_MSG_TYPE_TX_COMPL_IND,
0104     [HTT_10_4_T2H_MSG_TYPE_PKTLOG] = HTT_T2H_MSG_TYPE_PKTLOG,
0105     [HTT_10_4_T2H_MSG_TYPE_STATS_CONF] = HTT_T2H_MSG_TYPE_STATS_CONF,
0106     [HTT_10_4_T2H_MSG_TYPE_RX_FRAG_IND] = HTT_T2H_MSG_TYPE_RX_FRAG_IND,
0107     [HTT_10_4_T2H_MSG_TYPE_SEC_IND] = HTT_T2H_MSG_TYPE_SEC_IND,
0108     [HTT_10_4_T2H_MSG_TYPE_RC_UPDATE_IND] = HTT_T2H_MSG_TYPE_RC_UPDATE_IND,
0109     [HTT_10_4_T2H_MSG_TYPE_TX_INSPECT_IND] =
0110                 HTT_T2H_MSG_TYPE_TX_INSPECT_IND,
0111     [HTT_10_4_T2H_MSG_TYPE_MGMT_TX_COMPL_IND] =
0112                 HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION,
0113     [HTT_10_4_T2H_MSG_TYPE_CHAN_CHANGE] = HTT_T2H_MSG_TYPE_CHAN_CHANGE,
0114     [HTT_10_4_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND] =
0115                 HTT_T2H_MSG_TYPE_TX_CREDIT_UPDATE_IND,
0116     [HTT_10_4_T2H_MSG_TYPE_RX_PN_IND] = HTT_T2H_MSG_TYPE_RX_PN_IND,
0117     [HTT_10_4_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND] =
0118                 HTT_T2H_MSG_TYPE_RX_OFFLOAD_DELIVER_IND,
0119     [HTT_10_4_T2H_MSG_TYPE_TEST] = HTT_T2H_MSG_TYPE_TEST,
0120     [HTT_10_4_T2H_MSG_TYPE_EN_STATS] = HTT_T2H_MSG_TYPE_EN_STATS,
0121     [HTT_10_4_T2H_MSG_TYPE_AGGR_CONF] = HTT_T2H_MSG_TYPE_AGGR_CONF,
0122     [HTT_10_4_T2H_MSG_TYPE_TX_FETCH_IND] =
0123                 HTT_T2H_MSG_TYPE_TX_FETCH_IND,
0124     [HTT_10_4_T2H_MSG_TYPE_TX_FETCH_CONFIRM] =
0125                 HTT_T2H_MSG_TYPE_TX_FETCH_CONFIRM,
0126     [HTT_10_4_T2H_MSG_TYPE_STATS_NOUPLOAD] =
0127                 HTT_T2H_MSG_TYPE_STATS_NOUPLOAD,
0128     [HTT_10_4_T2H_MSG_TYPE_TX_MODE_SWITCH_IND] =
0129                 HTT_T2H_MSG_TYPE_TX_MODE_SWITCH_IND,
0130     [HTT_10_4_T2H_MSG_TYPE_PEER_STATS] =
0131                 HTT_T2H_MSG_TYPE_PEER_STATS,
0132 };
0133
0134 const struct ath10k_htt_rx_desc_ops qca988x_rx_desc_ops = {
0135     .rx_desc_size = sizeof(struct htt_rx_desc_v1),
0136     .rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v1, msdu_payload)
0137 };
0138
0139 static int ath10k_qca99x0_rx_desc_get_l3_pad_bytes(struct htt_rx_desc *rxd)
0140 {
0141     struct htt_rx_desc_v1 *rx_desc = container_of(rxd,
0142                               struct htt_rx_desc_v1,
0143                               base);
0144
0145     return MS(__le32_to_cpu(rx_desc->msdu_end.qca99x0.info1),
0146           RX_MSDU_END_INFO1_L3_HDR_PAD);
0147 }
0148
0149 static bool ath10k_qca99x0_rx_desc_msdu_limit_error(struct htt_rx_desc *rxd)
0150 {
0151     struct htt_rx_desc_v1 *rx_desc = container_of(rxd,
0152                               struct htt_rx_desc_v1,
0153                               base);
0154
0155     return !!(rx_desc->msdu_end.common.info0 &
0156           __cpu_to_le32(RX_MSDU_END_INFO0_MSDU_LIMIT_ERR));
0157 }
0158
0159 const struct ath10k_htt_rx_desc_ops qca99x0_rx_desc_ops = {
0160     .rx_desc_size = sizeof(struct htt_rx_desc_v1),
0161     .rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v1, msdu_payload),
0162
0163     .rx_desc_get_l3_pad_bytes = ath10k_qca99x0_rx_desc_get_l3_pad_bytes,
0164     .rx_desc_get_msdu_limit_error = ath10k_qca99x0_rx_desc_msdu_limit_error,
0165 };
0166
0167 static void ath10k_rx_desc_wcn3990_get_offsets(struct htt_rx_ring_rx_desc_offsets *off)
0168 {
0169 #define desc_offset(x) (offsetof(struct htt_rx_desc_v2, x) / 4)
0170     off->mac80211_hdr_offset = __cpu_to_le16(desc_offset(rx_hdr_status));
0171     off->msdu_payload_offset = __cpu_to_le16(desc_offset(msdu_payload));
0172     off->ppdu_start_offset = __cpu_to_le16(desc_offset(ppdu_start));
0173     off->ppdu_end_offset = __cpu_to_le16(desc_offset(ppdu_end));
0174     off->mpdu_start_offset = __cpu_to_le16(desc_offset(mpdu_start));
0175     off->mpdu_end_offset = __cpu_to_le16(desc_offset(mpdu_end));
0176     off->msdu_start_offset = __cpu_to_le16(desc_offset(msdu_start));
0177     off->msdu_end_offset = __cpu_to_le16(desc_offset(msdu_end));
0178     off->rx_attention_offset = __cpu_to_le16(desc_offset(attention));
0179     off->frag_info_offset = __cpu_to_le16(desc_offset(frag_info));
0180 #undef desc_offset
0181 }
0182
0183 static struct htt_rx_desc *
0184 ath10k_rx_desc_wcn3990_from_raw_buffer(void *buff)
0185 {
0186     return &((struct htt_rx_desc_v2 *)buff)->base;
0187 }
0188
0189 static struct rx_attention *
0190 ath10k_rx_desc_wcn3990_get_attention(struct htt_rx_desc *rxd)
0191 {
0192     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0193
0194     return &rx_desc->attention;
0195 }
0196
0197 static struct rx_frag_info_common *
0198 ath10k_rx_desc_wcn3990_get_frag_info(struct htt_rx_desc *rxd)
0199 {
0200     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0201
0202     return &rx_desc->frag_info.common;
0203 }
0204
0205 static struct rx_mpdu_start *
0206 ath10k_rx_desc_wcn3990_get_mpdu_start(struct htt_rx_desc *rxd)
0207 {
0208     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0209
0210     return &rx_desc->mpdu_start;
0211 }
0212
0213 static struct rx_mpdu_end *
0214 ath10k_rx_desc_wcn3990_get_mpdu_end(struct htt_rx_desc *rxd)
0215 {
0216     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0217
0218     return &rx_desc->mpdu_end;
0219 }
0220
0221 static struct rx_msdu_start_common *
0222 ath10k_rx_desc_wcn3990_get_msdu_start(struct htt_rx_desc *rxd)
0223 {
0224     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0225
0226     return &rx_desc->msdu_start.common;
0227 }
0228
0229 static struct rx_msdu_end_common *
0230 ath10k_rx_desc_wcn3990_get_msdu_end(struct htt_rx_desc *rxd)
0231 {
0232     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0233
0234     return &rx_desc->msdu_end.common;
0235 }
0236
0237 static struct rx_ppdu_start *
0238 ath10k_rx_desc_wcn3990_get_ppdu_start(struct htt_rx_desc *rxd)
0239 {
0240     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0241
0242     return &rx_desc->ppdu_start;
0243 }
0244
0245 static struct rx_ppdu_end_common *
0246 ath10k_rx_desc_wcn3990_get_ppdu_end(struct htt_rx_desc *rxd)
0247 {
0248     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0249
0250     return &rx_desc->ppdu_end.common;
0251 }
0252
0253 static u8 *
0254 ath10k_rx_desc_wcn3990_get_rx_hdr_status(struct htt_rx_desc *rxd)
0255 {
0256     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0257
0258     return rx_desc->rx_hdr_status;
0259 }
0260
0261 static u8 *
0262 ath10k_rx_desc_wcn3990_get_msdu_payload(struct htt_rx_desc *rxd)
0263 {
0264     struct htt_rx_desc_v2 *rx_desc = container_of(rxd, struct htt_rx_desc_v2, base);
0265
0266     return rx_desc->msdu_payload;
0267 }
0268
0269 const struct ath10k_htt_rx_desc_ops wcn3990_rx_desc_ops = {
0270     .rx_desc_size = sizeof(struct htt_rx_desc_v2),
0271     .rx_desc_msdu_payload_offset = offsetof(struct htt_rx_desc_v2, msdu_payload),
0272
0273     .rx_desc_from_raw_buffer = ath10k_rx_desc_wcn3990_from_raw_buffer,
0274     .rx_desc_get_offsets = ath10k_rx_desc_wcn3990_get_offsets,
0275     .rx_desc_get_attention = ath10k_rx_desc_wcn3990_get_attention,
0276     .rx_desc_get_frag_info = ath10k_rx_desc_wcn3990_get_frag_info,
0277     .rx_desc_get_mpdu_start = ath10k_rx_desc_wcn3990_get_mpdu_start,
0278     .rx_desc_get_mpdu_end = ath10k_rx_desc_wcn3990_get_mpdu_end,
0279     .rx_desc_get_msdu_start = ath10k_rx_desc_wcn3990_get_msdu_start,
0280     .rx_desc_get_msdu_end = ath10k_rx_desc_wcn3990_get_msdu_end,
0281     .rx_desc_get_ppdu_start = ath10k_rx_desc_wcn3990_get_ppdu_start,
0282     .rx_desc_get_ppdu_end = ath10k_rx_desc_wcn3990_get_ppdu_end,
0283     .rx_desc_get_rx_hdr_status = ath10k_rx_desc_wcn3990_get_rx_hdr_status,
0284     .rx_desc_get_msdu_payload = ath10k_rx_desc_wcn3990_get_msdu_payload,
0285 };
0286
0287 int ath10k_htt_connect(struct ath10k_htt *htt)
0288 {
0289     struct ath10k_htc_svc_conn_req conn_req;
0290     struct ath10k_htc_svc_conn_resp conn_resp;
0291     struct ath10k *ar = htt->ar;
0292     struct ath10k_htc_ep *ep;
0293     int status;
0294
0295     memset(&conn_req, 0, sizeof(conn_req));
0296     memset(&conn_resp, 0, sizeof(conn_resp));
0297
0298     conn_req.ep_ops.ep_tx_complete = ath10k_htt_htc_tx_complete;
0299     conn_req.ep_ops.ep_rx_complete = ath10k_htt_htc_t2h_msg_handler;
0300     conn_req.ep_ops.ep_tx_credits = ath10k_htt_op_ep_tx_credits;
0301
0302     /* connect to control service */
0303     conn_req.service_id = ATH10K_HTC_SVC_ID_HTT_DATA_MSG;
0304
0305     status = ath10k_htc_connect_service(&htt->ar->htc, &conn_req,
0306                         &conn_resp);
0307
0308     if (status)
0309         return status;
0310
0311     htt->eid = conn_resp.eid;
0312
0313     if (ar->bus_param.dev_type == ATH10K_DEV_TYPE_HL) {
0314         ep = &ar->htc.endpoint[htt->eid];
0315         ath10k_htc_setup_tx_req(ep);
0316     }
0317
0318     htt->disable_tx_comp = ath10k_hif_get_htt_tx_complete(htt->ar);
0319     if (htt->disable_tx_comp)
0320         ath10k_htc_change_tx_credit_flow(&htt->ar->htc, htt->eid, true);
0321
0322     return 0;
0323 }
0324
0325 int ath10k_htt_init(struct ath10k *ar)
0326 {
0327     struct ath10k_htt *htt = &ar->htt;
0328
0329     htt->ar = ar;
0330
0331     /*
0332      * Prefetch enough data to satisfy target
0333      * classification engine.
0334      * This is for LL chips. HL chips will probably
0335      * transfer all frame in the tx fragment.
0336      */
0337     htt->prefetch_len =
0338         36 + /* 802.11 + qos + ht */
0339         4 + /* 802.1q */
0340         8 + /* llc snap */
0341         2; /* ip4 dscp or ip6 priority */
0342
0343     switch (ar->running_fw->fw_file.htt_op_version) {
0344     case ATH10K_FW_HTT_OP_VERSION_10_4:
0345         ar->htt.t2h_msg_types = htt_10_4_t2h_msg_types;
0346         ar->htt.t2h_msg_types_max = HTT_10_4_T2H_NUM_MSGS;
0347         break;
0348     case ATH10K_FW_HTT_OP_VERSION_10_1:
0349         ar->htt.t2h_msg_types = htt_10x_t2h_msg_types;
0350         ar->htt.t2h_msg_types_max = HTT_10X_T2H_NUM_MSGS;
0351         break;
0352     case ATH10K_FW_HTT_OP_VERSION_TLV:
0353         ar->htt.t2h_msg_types = htt_tlv_t2h_msg_types;
0354         ar->htt.t2h_msg_types_max = HTT_TLV_T2H_NUM_MSGS;
0355         break;
0356     case ATH10K_FW_HTT_OP_VERSION_MAIN:
0357         ar->htt.t2h_msg_types = htt_main_t2h_msg_types;
0358         ar->htt.t2h_msg_types_max = HTT_MAIN_T2H_NUM_MSGS;
0359         break;
0360     case ATH10K_FW_HTT_OP_VERSION_MAX:
0361     case ATH10K_FW_HTT_OP_VERSION_UNSET:
0362         WARN_ON(1);
0363         return -EINVAL;
0364     }
0365     ath10k_htt_set_tx_ops(htt);
0366     ath10k_htt_set_rx_ops(htt);
0367
0368     return 0;
0369 }
0370
0371 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
0372
0373 static int ath10k_htt_verify_version(struct ath10k_htt *htt)
0374 {
0375     struct ath10k *ar = htt->ar;
0376
0377     ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt target version %d.%d\n",
0378            htt->target_version_major, htt->target_version_minor);
0379
0380     if (htt->target_version_major != 2 &&
0381         htt->target_version_major != 3) {
0382         ath10k_err(ar, "unsupported htt major version %d. supported versions are 2 and 3\n",
0383                htt->target_version_major);
0384         return -ENOTSUPP;
0385     }
0386
0387     return 0;
0388 }
0389
0390 int ath10k_htt_setup(struct ath10k_htt *htt)
0391 {
0392     struct ath10k *ar = htt->ar;
0393     int status;
0394
0395     init_completion(&htt->target_version_received);
0396
0397     status = ath10k_htt_h2t_ver_req_msg(htt);
0398     if (status)
0399         return status;
0400
0401     status = wait_for_completion_timeout(&htt->target_version_received,
0402                          HTT_TARGET_VERSION_TIMEOUT_HZ);
0403     if (status == 0) {
0404         ath10k_warn(ar, "htt version request timed out\n");
0405         return -ETIMEDOUT;
0406     }
0407
0408     status = ath10k_htt_verify_version(htt);
0409     if (status) {
0410         ath10k_warn(ar, "failed to verify htt version: %d\n",
0411                 status);
0412         return status;
0413     }
0414
0415     status = ath10k_htt_send_frag_desc_bank_cfg(htt);
0416     if (status)
0417         return status;
0418
0419     status = ath10k_htt_send_rx_ring_cfg(htt);
0420     if (status) {
0421         ath10k_warn(ar, "failed to setup rx ring: %d\n",
0422                 status);
0423         return status;
0424     }
0425
0426     status = ath10k_htt_h2t_aggr_cfg_msg(htt,
0427                          htt->max_num_ampdu,
0428                          htt->max_num_amsdu);
0429     if (status) {
0430         ath10k_warn(ar, "failed to setup amsdu/ampdu limit: %d\n",
0431                 status);
0432         return status;
0433     }
0434
0435     return 0;
0436 }