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0008 #ifndef _CORE_H_
0009 #define _CORE_H_
0010
0011 #include <linux/completion.h>
0012 #include <linux/if_ether.h>
0013 #include <linux/types.h>
0014 #include <linux/pci.h>
0015 #include <linux/uuid.h>
0016 #include <linux/time.h>
0017
0018 #include "htt.h"
0019 #include "htc.h"
0020 #include "hw.h"
0021 #include "targaddrs.h"
0022 #include "wmi.h"
0023 #include "../ath.h"
0024 #include "../regd.h"
0025 #include "../dfs_pattern_detector.h"
0026 #include "spectral.h"
0027 #include "thermal.h"
0028 #include "wow.h"
0029 #include "swap.h"
0030
0031 #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
0032 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
0033 #define WO(_f) ((_f##_OFFSET) >> 2)
0034
0035 #define ATH10K_SCAN_ID 0
0036 #define ATH10K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD 10
0037 #define WMI_READY_TIMEOUT (5 * HZ)
0038 #define ATH10K_FLUSH_TIMEOUT_HZ (5 * HZ)
0039 #define ATH10K_CONNECTION_LOSS_HZ (3 * HZ)
0040 #define ATH10K_NUM_CHANS 41
0041 #define ATH10K_MAX_5G_CHAN 173
0042
0043
0044 #define ATH10K_DEFAULT_NOISE_FLOOR -95
0045
0046 #define ATH10K_INVALID_RSSI 128
0047
0048 #define ATH10K_MAX_NUM_MGMT_PENDING 128
0049
0050
0051 #define ATH10K_KICKOUT_THRESHOLD (20 * 16)
0052
0053
0054
0055
0056
0057
0058 #define ATH10K_KEEPALIVE_MIN_IDLE 3747
0059 #define ATH10K_KEEPALIVE_MAX_IDLE 3895
0060 #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
0061
0062
0063 #define ATH10K_SMBIOS_BDF_EXT_TYPE 0xF8
0064
0065
0066 #define ATH10K_SMBIOS_BDF_EXT_LENGTH 0x9
0067
0068
0069 #define ATH10K_SMBIOS_BDF_EXT_OFFSET 0x8
0070
0071
0072
0073
0074 #define ATH10K_SMBIOS_BDF_EXT_STR_LENGTH 0x20
0075
0076
0077 #define ATH10K_SMBIOS_BDF_EXT_MAGIC "BDF_"
0078
0079
0080 #define ATH10K_AIRTIME_WEIGHT_MULTIPLIER 4
0081
0082 #define ATH10K_MAX_RETRY_COUNT 30
0083
0084 #define ATH10K_ITER_NORMAL_FLAGS (IEEE80211_IFACE_ITER_NORMAL | \
0085 IEEE80211_IFACE_SKIP_SDATA_NOT_IN_DRIVER)
0086 #define ATH10K_ITER_RESUME_FLAGS (IEEE80211_IFACE_ITER_RESUME_ALL |\
0087 IEEE80211_IFACE_SKIP_SDATA_NOT_IN_DRIVER)
0088
0089 struct ath10k;
0090
0091 static inline const char *ath10k_bus_str(enum ath10k_bus bus)
0092 {
0093 switch (bus) {
0094 case ATH10K_BUS_PCI:
0095 return "pci";
0096 case ATH10K_BUS_AHB:
0097 return "ahb";
0098 case ATH10K_BUS_SDIO:
0099 return "sdio";
0100 case ATH10K_BUS_USB:
0101 return "usb";
0102 case ATH10K_BUS_SNOC:
0103 return "snoc";
0104 }
0105
0106 return "unknown";
0107 }
0108
0109 enum ath10k_skb_flags {
0110 ATH10K_SKB_F_NO_HWCRYPT = BIT(0),
0111 ATH10K_SKB_F_DTIM_ZERO = BIT(1),
0112 ATH10K_SKB_F_DELIVER_CAB = BIT(2),
0113 ATH10K_SKB_F_MGMT = BIT(3),
0114 ATH10K_SKB_F_QOS = BIT(4),
0115 ATH10K_SKB_F_RAW_TX = BIT(5),
0116 ATH10K_SKB_F_NOACK_TID = BIT(6),
0117 };
0118
0119 struct ath10k_skb_cb {
0120 dma_addr_t paddr;
0121 u8 flags;
0122 u8 eid;
0123 u16 msdu_id;
0124 u16 airtime_est;
0125 struct ieee80211_vif *vif;
0126 struct ieee80211_txq *txq;
0127 u32 ucast_cipher;
0128 } __packed;
0129
0130 struct ath10k_skb_rxcb {
0131 dma_addr_t paddr;
0132 struct hlist_node hlist;
0133 u8 eid;
0134 };
0135
0136 static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
0137 {
0138 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
0139 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
0140 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
0141 }
0142
0143 static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
0144 {
0145 BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
0146 return (struct ath10k_skb_rxcb *)skb->cb;
0147 }
0148
0149 #define ATH10K_RXCB_SKB(rxcb) \
0150 container_of((void *)rxcb, struct sk_buff, cb)
0151
0152 static inline u32 host_interest_item_address(u32 item_offset)
0153 {
0154 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
0155 }
0156
0157 enum ath10k_phy_mode {
0158 ATH10K_PHY_MODE_LEGACY = 0,
0159 ATH10K_PHY_MODE_HT = 1,
0160 ATH10K_PHY_MODE_VHT = 2,
0161 };
0162
0163
0164 struct ath10k_index_ht_data_rate_type {
0165 u8 beacon_rate_index;
0166 u16 supported_rate[4];
0167 };
0168
0169
0170 struct ath10k_index_vht_data_rate_type {
0171 u8 beacon_rate_index;
0172 u16 supported_VHT80_rate[2];
0173 u16 supported_VHT40_rate[2];
0174 u16 supported_VHT20_rate[2];
0175 };
0176
0177 struct ath10k_bmi {
0178 bool done_sent;
0179 };
0180
0181 struct ath10k_mem_chunk {
0182 void *vaddr;
0183 dma_addr_t paddr;
0184 u32 len;
0185 u32 req_id;
0186 };
0187
0188 struct ath10k_wmi {
0189 enum ath10k_htc_ep_id eid;
0190 struct completion service_ready;
0191 struct completion unified_ready;
0192 struct completion barrier;
0193 struct completion radar_confirm;
0194 wait_queue_head_t tx_credits_wq;
0195 DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
0196 struct wmi_cmd_map *cmd;
0197 struct wmi_vdev_param_map *vdev_param;
0198 struct wmi_pdev_param_map *pdev_param;
0199 struct wmi_peer_param_map *peer_param;
0200 const struct wmi_ops *ops;
0201 const struct wmi_peer_flags_map *peer_flags;
0202
0203 u32 mgmt_max_num_pending_tx;
0204
0205
0206 struct idr mgmt_pending_tx;
0207
0208 u32 num_mem_chunks;
0209 u32 rx_decap_mode;
0210 struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
0211 };
0212
0213 struct ath10k_fw_stats_peer {
0214 struct list_head list;
0215
0216 u8 peer_macaddr[ETH_ALEN];
0217 u32 peer_rssi;
0218 u32 peer_tx_rate;
0219 u32 peer_rx_rate;
0220 u64 rx_duration;
0221 };
0222
0223 struct ath10k_fw_extd_stats_peer {
0224 struct list_head list;
0225
0226 u8 peer_macaddr[ETH_ALEN];
0227 u64 rx_duration;
0228 };
0229
0230 struct ath10k_fw_stats_vdev {
0231 struct list_head list;
0232
0233 u32 vdev_id;
0234 u32 beacon_snr;
0235 u32 data_snr;
0236 u32 num_tx_frames[4];
0237 u32 num_rx_frames;
0238 u32 num_tx_frames_retries[4];
0239 u32 num_tx_frames_failures[4];
0240 u32 num_rts_fail;
0241 u32 num_rts_success;
0242 u32 num_rx_err;
0243 u32 num_rx_discard;
0244 u32 num_tx_not_acked;
0245 u32 tx_rate_history[10];
0246 u32 beacon_rssi_history[10];
0247 };
0248
0249 struct ath10k_fw_stats_vdev_extd {
0250 struct list_head list;
0251
0252 u32 vdev_id;
0253 u32 ppdu_aggr_cnt;
0254 u32 ppdu_noack;
0255 u32 mpdu_queued;
0256 u32 ppdu_nonaggr_cnt;
0257 u32 mpdu_sw_requeued;
0258 u32 mpdu_suc_retry;
0259 u32 mpdu_suc_multitry;
0260 u32 mpdu_fail_retry;
0261 u32 tx_ftm_suc;
0262 u32 tx_ftm_suc_retry;
0263 u32 tx_ftm_fail;
0264 u32 rx_ftmr_cnt;
0265 u32 rx_ftmr_dup_cnt;
0266 u32 rx_iftmr_cnt;
0267 u32 rx_iftmr_dup_cnt;
0268 };
0269
0270 struct ath10k_fw_stats_pdev {
0271 struct list_head list;
0272
0273
0274 s32 ch_noise_floor;
0275 u32 tx_frame_count;
0276 u32 rx_frame_count;
0277 u32 rx_clear_count;
0278 u32 cycle_count;
0279 u32 phy_err_count;
0280 u32 chan_tx_power;
0281 u32 ack_rx_bad;
0282 u32 rts_bad;
0283 u32 rts_good;
0284 u32 fcs_bad;
0285 u32 no_beacons;
0286 u32 mib_int_count;
0287
0288
0289 s32 comp_queued;
0290 s32 comp_delivered;
0291 s32 msdu_enqued;
0292 s32 mpdu_enqued;
0293 s32 wmm_drop;
0294 s32 local_enqued;
0295 s32 local_freed;
0296 s32 hw_queued;
0297 s32 hw_reaped;
0298 s32 underrun;
0299 u32 hw_paused;
0300 s32 tx_abort;
0301 s32 mpdus_requeued;
0302 u32 tx_ko;
0303 u32 data_rc;
0304 u32 self_triggers;
0305 u32 sw_retry_failure;
0306 u32 illgl_rate_phy_err;
0307 u32 pdev_cont_xretry;
0308 u32 pdev_tx_timeout;
0309 u32 pdev_resets;
0310 u32 phy_underrun;
0311 u32 txop_ovf;
0312 u32 seq_posted;
0313 u32 seq_failed_queueing;
0314 u32 seq_completed;
0315 u32 seq_restarted;
0316 u32 mu_seq_posted;
0317 u32 mpdus_sw_flush;
0318 u32 mpdus_hw_filter;
0319 u32 mpdus_truncated;
0320 u32 mpdus_ack_failed;
0321 u32 mpdus_expired;
0322
0323
0324 s32 mid_ppdu_route_change;
0325 s32 status_rcvd;
0326 s32 r0_frags;
0327 s32 r1_frags;
0328 s32 r2_frags;
0329 s32 r3_frags;
0330 s32 htt_msdus;
0331 s32 htt_mpdus;
0332 s32 loc_msdus;
0333 s32 loc_mpdus;
0334 s32 oversize_amsdu;
0335 s32 phy_errs;
0336 s32 phy_err_drop;
0337 s32 mpdu_errs;
0338 s32 rx_ovfl_errs;
0339 };
0340
0341 struct ath10k_fw_stats {
0342 bool extended;
0343 struct list_head pdevs;
0344 struct list_head vdevs;
0345 struct list_head peers;
0346 struct list_head peers_extd;
0347 };
0348
0349 #define ATH10K_TPC_TABLE_TYPE_FLAG 1
0350 #define ATH10K_TPC_PREAM_TABLE_END 0xFFFF
0351
0352 struct ath10k_tpc_table {
0353 u32 pream_idx[WMI_TPC_RATE_MAX];
0354 u8 rate_code[WMI_TPC_RATE_MAX];
0355 char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
0356 };
0357
0358 struct ath10k_tpc_stats {
0359 u32 reg_domain;
0360 u32 chan_freq;
0361 u32 phy_mode;
0362 u32 twice_antenna_reduction;
0363 u32 twice_max_rd_power;
0364 s32 twice_antenna_gain;
0365 u32 power_limit;
0366 u32 num_tx_chain;
0367 u32 ctl;
0368 u32 rate_max;
0369 u8 flag[WMI_TPC_FLAG];
0370 struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
0371 };
0372
0373 struct ath10k_tpc_table_final {
0374 u32 pream_idx[WMI_TPC_FINAL_RATE_MAX];
0375 u8 rate_code[WMI_TPC_FINAL_RATE_MAX];
0376 char tpc_value[WMI_TPC_FINAL_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
0377 };
0378
0379 struct ath10k_tpc_stats_final {
0380 u32 reg_domain;
0381 u32 chan_freq;
0382 u32 phy_mode;
0383 u32 twice_antenna_reduction;
0384 u32 twice_max_rd_power;
0385 s32 twice_antenna_gain;
0386 u32 power_limit;
0387 u32 num_tx_chain;
0388 u32 ctl;
0389 u32 rate_max;
0390 u8 flag[WMI_TPC_FLAG];
0391 struct ath10k_tpc_table_final tpc_table_final[WMI_TPC_FLAG];
0392 };
0393
0394 struct ath10k_dfs_stats {
0395 u32 phy_errors;
0396 u32 pulses_total;
0397 u32 pulses_detected;
0398 u32 pulses_discarded;
0399 u32 radar_detected;
0400 };
0401
0402 enum ath10k_radar_confirmation_state {
0403 ATH10K_RADAR_CONFIRMATION_IDLE = 0,
0404 ATH10K_RADAR_CONFIRMATION_INPROGRESS,
0405 ATH10K_RADAR_CONFIRMATION_STOPPED,
0406 };
0407
0408 struct ath10k_radar_found_info {
0409 u32 pri_min;
0410 u32 pri_max;
0411 u32 width_min;
0412 u32 width_max;
0413 u32 sidx_min;
0414 u32 sidx_max;
0415 };
0416
0417 #define ATH10K_MAX_NUM_PEER_IDS (1 << 11)
0418
0419 struct ath10k_peer {
0420 struct list_head list;
0421 struct ieee80211_vif *vif;
0422 struct ieee80211_sta *sta;
0423
0424 bool removed;
0425 int vdev_id;
0426 u8 addr[ETH_ALEN];
0427 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
0428
0429
0430 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
0431 union htt_rx_pn_t tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS];
0432 bool tids_last_pn_valid[ATH10K_TXRX_NUM_EXT_TIDS];
0433 union htt_rx_pn_t frag_tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS];
0434 u32 frag_tids_seq[ATH10K_TXRX_NUM_EXT_TIDS];
0435 struct {
0436 enum htt_security_types sec_type;
0437 int pn_len;
0438 } rx_pn[ATH10K_HTT_TXRX_PEER_SECURITY_MAX];
0439 };
0440
0441 struct ath10k_txq {
0442 struct list_head list;
0443 unsigned long num_fw_queued;
0444 unsigned long num_push_allowed;
0445 };
0446
0447 enum ath10k_pkt_rx_err {
0448 ATH10K_PKT_RX_ERR_FCS,
0449 ATH10K_PKT_RX_ERR_TKIP,
0450 ATH10K_PKT_RX_ERR_CRYPT,
0451 ATH10K_PKT_RX_ERR_PEER_IDX_INVAL,
0452 ATH10K_PKT_RX_ERR_MAX,
0453 };
0454
0455 enum ath10k_ampdu_subfrm_num {
0456 ATH10K_AMPDU_SUBFRM_NUM_10,
0457 ATH10K_AMPDU_SUBFRM_NUM_20,
0458 ATH10K_AMPDU_SUBFRM_NUM_30,
0459 ATH10K_AMPDU_SUBFRM_NUM_40,
0460 ATH10K_AMPDU_SUBFRM_NUM_50,
0461 ATH10K_AMPDU_SUBFRM_NUM_60,
0462 ATH10K_AMPDU_SUBFRM_NUM_MORE,
0463 ATH10K_AMPDU_SUBFRM_NUM_MAX,
0464 };
0465
0466 enum ath10k_amsdu_subfrm_num {
0467 ATH10K_AMSDU_SUBFRM_NUM_1,
0468 ATH10K_AMSDU_SUBFRM_NUM_2,
0469 ATH10K_AMSDU_SUBFRM_NUM_3,
0470 ATH10K_AMSDU_SUBFRM_NUM_4,
0471 ATH10K_AMSDU_SUBFRM_NUM_MORE,
0472 ATH10K_AMSDU_SUBFRM_NUM_MAX,
0473 };
0474
0475 struct ath10k_sta_tid_stats {
0476 unsigned long rx_pkt_from_fw;
0477 unsigned long rx_pkt_unchained;
0478 unsigned long rx_pkt_drop_chained;
0479 unsigned long rx_pkt_drop_filter;
0480 unsigned long rx_pkt_err[ATH10K_PKT_RX_ERR_MAX];
0481 unsigned long rx_pkt_queued_for_mac;
0482 unsigned long rx_pkt_ampdu[ATH10K_AMPDU_SUBFRM_NUM_MAX];
0483 unsigned long rx_pkt_amsdu[ATH10K_AMSDU_SUBFRM_NUM_MAX];
0484 };
0485
0486 enum ath10k_counter_type {
0487 ATH10K_COUNTER_TYPE_BYTES,
0488 ATH10K_COUNTER_TYPE_PKTS,
0489 ATH10K_COUNTER_TYPE_MAX,
0490 };
0491
0492 enum ath10k_stats_type {
0493 ATH10K_STATS_TYPE_SUCC,
0494 ATH10K_STATS_TYPE_FAIL,
0495 ATH10K_STATS_TYPE_RETRY,
0496 ATH10K_STATS_TYPE_AMPDU,
0497 ATH10K_STATS_TYPE_MAX,
0498 };
0499
0500 struct ath10k_htt_data_stats {
0501 u64 legacy[ATH10K_COUNTER_TYPE_MAX][ATH10K_LEGACY_NUM];
0502 u64 ht[ATH10K_COUNTER_TYPE_MAX][ATH10K_HT_MCS_NUM];
0503 u64 vht[ATH10K_COUNTER_TYPE_MAX][ATH10K_VHT_MCS_NUM];
0504 u64 bw[ATH10K_COUNTER_TYPE_MAX][ATH10K_BW_NUM];
0505 u64 nss[ATH10K_COUNTER_TYPE_MAX][ATH10K_NSS_NUM];
0506 u64 gi[ATH10K_COUNTER_TYPE_MAX][ATH10K_GI_NUM];
0507 u64 rate_table[ATH10K_COUNTER_TYPE_MAX][ATH10K_RATE_TABLE_NUM];
0508 };
0509
0510 struct ath10k_htt_tx_stats {
0511 struct ath10k_htt_data_stats stats[ATH10K_STATS_TYPE_MAX];
0512 u64 tx_duration;
0513 u64 ba_fails;
0514 u64 ack_fails;
0515 };
0516
0517 #define ATH10K_TID_MAX 8
0518
0519 struct ath10k_sta {
0520 struct ath10k_vif *arvif;
0521
0522
0523 u32 changed;
0524 u32 bw;
0525 u32 nss;
0526 u32 smps;
0527 u16 peer_id;
0528 struct rate_info txrate;
0529 struct ieee80211_tx_info tx_info;
0530 u32 tx_retries;
0531 u32 tx_failed;
0532 u32 last_tx_bitrate;
0533
0534 u32 rx_rate_code;
0535 u32 rx_bitrate_kbps;
0536 u32 tx_rate_code;
0537 u32 tx_bitrate_kbps;
0538 struct work_struct update_wk;
0539 u64 rx_duration;
0540 struct ath10k_htt_tx_stats *tx_stats;
0541 u32 ucast_cipher;
0542
0543 #ifdef CONFIG_MAC80211_DEBUGFS
0544
0545 bool aggr_mode;
0546
0547
0548 struct ath10k_sta_tid_stats tid_stats[IEEE80211_NUM_TIDS + 1];
0549 #endif
0550
0551 u32 peer_ps_state;
0552 struct work_struct tid_config_wk;
0553 int noack[ATH10K_TID_MAX];
0554 int retry_long[ATH10K_TID_MAX];
0555 int ampdu[ATH10K_TID_MAX];
0556 u8 rate_ctrl[ATH10K_TID_MAX];
0557 u32 rate_code[ATH10K_TID_MAX];
0558 int rtscts[ATH10K_TID_MAX];
0559 };
0560
0561 #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ)
0562 #define ATH10K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
0563
0564 enum ath10k_beacon_state {
0565 ATH10K_BEACON_SCHEDULED = 0,
0566 ATH10K_BEACON_SENDING,
0567 ATH10K_BEACON_SENT,
0568 };
0569
0570 struct ath10k_vif {
0571 struct list_head list;
0572
0573 u32 vdev_id;
0574 u16 peer_id;
0575 enum wmi_vdev_type vdev_type;
0576 enum wmi_vdev_subtype vdev_subtype;
0577 u32 beacon_interval;
0578 u32 dtim_period;
0579 struct sk_buff *beacon;
0580
0581 enum ath10k_beacon_state beacon_state;
0582 void *beacon_buf;
0583 dma_addr_t beacon_paddr;
0584 unsigned long tx_paused;
0585
0586 struct ath10k *ar;
0587 struct ieee80211_vif *vif;
0588
0589 bool is_started;
0590 bool is_up;
0591 bool spectral_enabled;
0592 bool ps;
0593 u32 aid;
0594 u8 bssid[ETH_ALEN];
0595
0596 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
0597 s8 def_wep_key_idx;
0598
0599 u16 tx_seq_no;
0600
0601 union {
0602 struct {
0603 u32 uapsd;
0604 } sta;
0605 struct {
0606
0607 u8 tim_bitmap[64];
0608 u8 tim_len;
0609 u32 ssid_len;
0610 u8 ssid[IEEE80211_MAX_SSID_LEN];
0611 bool hidden_ssid;
0612
0613 u32 noa_len;
0614 u8 *noa_data;
0615 } ap;
0616 } u;
0617
0618 bool use_cts_prot;
0619 bool nohwcrypt;
0620 int num_legacy_stations;
0621 int txpower;
0622 bool ftm_responder;
0623 struct wmi_wmm_params_all_arg wmm_params;
0624 struct work_struct ap_csa_work;
0625 struct delayed_work connection_loss_work;
0626 struct cfg80211_bitrate_mask bitrate_mask;
0627
0628
0629 int vht_num_rates;
0630 u8 vht_pfr;
0631 u32 tid_conf_changed[ATH10K_TID_MAX];
0632 int noack[ATH10K_TID_MAX];
0633 int retry_long[ATH10K_TID_MAX];
0634 int ampdu[ATH10K_TID_MAX];
0635 u8 rate_ctrl[ATH10K_TID_MAX];
0636 u32 rate_code[ATH10K_TID_MAX];
0637 int rtscts[ATH10K_TID_MAX];
0638 u32 tids_rst;
0639 };
0640
0641 struct ath10k_vif_iter {
0642 u32 vdev_id;
0643 struct ath10k_vif *arvif;
0644 };
0645
0646
0647 struct ath10k_ce_crash_data {
0648 __le32 base_addr;
0649 __le32 src_wr_idx;
0650 __le32 src_r_idx;
0651 __le32 dst_wr_idx;
0652 __le32 dst_r_idx;
0653 };
0654
0655 struct ath10k_ce_crash_hdr {
0656 __le32 ce_count;
0657 __le32 reserved[3];
0658 struct ath10k_ce_crash_data entries[];
0659 };
0660
0661 #define MAX_MEM_DUMP_TYPE 5
0662
0663
0664 struct ath10k_fw_crash_data {
0665 guid_t guid;
0666 struct timespec64 timestamp;
0667 __le32 registers[REG_DUMP_COUNT_QCA988X];
0668 struct ath10k_ce_crash_data ce_crash_data[CE_COUNT_MAX];
0669
0670 u8 *ramdump_buf;
0671 size_t ramdump_buf_len;
0672 };
0673
0674 struct ath10k_debug {
0675 struct dentry *debugfs_phy;
0676
0677 struct ath10k_fw_stats fw_stats;
0678 struct completion fw_stats_complete;
0679 bool fw_stats_done;
0680
0681 unsigned long htt_stats_mask;
0682 unsigned long reset_htt_stats;
0683 struct delayed_work htt_stats_dwork;
0684 struct ath10k_dfs_stats dfs_stats;
0685 struct ath_dfs_pool_stats dfs_pool_stats;
0686
0687
0688 struct ath10k_tpc_stats *tpc_stats;
0689 struct ath10k_tpc_stats_final *tpc_stats_final;
0690
0691 struct completion tpc_complete;
0692
0693
0694 u64 fw_dbglog_mask;
0695 u32 fw_dbglog_level;
0696 u32 reg_addr;
0697 u32 nf_cal_period;
0698 void *cal_data;
0699 u32 enable_extd_tx_stats;
0700 u8 fw_dbglog_mode;
0701 };
0702
0703 enum ath10k_state {
0704 ATH10K_STATE_OFF = 0,
0705 ATH10K_STATE_ON,
0706
0707
0708
0709
0710
0711
0712
0713
0714
0715
0716 ATH10K_STATE_RESTARTING,
0717 ATH10K_STATE_RESTARTED,
0718
0719
0720
0721
0722
0723
0724 ATH10K_STATE_WEDGED,
0725
0726
0727 ATH10K_STATE_UTF,
0728 };
0729
0730 enum ath10k_firmware_mode {
0731
0732 ATH10K_FIRMWARE_MODE_NORMAL,
0733
0734
0735 ATH10K_FIRMWARE_MODE_UTF,
0736 };
0737
0738 enum ath10k_fw_features {
0739
0740 ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
0741
0742
0743 ATH10K_FW_FEATURE_WMI_10X = 1,
0744
0745
0746 ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
0747
0748
0749 ATH10K_FW_FEATURE_NO_P2P = 3,
0750
0751
0752
0753
0754
0755 ATH10K_FW_FEATURE_WMI_10_2 = 4,
0756
0757
0758
0759
0760
0761 ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
0762
0763
0764
0765
0766
0767 ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6,
0768
0769
0770 ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7,
0771
0772
0773
0774
0775 ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8,
0776
0777
0778 ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9,
0779
0780
0781
0782
0783 ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10,
0784
0785
0786 ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11,
0787
0788
0789 ATH10K_FW_FEATURE_MFP_SUPPORT = 12,
0790
0791
0792
0793
0794
0795
0796
0797
0798 ATH10K_FW_FEATURE_PEER_FLOW_CONTROL = 13,
0799
0800
0801
0802
0803
0804
0805 ATH10K_FW_FEATURE_BTCOEX_PARAM = 14,
0806
0807
0808
0809
0810 ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR = 15,
0811
0812
0813
0814
0815
0816
0817 ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST = 16,
0818
0819
0820 ATH10K_FW_FEATURE_NO_PS = 17,
0821
0822
0823 ATH10K_FW_FEATURE_MGMT_TX_BY_REF = 18,
0824
0825
0826 ATH10K_FW_FEATURE_NON_BMI = 19,
0827
0828
0829 ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL = 20,
0830
0831
0832 ATH10K_FW_FEATURE_PEER_FIXED_RATE = 21,
0833
0834
0835 ATH10K_FW_FEATURE_IRAM_RECOVERY = 22,
0836
0837
0838 ATH10K_FW_FEATURE_COUNT,
0839 };
0840
0841 enum ath10k_dev_flags {
0842
0843 ATH10K_CAC_RUNNING,
0844 ATH10K_FLAG_CORE_REGISTERED,
0845
0846
0847
0848
0849 ATH10K_FLAG_CRASH_FLUSH,
0850
0851
0852
0853
0854
0855 ATH10K_FLAG_RAW_MODE,
0856
0857
0858 ATH10K_FLAG_HW_CRYPTO_DISABLED,
0859
0860
0861 ATH10K_FLAG_BTCOEX,
0862
0863
0864 ATH10K_FLAG_PEER_STATS,
0865
0866
0867 ATH10K_FLAG_RESTARTING,
0868
0869
0870 ATH10K_FLAG_NAPI_ENABLED,
0871 };
0872
0873 enum ath10k_cal_mode {
0874 ATH10K_CAL_MODE_FILE,
0875 ATH10K_CAL_MODE_OTP,
0876 ATH10K_CAL_MODE_DT,
0877 ATH10K_CAL_MODE_NVMEM,
0878 ATH10K_PRE_CAL_MODE_FILE,
0879 ATH10K_PRE_CAL_MODE_DT,
0880 ATH10K_PRE_CAL_MODE_NVMEM,
0881 ATH10K_CAL_MODE_EEPROM,
0882 };
0883
0884 enum ath10k_crypt_mode {
0885
0886 ATH10K_CRYPT_MODE_HW,
0887
0888 ATH10K_CRYPT_MODE_SW,
0889 };
0890
0891 static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
0892 {
0893 switch (mode) {
0894 case ATH10K_CAL_MODE_FILE:
0895 return "file";
0896 case ATH10K_CAL_MODE_OTP:
0897 return "otp";
0898 case ATH10K_CAL_MODE_DT:
0899 return "dt";
0900 case ATH10K_CAL_MODE_NVMEM:
0901 return "nvmem";
0902 case ATH10K_PRE_CAL_MODE_FILE:
0903 return "pre-cal-file";
0904 case ATH10K_PRE_CAL_MODE_DT:
0905 return "pre-cal-dt";
0906 case ATH10K_PRE_CAL_MODE_NVMEM:
0907 return "pre-cal-nvmem";
0908 case ATH10K_CAL_MODE_EEPROM:
0909 return "eeprom";
0910 }
0911
0912 return "unknown";
0913 }
0914
0915 enum ath10k_scan_state {
0916 ATH10K_SCAN_IDLE,
0917 ATH10K_SCAN_STARTING,
0918 ATH10K_SCAN_RUNNING,
0919 ATH10K_SCAN_ABORTING,
0920 };
0921
0922 static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
0923 {
0924 switch (state) {
0925 case ATH10K_SCAN_IDLE:
0926 return "idle";
0927 case ATH10K_SCAN_STARTING:
0928 return "starting";
0929 case ATH10K_SCAN_RUNNING:
0930 return "running";
0931 case ATH10K_SCAN_ABORTING:
0932 return "aborting";
0933 }
0934
0935 return "unknown";
0936 }
0937
0938 enum ath10k_tx_pause_reason {
0939 ATH10K_TX_PAUSE_Q_FULL,
0940 ATH10K_TX_PAUSE_MAX,
0941 };
0942
0943 struct ath10k_fw_file {
0944 const struct firmware *firmware;
0945
0946 char fw_version[ETHTOOL_FWVERS_LEN];
0947
0948 DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
0949
0950 enum ath10k_fw_wmi_op_version wmi_op_version;
0951 enum ath10k_fw_htt_op_version htt_op_version;
0952
0953 const void *firmware_data;
0954 size_t firmware_len;
0955
0956 const void *otp_data;
0957 size_t otp_len;
0958
0959 const void *codeswap_data;
0960 size_t codeswap_len;
0961
0962
0963
0964
0965
0966
0967
0968
0969 struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info;
0970 };
0971
0972 struct ath10k_fw_components {
0973 const struct firmware *board;
0974 const void *board_data;
0975 size_t board_len;
0976 const struct firmware *ext_board;
0977 const void *ext_board_data;
0978 size_t ext_board_len;
0979
0980 struct ath10k_fw_file fw_file;
0981 };
0982
0983 struct ath10k_per_peer_tx_stats {
0984 u32 succ_bytes;
0985 u32 retry_bytes;
0986 u32 failed_bytes;
0987 u8 ratecode;
0988 u8 flags;
0989 u16 peer_id;
0990 u16 succ_pkts;
0991 u16 retry_pkts;
0992 u16 failed_pkts;
0993 u16 duration;
0994 u32 reserved1;
0995 u32 reserved2;
0996 };
0997
0998 enum ath10k_dev_type {
0999 ATH10K_DEV_TYPE_LL,
1000 ATH10K_DEV_TYPE_HL,
1001 };
1002
1003 struct ath10k_bus_params {
1004 u32 chip_id;
1005 enum ath10k_dev_type dev_type;
1006 bool link_can_suspend;
1007 bool hl_msdu_ids;
1008 };
1009
1010 struct ath10k {
1011 struct ath_common ath_common;
1012 struct ieee80211_hw *hw;
1013 struct ieee80211_ops *ops;
1014 struct device *dev;
1015 struct msa_region {
1016 dma_addr_t paddr;
1017 u32 mem_size;
1018 void *vaddr;
1019 } msa;
1020 u8 mac_addr[ETH_ALEN];
1021
1022 enum ath10k_hw_rev hw_rev;
1023 u16 dev_id;
1024 u32 chip_id;
1025 u32 target_version;
1026 u8 fw_version_major;
1027 u32 fw_version_minor;
1028 u16 fw_version_release;
1029 u16 fw_version_build;
1030 u32 fw_stats_req_mask;
1031 u32 phy_capability;
1032 u32 hw_min_tx_power;
1033 u32 hw_max_tx_power;
1034 u32 hw_eeprom_rd;
1035 u32 ht_cap_info;
1036 u32 vht_cap_info;
1037 u32 vht_supp_mcs;
1038 u32 num_rf_chains;
1039 u32 max_spatial_stream;
1040
1041 u32 low_2ghz_chan;
1042 u32 high_2ghz_chan;
1043 u32 low_5ghz_chan;
1044 u32 high_5ghz_chan;
1045 bool ani_enabled;
1046 u32 sys_cap_info;
1047
1048
1049 bool hw_rfkill_on;
1050
1051
1052 u8 ps_state_enable;
1053
1054 bool nlo_enabled;
1055 bool p2p;
1056
1057 struct {
1058 enum ath10k_bus bus;
1059 const struct ath10k_hif_ops *ops;
1060 } hif;
1061
1062 struct completion target_suspend;
1063 struct completion driver_recovery;
1064
1065 const struct ath10k_hw_regs *regs;
1066 const struct ath10k_hw_ce_regs *hw_ce_regs;
1067 const struct ath10k_hw_values *hw_values;
1068 struct ath10k_bmi bmi;
1069 struct ath10k_wmi wmi;
1070 struct ath10k_htc htc;
1071 struct ath10k_htt htt;
1072
1073 struct ath10k_hw_params hw_params;
1074
1075
1076 struct ath10k_fw_components normal_mode_fw;
1077
1078
1079
1080
1081 const struct ath10k_fw_components *running_fw;
1082
1083 const struct firmware *pre_cal_file;
1084 const struct firmware *cal_file;
1085
1086 struct {
1087 u32 vendor;
1088 u32 device;
1089 u32 subsystem_vendor;
1090 u32 subsystem_device;
1091
1092 bool bmi_ids_valid;
1093 bool qmi_ids_valid;
1094 u32 qmi_board_id;
1095 u32 qmi_chip_id;
1096 u8 bmi_board_id;
1097 u8 bmi_eboard_id;
1098 u8 bmi_chip_id;
1099 bool ext_bid_supported;
1100
1101 char bdf_ext[ATH10K_SMBIOS_BDF_EXT_STR_LENGTH];
1102 } id;
1103
1104 int fw_api;
1105 int bd_api;
1106 enum ath10k_cal_mode cal_mode;
1107
1108 struct {
1109 struct completion started;
1110 struct completion completed;
1111 struct completion on_channel;
1112 struct delayed_work timeout;
1113 enum ath10k_scan_state state;
1114 bool is_roc;
1115 int vdev_id;
1116 int roc_freq;
1117 bool roc_notify;
1118 } scan;
1119
1120 struct {
1121 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
1122 } mac;
1123
1124
1125 struct ieee80211_channel *rx_channel;
1126
1127
1128 struct ieee80211_channel *scan_channel;
1129
1130
1131 struct cfg80211_chan_def chandef;
1132
1133
1134 struct ieee80211_channel *tgt_oper_chan;
1135
1136 unsigned long long free_vdev_map;
1137 struct ath10k_vif *monitor_arvif;
1138 bool monitor;
1139 int monitor_vdev_id;
1140 bool monitor_started;
1141 unsigned int filter_flags;
1142 unsigned long dev_flags;
1143 bool dfs_block_radar_events;
1144
1145
1146 bool radar_enabled;
1147 int num_started_vdevs;
1148
1149
1150 u8 cfg_tx_chainmask;
1151 u8 cfg_rx_chainmask;
1152
1153 struct completion install_key_done;
1154
1155 int last_wmi_vdev_start_status;
1156 struct completion vdev_setup_done;
1157 struct completion vdev_delete_done;
1158 struct completion peer_stats_info_complete;
1159
1160 struct workqueue_struct *workqueue;
1161
1162 struct workqueue_struct *workqueue_aux;
1163 struct workqueue_struct *workqueue_tx_complete;
1164
1165 struct mutex conf_mutex;
1166
1167
1168 struct mutex dump_mutex;
1169
1170
1171 spinlock_t data_lock;
1172
1173 struct list_head arvifs;
1174 struct list_head peers;
1175 struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS];
1176 wait_queue_head_t peer_mapping_wq;
1177
1178
1179 int num_peers;
1180 int num_stations;
1181
1182 int max_num_peers;
1183 int max_num_stations;
1184 int max_num_vdevs;
1185 int max_num_tdls_vdevs;
1186 int num_active_peers;
1187 int num_tids;
1188
1189 struct work_struct svc_rdy_work;
1190 struct sk_buff *svc_rdy_skb;
1191
1192 struct work_struct offchan_tx_work;
1193 struct sk_buff_head offchan_tx_queue;
1194 struct completion offchan_tx_completed;
1195 struct sk_buff *offchan_tx_skb;
1196
1197 struct work_struct wmi_mgmt_tx_work;
1198 struct sk_buff_head wmi_mgmt_tx_queue;
1199
1200 enum ath10k_state state;
1201
1202 struct work_struct register_work;
1203 struct work_struct restart_work;
1204 struct work_struct bundle_tx_work;
1205 struct work_struct tx_complete_work;
1206
1207
1208
1209
1210 u32 survey_last_rx_clear_count;
1211 u32 survey_last_cycle_count;
1212 struct survey_info survey[ATH10K_NUM_CHANS];
1213
1214
1215
1216
1217
1218
1219
1220 bool ch_info_can_report_survey;
1221 struct completion bss_survey_done;
1222
1223 struct dfs_pattern_detector *dfs_detector;
1224
1225 unsigned long tx_paused;
1226
1227 #ifdef CONFIG_ATH10K_DEBUGFS
1228 struct ath10k_debug debug;
1229 struct {
1230
1231 struct rchan *rfs_chan_spec_scan;
1232
1233
1234 enum ath10k_spectral_mode mode;
1235 struct ath10k_spec_scan config;
1236 } spectral;
1237 #endif
1238
1239 u32 pktlog_filter;
1240
1241 #ifdef CONFIG_DEV_COREDUMP
1242 struct {
1243 struct ath10k_fw_crash_data *fw_crash_data;
1244 } coredump;
1245 #endif
1246
1247 struct {
1248
1249 struct ath10k_fw_components utf_mode_fw;
1250
1251
1252 bool utf_monitor;
1253 } testmode;
1254
1255 struct {
1256
1257 u32 rx_crc_err_drop;
1258 u32 fw_crash_counter;
1259 u32 fw_warm_reset_counter;
1260 u32 fw_cold_reset_counter;
1261 } stats;
1262
1263 struct ath10k_thermal thermal;
1264 struct ath10k_wow wow;
1265 struct ath10k_per_peer_tx_stats peer_tx_stats;
1266
1267
1268 struct net_device napi_dev;
1269 struct napi_struct napi;
1270
1271 struct work_struct set_coverage_class_work;
1272
1273 struct {
1274
1275 s16 coverage_class;
1276
1277 u32 reg_phyclk;
1278 u32 reg_slottime_conf;
1279 u32 reg_slottime_orig;
1280 u32 reg_ack_cts_timeout_conf;
1281 u32 reg_ack_cts_timeout_orig;
1282 } fw_coverage;
1283
1284 u32 ampdu_reference;
1285
1286 const u8 *wmi_key_cipher;
1287 void *ce_priv;
1288
1289 u32 sta_tid_stats_mask;
1290
1291
1292 enum ath10k_radar_confirmation_state radar_conf_state;
1293 struct ath10k_radar_found_info last_radar_info;
1294 struct work_struct radar_confirmation_work;
1295 struct ath10k_bus_params bus_param;
1296 struct completion peer_delete_done;
1297
1298 bool coex_support;
1299 int coex_gpio_pin;
1300
1301 s32 tx_power_2g_limit;
1302 s32 tx_power_5g_limit;
1303
1304
1305 u8 drv_priv[] __aligned(sizeof(void *));
1306 };
1307
1308 static inline bool ath10k_peer_stats_enabled(struct ath10k *ar)
1309 {
1310 if (test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) &&
1311 test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map))
1312 return true;
1313
1314 return false;
1315 }
1316
1317 extern unsigned int ath10k_frame_mode;
1318 extern unsigned long ath10k_coredump_mask;
1319
1320 void ath10k_core_napi_sync_disable(struct ath10k *ar);
1321 void ath10k_core_napi_enable(struct ath10k *ar);
1322 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
1323 enum ath10k_bus bus,
1324 enum ath10k_hw_rev hw_rev,
1325 const struct ath10k_hif_ops *hif_ops);
1326 void ath10k_core_destroy(struct ath10k *ar);
1327 void ath10k_core_get_fw_features_str(struct ath10k *ar,
1328 char *buf,
1329 size_t max_len);
1330 int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
1331 struct ath10k_fw_file *fw_file);
1332
1333 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
1334 const struct ath10k_fw_components *fw_components);
1335 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
1336 void ath10k_core_stop(struct ath10k *ar);
1337 void ath10k_core_start_recovery(struct ath10k *ar);
1338 int ath10k_core_register(struct ath10k *ar,
1339 const struct ath10k_bus_params *bus_params);
1340 void ath10k_core_unregister(struct ath10k *ar);
1341 int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type);
1342 int ath10k_core_check_dt(struct ath10k *ar);
1343 void ath10k_core_free_board_files(struct ath10k *ar);
1344
1345 #endif