ath/ath10k/ce.h

0001 /* SPDX-License-Identifier: ISC */
0002 /*
0003  * Copyright (c) 2005-2011 Atheros Communications Inc.
0004  * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
0005  * Copyright (c) 2018 The Linux Foundation. All rights reserved.
0006  */
0007
0008 #ifndef _CE_H_
0009 #define _CE_H_
0010
0011 #include "hif.h"
0012
0013 #define CE_HTT_H2T_MSG_SRC_NENTRIES 8192
0014
0015 /* Descriptor rings must be aligned to this boundary */
0016 #define CE_DESC_RING_ALIGN  8
0017 #define CE_SEND_FLAG_GATHER 0x00010000
0018
0019 /*
0020  * Copy Engine support: low-level Target-side Copy Engine API.
0021  * This is a hardware access layer used by code that understands
0022  * how to use copy engines.
0023  */
0024
0025 struct ath10k_ce_pipe;
0026
0027 #define CE_DESC_FLAGS_GATHER         (1 << 0)
0028 #define CE_DESC_FLAGS_BYTE_SWAP      (1 << 1)
0029 #define CE_WCN3990_DESC_FLAGS_GATHER BIT(31)
0030
0031 #define CE_DESC_ADDR_MASK       GENMASK_ULL(34, 0)
0032 #define CE_DESC_ADDR_HI_MASK        GENMASK(4, 0)
0033
0034 /* Following desc flags are used in QCA99X0 */
0035 #define CE_DESC_FLAGS_HOST_INT_DIS  (1 << 2)
0036 #define CE_DESC_FLAGS_TGT_INT_DIS   (1 << 3)
0037
0038 #define CE_DESC_FLAGS_META_DATA_MASK ar->hw_values->ce_desc_meta_data_mask
0039 #define CE_DESC_FLAGS_META_DATA_LSB  ar->hw_values->ce_desc_meta_data_lsb
0040
0041 #define CE_DDR_RRI_MASK         GENMASK(15, 0)
0042 #define CE_DDR_DRRI_SHIFT       16
0043
0044 struct ce_desc {
0045     __le32 addr;
0046     __le16 nbytes;
0047     __le16 flags; /* %CE_DESC_FLAGS_ */
0048 };
0049
0050 struct ce_desc_64 {
0051     __le64 addr;
0052     __le16 nbytes; /* length in register map */
0053     __le16 flags; /* fw_metadata_high */
0054     __le32 toeplitz_hash_result;
0055 };
0056
0057 #define CE_DESC_SIZE sizeof(struct ce_desc)
0058 #define CE_DESC_SIZE_64 sizeof(struct ce_desc_64)
0059
0060 struct ath10k_ce_ring {
0061     /* Number of entries in this ring; must be power of 2 */
0062     unsigned int nentries;
0063     unsigned int nentries_mask;
0064
0065     /*
0066      * For dest ring, this is the next index to be processed
0067      * by software after it was/is received into.
0068      *
0069      * For src ring, this is the last descriptor that was sent
0070      * and completion processed by software.
0071      *
0072      * Regardless of src or dest ring, this is an invariant
0073      * (modulo ring size):
0074      *     write index >= read index >= sw_index
0075      */
0076     unsigned int sw_index;
0077     /* cached copy */
0078     unsigned int write_index;
0079     /*
0080      * For src ring, this is the next index not yet processed by HW.
0081      * This is a cached copy of the real HW index (read index), used
0082      * for avoiding reading the HW index register more often than
0083      * necessary.
0084      * This extends the invariant:
0085      *     write index >= read index >= hw_index >= sw_index
0086      *
0087      * For dest ring, this is currently unused.
0088      */
0089     /* cached copy */
0090     unsigned int hw_index;
0091
0092     /* Start of DMA-coherent area reserved for descriptors */
0093     /* Host address space */
0094     void *base_addr_owner_space_unaligned;
0095     /* CE address space */
0096     dma_addr_t base_addr_ce_space_unaligned;
0097
0098     /*
0099      * Actual start of descriptors.
0100      * Aligned to descriptor-size boundary.
0101      * Points into reserved DMA-coherent area, above.
0102      */
0103     /* Host address space */
0104     void *base_addr_owner_space;
0105
0106     /* CE address space */
0107     dma_addr_t base_addr_ce_space;
0108
0109     char *shadow_base_unaligned;
0110     struct ce_desc_64 *shadow_base;
0111
0112     /* keep last */
0113     void *per_transfer_context[];
0114 };
0115
0116 struct ath10k_ce_pipe {
0117     struct ath10k *ar;
0118     unsigned int id;
0119
0120     unsigned int attr_flags;
0121
0122     u32 ctrl_addr;
0123
0124     void (*send_cb)(struct ath10k_ce_pipe *);
0125     void (*recv_cb)(struct ath10k_ce_pipe *);
0126
0127     unsigned int src_sz_max;
0128     struct ath10k_ce_ring *src_ring;
0129     struct ath10k_ce_ring *dest_ring;
0130     const struct ath10k_ce_ops *ops;
0131 };
0132
0133 /* Copy Engine settable attributes */
0134 struct ce_attr;
0135
0136 struct ath10k_bus_ops {
0137     u32 (*read32)(struct ath10k *ar, u32 offset);
0138     void (*write32)(struct ath10k *ar, u32 offset, u32 value);
0139     int (*get_num_banks)(struct ath10k *ar);
0140 };
0141
0142 static inline struct ath10k_ce *ath10k_ce_priv(struct ath10k *ar)
0143 {
0144     return (struct ath10k_ce *)ar->ce_priv;
0145 }
0146
0147 struct ath10k_ce {
0148     /* protects CE info */
0149     spinlock_t ce_lock;
0150     const struct ath10k_bus_ops *bus_ops;
0151     struct ath10k_ce_pipe ce_states[CE_COUNT_MAX];
0152     u32 *vaddr_rri;
0153     dma_addr_t paddr_rri;
0154 };
0155
0156 /*==================Send====================*/
0157
0158 /* ath10k_ce_send flags */
0159 #define CE_SEND_FLAG_BYTE_SWAP 1
0160
0161 /*
0162  * Queue a source buffer to be sent to an anonymous destination buffer.
0163  *   ce         - which copy engine to use
0164  *   buffer          - address of buffer
0165  *   nbytes          - number of bytes to send
0166  *   transfer_id     - arbitrary ID; reflected to destination
0167  *   flags           - CE_SEND_FLAG_* values
0168  * Returns 0 on success; otherwise an error status.
0169  *
0170  * Note: If no flags are specified, use CE's default data swap mode.
0171  *
0172  * Implementation note: pushes 1 buffer to Source ring
0173  */
0174 int ath10k_ce_send(struct ath10k_ce_pipe *ce_state,
0175            void *per_transfer_send_context,
0176            dma_addr_t buffer,
0177            unsigned int nbytes,
0178            /* 14 bits */
0179            unsigned int transfer_id,
0180            unsigned int flags);
0181
0182 int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
0183               void *per_transfer_context,
0184               dma_addr_t buffer,
0185               unsigned int nbytes,
0186               unsigned int transfer_id,
0187               unsigned int flags);
0188
0189 void __ath10k_ce_send_revert(struct ath10k_ce_pipe *pipe);
0190
0191 int ath10k_ce_num_free_src_entries(struct ath10k_ce_pipe *pipe);
0192
0193 /*==================Recv=======================*/
0194
0195 int __ath10k_ce_rx_num_free_bufs(struct ath10k_ce_pipe *pipe);
0196 int ath10k_ce_rx_post_buf(struct ath10k_ce_pipe *pipe, void *ctx,
0197               dma_addr_t paddr);
0198 void ath10k_ce_rx_update_write_idx(struct ath10k_ce_pipe *pipe, u32 nentries);
0199
0200 /* recv flags */
0201 /* Data is byte-swapped */
0202 #define CE_RECV_FLAG_SWAPPED    1
0203
0204 /*
0205  * Supply data for the next completed unprocessed receive descriptor.
0206  * Pops buffer from Dest ring.
0207  */
0208 int ath10k_ce_completed_recv_next(struct ath10k_ce_pipe *ce_state,
0209                   void **per_transfer_contextp,
0210                   unsigned int *nbytesp);
0211 /*
0212  * Supply data for the next completed unprocessed send descriptor.
0213  * Pops 1 completed send buffer from Source ring.
0214  */
0215 int ath10k_ce_completed_send_next(struct ath10k_ce_pipe *ce_state,
0216                   void **per_transfer_contextp);
0217
0218 int ath10k_ce_completed_send_next_nolock(struct ath10k_ce_pipe *ce_state,
0219                      void **per_transfer_contextp);
0220
0221 /*==================CE Engine Initialization=======================*/
0222
0223 int ath10k_ce_init_pipe(struct ath10k *ar, unsigned int ce_id,
0224             const struct ce_attr *attr);
0225 void ath10k_ce_deinit_pipe(struct ath10k *ar, unsigned int ce_id);
0226 int ath10k_ce_alloc_pipe(struct ath10k *ar, int ce_id,
0227              const struct ce_attr *attr);
0228 void ath10k_ce_free_pipe(struct ath10k *ar, int ce_id);
0229
0230 /*==================CE Engine Shutdown=======================*/
0231 /*
0232  * Support clean shutdown by allowing the caller to revoke
0233  * receive buffers.  Target DMA must be stopped before using
0234  * this API.
0235  */
0236 int ath10k_ce_revoke_recv_next(struct ath10k_ce_pipe *ce_state,
0237                    void **per_transfer_contextp,
0238                    dma_addr_t *bufferp);
0239
0240 int ath10k_ce_completed_recv_next_nolock(struct ath10k_ce_pipe *ce_state,
0241                      void **per_transfer_contextp,
0242                      unsigned int *nbytesp);
0243
0244 /*
0245  * Support clean shutdown by allowing the caller to cancel
0246  * pending sends.  Target DMA must be stopped before using
0247  * this API.
0248  */
0249 int ath10k_ce_cancel_send_next(struct ath10k_ce_pipe *ce_state,
0250                    void **per_transfer_contextp,
0251                    dma_addr_t *bufferp,
0252                    unsigned int *nbytesp,
0253                    unsigned int *transfer_idp);
0254
0255 /*==================CE Interrupt Handlers====================*/
0256 void ath10k_ce_per_engine_service_any(struct ath10k *ar);
0257 void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id);
0258 void ath10k_ce_disable_interrupt(struct ath10k *ar, int ce_id);
0259 void ath10k_ce_disable_interrupts(struct ath10k *ar);
0260 void ath10k_ce_enable_interrupt(struct ath10k *ar, int ce_id);
0261 void ath10k_ce_enable_interrupts(struct ath10k *ar);
0262 void ath10k_ce_dump_registers(struct ath10k *ar,
0263                   struct ath10k_fw_crash_data *crash_data);
0264
0265 void ath10k_ce_alloc_rri(struct ath10k *ar);
0266 void ath10k_ce_free_rri(struct ath10k *ar);
0267
0268 /* ce_attr.flags values */
0269 /* Use NonSnooping PCIe accesses? */
0270 #define CE_ATTR_NO_SNOOP        BIT(0)
0271
0272 /* Byte swap data words */
0273 #define CE_ATTR_BYTE_SWAP_DATA      BIT(1)
0274
0275 /* Swizzle descriptors? */
0276 #define CE_ATTR_SWIZZLE_DESCRIPTORS BIT(2)
0277
0278 /* no interrupt on copy completion */
0279 #define CE_ATTR_DIS_INTR        BIT(3)
0280
0281 /* no interrupt, only polling */
0282 #define CE_ATTR_POLL            BIT(4)
0283
0284 /* Attributes of an instance of a Copy Engine */
0285 struct ce_attr {
0286     /* CE_ATTR_* values */
0287     unsigned int flags;
0288
0289     /* #entries in source ring - Must be a power of 2 */
0290     unsigned int src_nentries;
0291
0292     /*
0293      * Max source send size for this CE.
0294      * This is also the minimum size of a destination buffer.
0295      */
0296     unsigned int src_sz_max;
0297
0298     /* #entries in destination ring - Must be a power of 2 */
0299     unsigned int dest_nentries;
0300
0301     void (*send_cb)(struct ath10k_ce_pipe *);
0302     void (*recv_cb)(struct ath10k_ce_pipe *);
0303 };
0304
0305 struct ath10k_ce_ops {
0306     struct ath10k_ce_ring *(*ce_alloc_src_ring)(struct ath10k *ar,
0307                             u32 ce_id,
0308                             const struct ce_attr *attr);
0309     struct ath10k_ce_ring *(*ce_alloc_dst_ring)(struct ath10k *ar,
0310                             u32 ce_id,
0311                             const struct ce_attr *attr);
0312     int (*ce_rx_post_buf)(struct ath10k_ce_pipe *pipe, void *ctx,
0313                   dma_addr_t paddr);
0314     int (*ce_completed_recv_next_nolock)(struct ath10k_ce_pipe *ce_state,
0315                          void **per_transfer_contextp,
0316                          u32 *nbytesp);
0317     int (*ce_revoke_recv_next)(struct ath10k_ce_pipe *ce_state,
0318                    void **per_transfer_contextp,
0319                    dma_addr_t *nbytesp);
0320     void (*ce_extract_desc_data)(struct ath10k *ar,
0321                      struct ath10k_ce_ring *src_ring,
0322                      u32 sw_index, dma_addr_t *bufferp,
0323                      u32 *nbytesp, u32 *transfer_idp);
0324     void (*ce_free_pipe)(struct ath10k *ar, int ce_id);
0325     int (*ce_send_nolock)(struct ath10k_ce_pipe *pipe,
0326                   void *per_transfer_context,
0327                   dma_addr_t buffer, u32 nbytes,
0328                   u32 transfer_id, u32 flags);
0329     void (*ce_set_src_ring_base_addr_hi)(struct ath10k *ar,
0330                          u32 ce_ctrl_addr,
0331                          u64 addr);
0332     void (*ce_set_dest_ring_base_addr_hi)(struct ath10k *ar,
0333                           u32 ce_ctrl_addr,
0334                           u64 addr);
0335     int (*ce_completed_send_next_nolock)(struct ath10k_ce_pipe *ce_state,
0336                          void **per_transfer_contextp);
0337 };
0338
0339 static inline u32 ath10k_ce_base_address(struct ath10k *ar, unsigned int ce_id)
0340 {
0341     return CE0_BASE_ADDRESS + (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS) * ce_id;
0342 }
0343
0344 #define COPY_ENGINE_ID(COPY_ENGINE_BASE_ADDRESS) (((COPY_ENGINE_BASE_ADDRESS) \
0345         - CE0_BASE_ADDRESS) / (CE1_BASE_ADDRESS - CE0_BASE_ADDRESS))
0346
0347 #define CE_SRC_RING_TO_DESC(baddr, idx) \
0348     (&(((struct ce_desc *)baddr)[idx]))
0349
0350 #define CE_DEST_RING_TO_DESC(baddr, idx) \
0351     (&(((struct ce_desc *)baddr)[idx]))
0352
0353 #define CE_SRC_RING_TO_DESC_64(baddr, idx) \
0354     (&(((struct ce_desc_64 *)baddr)[idx]))
0355
0356 #define CE_DEST_RING_TO_DESC_64(baddr, idx) \
0357     (&(((struct ce_desc_64 *)baddr)[idx]))
0358
0359 /* Ring arithmetic (modulus number of entries in ring, which is a pwr of 2). */
0360 #define CE_RING_DELTA(nentries_mask, fromidx, toidx) \
0361     (((int)(toidx) - (int)(fromidx)) & (nentries_mask))
0362
0363 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
0364 #define CE_RING_IDX_ADD(nentries_mask, idx, num) \
0365         (((idx) + (num)) & (nentries_mask))
0366
0367 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB \
0368                 ar->regs->ce_wrap_intr_sum_host_msi_lsb
0369 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK \
0370                 ar->regs->ce_wrap_intr_sum_host_msi_mask
0371 #define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(x) \
0372     (((x) & CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK) >> \
0373         CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
0374 #define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS            0x0000
0375
0376 static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
0377 {
0378     struct ath10k_ce *ce = ath10k_ce_priv(ar);
0379
0380     return CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET(
0381         ce->bus_ops->read32((ar), CE_WRAPPER_BASE_ADDRESS +
0382         CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS));
0383 }
0384
0385 /* Host software's Copy Engine configuration. */
0386 #define CE_ATTR_FLAGS 0
0387
0388 /*
0389  * Configuration information for a Copy Engine pipe.
0390  * Passed from Host to Target during startup (one per CE).
0391  *
0392  * NOTE: Structure is shared between Host software and Target firmware!
0393  */
0394 struct ce_pipe_config {
0395     __le32 pipenum;
0396     __le32 pipedir;
0397     __le32 nentries;
0398     __le32 nbytes_max;
0399     __le32 flags;
0400     __le32 reserved;
0401 };
0402
0403 /*
0404  * Directions for interconnect pipe configuration.
0405  * These definitions may be used during configuration and are shared
0406  * between Host and Target.
0407  *
0408  * Pipe Directions are relative to the Host, so PIPEDIR_IN means
0409  * "coming IN over air through Target to Host" as with a WiFi Rx operation.
0410  * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
0411  * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
0412  * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
0413  * over the interconnect.
0414  */
0415 #define PIPEDIR_NONE    0
0416 #define PIPEDIR_IN      1  /* Target-->Host, WiFi Rx direction */
0417 #define PIPEDIR_OUT     2  /* Host->Target, WiFi Tx direction */
0418 #define PIPEDIR_INOUT   3  /* bidirectional */
0419
0420 /* Establish a mapping between a service/direction and a pipe. */
0421 struct ce_service_to_pipe {
0422     __le32 service_id;
0423     __le32 pipedir;
0424     __le32 pipenum;
0425 };
0426
0427 #endif /* _CE_H_ */