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0007 #ifndef _AHB_H_
0008 #define _AHB_H_
0009
0010 #include <linux/platform_device.h>
0011
0012 struct ath10k_ahb {
0013 struct platform_device *pdev;
0014 void __iomem *mem;
0015 unsigned long mem_len;
0016 void __iomem *gcc_mem;
0017 void __iomem *tcsr_mem;
0018
0019 int irq;
0020
0021 struct clk *cmd_clk;
0022 struct clk *ref_clk;
0023 struct clk *rtc_clk;
0024
0025 struct reset_control *core_cold_rst;
0026 struct reset_control *radio_cold_rst;
0027 struct reset_control *radio_warm_rst;
0028 struct reset_control *radio_srif_rst;
0029 struct reset_control *cpu_init_rst;
0030 };
0031
0032 #ifdef CONFIG_ATH10K_AHB
0033
0034 #define ATH10K_GCC_REG_BASE 0x1800000
0035 #define ATH10K_GCC_REG_SIZE 0x60000
0036
0037 #define ATH10K_TCSR_REG_BASE 0x1900000
0038 #define ATH10K_TCSR_REG_SIZE 0x80000
0039
0040 #define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020
0041 #define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014
0042
0043 #define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030
0044
0045 #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000
0046 #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004
0047 #define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK BIT(25)
0048
0049 #define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000
0050 #define ATH10K_AHB_TCSR_WCSS1_HALTREQ 0x52010
0051 #define ATH10K_AHB_TCSR_WCSS0_HALTACK 0x52004
0052 #define ATH10K_AHB_TCSR_WCSS1_HALTACK 0x52014
0053
0054 #define ATH10K_AHB_AXI_BUS_HALT_TIMEOUT 10
0055 #define AHB_AXI_BUS_HALT_REQ 1
0056 #define AHB_AXI_BUS_HALT_ACK 1
0057
0058 #define ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK 1
0059
0060 int ath10k_ahb_init(void);
0061 void ath10k_ahb_exit(void);
0062
0063 #else
0064
0065 static inline int ath10k_ahb_init(void)
0066 {
0067 return 0;
0068 }
0069
0070 static inline void ath10k_ahb_exit(void)
0071 {
0072 }
0073
0074 #endif
0075
0076 #endif