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0001 // SPDX-License-Identifier: ISC
0002 /*
0003  * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
0004  * Copyright (c) 2015 The Linux Foundation. All rights reserved.
0005  */
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/of_device.h>
0009 #include <linux/clk.h>
0010 #include <linux/reset.h>
0011 #include "core.h"
0012 #include "debug.h"
0013 #include "pci.h"
0014 #include "ahb.h"
0015 
0016 static const struct of_device_id ath10k_ahb_of_match[] = {
0017     { .compatible = "qcom,ipq4019-wifi",
0018       .data = (void *)ATH10K_HW_QCA4019
0019     },
0020     { }
0021 };
0022 
0023 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match);
0024 
0025 #define QCA4019_SRAM_ADDR      0x000C0000
0026 #define QCA4019_SRAM_LEN       0x00040000 /* 256 kb */
0027 
0028 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
0029 {
0030     return &((struct ath10k_pci *)ar->drv_priv)->ahb[0];
0031 }
0032 
0033 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
0034 {
0035     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0036 
0037     iowrite32(value, ar_ahb->mem + offset);
0038 }
0039 
0040 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)
0041 {
0042     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0043 
0044     return ioread32(ar_ahb->mem + offset);
0045 }
0046 
0047 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)
0048 {
0049     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0050 
0051     return ioread32(ar_ahb->gcc_mem + offset);
0052 }
0053 
0054 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)
0055 {
0056     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0057 
0058     iowrite32(value, ar_ahb->tcsr_mem + offset);
0059 }
0060 
0061 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)
0062 {
0063     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0064 
0065     return ioread32(ar_ahb->tcsr_mem + offset);
0066 }
0067 
0068 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)
0069 {
0070     return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
0071 }
0072 
0073 static int ath10k_ahb_get_num_banks(struct ath10k *ar)
0074 {
0075     if (ar->hw_rev == ATH10K_HW_QCA4019)
0076         return 1;
0077 
0078     ath10k_warn(ar, "unknown number of banks, assuming 1\n");
0079     return 1;
0080 }
0081 
0082 static int ath10k_ahb_clock_init(struct ath10k *ar)
0083 {
0084     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0085     struct device *dev;
0086 
0087     dev = &ar_ahb->pdev->dev;
0088 
0089     ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd");
0090     if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) {
0091         ath10k_err(ar, "failed to get cmd clk: %ld\n",
0092                PTR_ERR(ar_ahb->cmd_clk));
0093         return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV;
0094     }
0095 
0096     ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref");
0097     if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) {
0098         ath10k_err(ar, "failed to get ref clk: %ld\n",
0099                PTR_ERR(ar_ahb->ref_clk));
0100         return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV;
0101     }
0102 
0103     ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc");
0104     if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
0105         ath10k_err(ar, "failed to get rtc clk: %ld\n",
0106                PTR_ERR(ar_ahb->rtc_clk));
0107         return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV;
0108     }
0109 
0110     return 0;
0111 }
0112 
0113 static void ath10k_ahb_clock_deinit(struct ath10k *ar)
0114 {
0115     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0116 
0117     ar_ahb->cmd_clk = NULL;
0118     ar_ahb->ref_clk = NULL;
0119     ar_ahb->rtc_clk = NULL;
0120 }
0121 
0122 static int ath10k_ahb_clock_enable(struct ath10k *ar)
0123 {
0124     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0125     int ret;
0126 
0127     if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) ||
0128         IS_ERR_OR_NULL(ar_ahb->ref_clk) ||
0129         IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
0130         ath10k_err(ar, "clock(s) is/are not initialized\n");
0131         ret = -EIO;
0132         goto out;
0133     }
0134 
0135     ret = clk_prepare_enable(ar_ahb->cmd_clk);
0136     if (ret) {
0137         ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);
0138         goto out;
0139     }
0140 
0141     ret = clk_prepare_enable(ar_ahb->ref_clk);
0142     if (ret) {
0143         ath10k_err(ar, "failed to enable ref clk: %d\n", ret);
0144         goto err_cmd_clk_disable;
0145     }
0146 
0147     ret = clk_prepare_enable(ar_ahb->rtc_clk);
0148     if (ret) {
0149         ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);
0150         goto err_ref_clk_disable;
0151     }
0152 
0153     return 0;
0154 
0155 err_ref_clk_disable:
0156     clk_disable_unprepare(ar_ahb->ref_clk);
0157 
0158 err_cmd_clk_disable:
0159     clk_disable_unprepare(ar_ahb->cmd_clk);
0160 
0161 out:
0162     return ret;
0163 }
0164 
0165 static void ath10k_ahb_clock_disable(struct ath10k *ar)
0166 {
0167     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0168 
0169     clk_disable_unprepare(ar_ahb->cmd_clk);
0170 
0171     clk_disable_unprepare(ar_ahb->ref_clk);
0172 
0173     clk_disable_unprepare(ar_ahb->rtc_clk);
0174 }
0175 
0176 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)
0177 {
0178     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0179     struct device *dev;
0180 
0181     dev = &ar_ahb->pdev->dev;
0182 
0183     ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev,
0184                                  "wifi_core_cold");
0185     if (IS_ERR(ar_ahb->core_cold_rst)) {
0186         ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",
0187                PTR_ERR(ar_ahb->core_cold_rst));
0188         return PTR_ERR(ar_ahb->core_cold_rst);
0189     }
0190 
0191     ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev,
0192                                   "wifi_radio_cold");
0193     if (IS_ERR(ar_ahb->radio_cold_rst)) {
0194         ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",
0195                PTR_ERR(ar_ahb->radio_cold_rst));
0196         return PTR_ERR(ar_ahb->radio_cold_rst);
0197     }
0198 
0199     ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev,
0200                                   "wifi_radio_warm");
0201     if (IS_ERR(ar_ahb->radio_warm_rst)) {
0202         ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",
0203                PTR_ERR(ar_ahb->radio_warm_rst));
0204         return PTR_ERR(ar_ahb->radio_warm_rst);
0205     }
0206 
0207     ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev,
0208                                   "wifi_radio_srif");
0209     if (IS_ERR(ar_ahb->radio_srif_rst)) {
0210         ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",
0211                PTR_ERR(ar_ahb->radio_srif_rst));
0212         return PTR_ERR(ar_ahb->radio_srif_rst);
0213     }
0214 
0215     ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev,
0216                                 "wifi_cpu_init");
0217     if (IS_ERR(ar_ahb->cpu_init_rst)) {
0218         ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",
0219                PTR_ERR(ar_ahb->cpu_init_rst));
0220         return PTR_ERR(ar_ahb->cpu_init_rst);
0221     }
0222 
0223     return 0;
0224 }
0225 
0226 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)
0227 {
0228     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0229 
0230     ar_ahb->core_cold_rst = NULL;
0231     ar_ahb->radio_cold_rst = NULL;
0232     ar_ahb->radio_warm_rst = NULL;
0233     ar_ahb->radio_srif_rst = NULL;
0234     ar_ahb->cpu_init_rst = NULL;
0235 }
0236 
0237 static int ath10k_ahb_release_reset(struct ath10k *ar)
0238 {
0239     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0240     int ret;
0241 
0242     if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
0243         IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
0244         IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
0245         IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
0246         ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
0247         return -EINVAL;
0248     }
0249 
0250     ret = reset_control_deassert(ar_ahb->radio_cold_rst);
0251     if (ret) {
0252         ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
0253         return ret;
0254     }
0255 
0256     ret = reset_control_deassert(ar_ahb->radio_warm_rst);
0257     if (ret) {
0258         ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
0259         return ret;
0260     }
0261 
0262     ret = reset_control_deassert(ar_ahb->radio_srif_rst);
0263     if (ret) {
0264         ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
0265         return ret;
0266     }
0267 
0268     ret = reset_control_deassert(ar_ahb->cpu_init_rst);
0269     if (ret) {
0270         ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
0271         return ret;
0272     }
0273 
0274     return 0;
0275 }
0276 
0277 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg,
0278                     u32 haltack_reg)
0279 {
0280     unsigned long timeout;
0281     u32 val;
0282 
0283     /* Issue halt axi bus request */
0284     val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
0285     val |= AHB_AXI_BUS_HALT_REQ;
0286     ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
0287 
0288     /* Wait for axi bus halted ack */
0289     timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT);
0290     do {
0291         val = ath10k_ahb_tcsr_read32(ar, haltack_reg);
0292         if (val & AHB_AXI_BUS_HALT_ACK)
0293             break;
0294 
0295         mdelay(1);
0296     } while (time_before(jiffies, timeout));
0297 
0298     if (!(val & AHB_AXI_BUS_HALT_ACK)) {
0299         ath10k_err(ar, "failed to halt axi bus: %d\n", val);
0300         return;
0301     }
0302 
0303     ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n");
0304 }
0305 
0306 static void ath10k_ahb_halt_chip(struct ath10k *ar)
0307 {
0308     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0309     u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg;
0310     u32 val;
0311     int ret;
0312 
0313     if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) ||
0314         IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
0315         IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
0316         IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
0317         IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
0318         ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
0319         return;
0320     }
0321 
0322     core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG);
0323 
0324     switch (core_id) {
0325     case 0:
0326         glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG;
0327         haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ;
0328         haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK;
0329         break;
0330     case 1:
0331         glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG;
0332         haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ;
0333         haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK;
0334         break;
0335     default:
0336         ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n",
0337                core_id);
0338         return;
0339     }
0340 
0341     ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg);
0342 
0343     val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
0344     val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
0345     ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
0346 
0347     ret = reset_control_assert(ar_ahb->core_cold_rst);
0348     if (ret)
0349         ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);
0350     msleep(1);
0351 
0352     ret = reset_control_assert(ar_ahb->radio_cold_rst);
0353     if (ret)
0354         ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);
0355     msleep(1);
0356 
0357     ret = reset_control_assert(ar_ahb->radio_warm_rst);
0358     if (ret)
0359         ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);
0360     msleep(1);
0361 
0362     ret = reset_control_assert(ar_ahb->radio_srif_rst);
0363     if (ret)
0364         ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);
0365     msleep(1);
0366 
0367     ret = reset_control_assert(ar_ahb->cpu_init_rst);
0368     if (ret)
0369         ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);
0370     msleep(10);
0371 
0372     /* Clear halt req and core clock disable req before
0373      * deasserting wifi core reset.
0374      */
0375     val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
0376     val &= ~AHB_AXI_BUS_HALT_REQ;
0377     ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
0378 
0379     val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
0380     val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
0381     ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
0382 
0383     ret = reset_control_deassert(ar_ahb->core_cold_rst);
0384     if (ret)
0385         ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);
0386 
0387     ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id);
0388 }
0389 
0390 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg)
0391 {
0392     struct ath10k *ar = arg;
0393 
0394     if (!ath10k_pci_irq_pending(ar))
0395         return IRQ_NONE;
0396 
0397     ath10k_pci_disable_and_clear_legacy_irq(ar);
0398     ath10k_pci_irq_msi_fw_mask(ar);
0399     napi_schedule(&ar->napi);
0400 
0401     return IRQ_HANDLED;
0402 }
0403 
0404 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar)
0405 {
0406     struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
0407     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0408     int ret;
0409 
0410     ret = request_irq(ar_ahb->irq,
0411               ath10k_ahb_interrupt_handler,
0412               IRQF_SHARED, "ath10k_ahb", ar);
0413     if (ret) {
0414         ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
0415                 ar_ahb->irq, ret);
0416         return ret;
0417     }
0418     ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
0419 
0420     return 0;
0421 }
0422 
0423 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar)
0424 {
0425     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0426 
0427     free_irq(ar_ahb->irq, ar);
0428 }
0429 
0430 static void ath10k_ahb_irq_disable(struct ath10k *ar)
0431 {
0432     ath10k_ce_disable_interrupts(ar);
0433     ath10k_pci_disable_and_clear_legacy_irq(ar);
0434 }
0435 
0436 static int ath10k_ahb_resource_init(struct ath10k *ar)
0437 {
0438     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0439     struct platform_device *pdev;
0440     struct resource *res;
0441     int ret;
0442 
0443     pdev = ar_ahb->pdev;
0444 
0445     ar_ahb->mem = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0446     if (IS_ERR(ar_ahb->mem)) {
0447         ath10k_err(ar, "mem ioremap error\n");
0448         ret = PTR_ERR(ar_ahb->mem);
0449         goto out;
0450     }
0451 
0452     ar_ahb->mem_len = resource_size(res);
0453 
0454     ar_ahb->gcc_mem = ioremap(ATH10K_GCC_REG_BASE,
0455                   ATH10K_GCC_REG_SIZE);
0456     if (!ar_ahb->gcc_mem) {
0457         ath10k_err(ar, "gcc mem ioremap error\n");
0458         ret = -ENOMEM;
0459         goto err_mem_unmap;
0460     }
0461 
0462     ar_ahb->tcsr_mem = ioremap(ATH10K_TCSR_REG_BASE,
0463                    ATH10K_TCSR_REG_SIZE);
0464     if (!ar_ahb->tcsr_mem) {
0465         ath10k_err(ar, "tcsr mem ioremap error\n");
0466         ret = -ENOMEM;
0467         goto err_gcc_mem_unmap;
0468     }
0469 
0470     ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
0471     if (ret) {
0472         ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);
0473         goto err_tcsr_mem_unmap;
0474     }
0475 
0476     ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
0477     if (ret) {
0478         ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n",
0479                ret);
0480         goto err_tcsr_mem_unmap;
0481     }
0482 
0483     ret = ath10k_ahb_clock_init(ar);
0484     if (ret)
0485         goto err_tcsr_mem_unmap;
0486 
0487     ret = ath10k_ahb_rst_ctrl_init(ar);
0488     if (ret)
0489         goto err_clock_deinit;
0490 
0491     ar_ahb->irq = platform_get_irq_byname(pdev, "legacy");
0492     if (ar_ahb->irq < 0) {
0493         ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq);
0494         ret = ar_ahb->irq;
0495         goto err_clock_deinit;
0496     }
0497 
0498     ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq);
0499 
0500     ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n",
0501            ar_ahb->mem, ar_ahb->mem_len,
0502            ar_ahb->gcc_mem, ar_ahb->tcsr_mem);
0503     return 0;
0504 
0505 err_clock_deinit:
0506     ath10k_ahb_clock_deinit(ar);
0507 
0508 err_tcsr_mem_unmap:
0509     iounmap(ar_ahb->tcsr_mem);
0510 
0511 err_gcc_mem_unmap:
0512     ar_ahb->tcsr_mem = NULL;
0513     iounmap(ar_ahb->gcc_mem);
0514 
0515 err_mem_unmap:
0516     ar_ahb->gcc_mem = NULL;
0517     devm_iounmap(&pdev->dev, ar_ahb->mem);
0518 
0519 out:
0520     ar_ahb->mem = NULL;
0521     return ret;
0522 }
0523 
0524 static void ath10k_ahb_resource_deinit(struct ath10k *ar)
0525 {
0526     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0527     struct device *dev;
0528 
0529     dev = &ar_ahb->pdev->dev;
0530 
0531     if (ar_ahb->mem)
0532         devm_iounmap(dev, ar_ahb->mem);
0533 
0534     if (ar_ahb->gcc_mem)
0535         iounmap(ar_ahb->gcc_mem);
0536 
0537     if (ar_ahb->tcsr_mem)
0538         iounmap(ar_ahb->tcsr_mem);
0539 
0540     ar_ahb->mem = NULL;
0541     ar_ahb->gcc_mem = NULL;
0542     ar_ahb->tcsr_mem = NULL;
0543 
0544     ath10k_ahb_clock_deinit(ar);
0545     ath10k_ahb_rst_ctrl_deinit(ar);
0546 }
0547 
0548 static int ath10k_ahb_prepare_device(struct ath10k *ar)
0549 {
0550     u32 val;
0551     int ret;
0552 
0553     ret = ath10k_ahb_clock_enable(ar);
0554     if (ret) {
0555         ath10k_err(ar, "failed to enable clocks\n");
0556         return ret;
0557     }
0558 
0559     /* Clock for the target is supplied from outside of target (ie,
0560      * external clock module controlled by the host). Target needs
0561      * to know what frequency target cpu is configured which is needed
0562      * for target internal use. Read target cpu frequency info from
0563      * gcc register and write into target's scratch register where
0564      * target expects this information.
0565      */
0566     val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV);
0567     ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val);
0568 
0569     ret = ath10k_ahb_release_reset(ar);
0570     if (ret)
0571         goto err_clk_disable;
0572 
0573     ath10k_ahb_irq_disable(ar);
0574 
0575     ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
0576 
0577     ret = ath10k_pci_wait_for_target_init(ar);
0578     if (ret)
0579         goto err_halt_chip;
0580 
0581     return 0;
0582 
0583 err_halt_chip:
0584     ath10k_ahb_halt_chip(ar);
0585 
0586 err_clk_disable:
0587     ath10k_ahb_clock_disable(ar);
0588 
0589     return ret;
0590 }
0591 
0592 static int ath10k_ahb_chip_reset(struct ath10k *ar)
0593 {
0594     int ret;
0595 
0596     ath10k_ahb_halt_chip(ar);
0597     ath10k_ahb_clock_disable(ar);
0598 
0599     ret = ath10k_ahb_prepare_device(ar);
0600     if (ret)
0601         return ret;
0602 
0603     return 0;
0604 }
0605 
0606 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar)
0607 {
0608     u32 addr, val;
0609 
0610     addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
0611     val = ath10k_ahb_read32(ar, addr);
0612     val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK;
0613     ath10k_ahb_write32(ar, addr, val);
0614 
0615     return 0;
0616 }
0617 
0618 static int ath10k_ahb_hif_start(struct ath10k *ar)
0619 {
0620     ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n");
0621 
0622     ath10k_core_napi_enable(ar);
0623     ath10k_ce_enable_interrupts(ar);
0624     ath10k_pci_enable_legacy_irq(ar);
0625 
0626     ath10k_pci_rx_post(ar);
0627 
0628     return 0;
0629 }
0630 
0631 static void ath10k_ahb_hif_stop(struct ath10k *ar)
0632 {
0633     struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
0634 
0635     ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n");
0636 
0637     ath10k_ahb_irq_disable(ar);
0638     synchronize_irq(ar_ahb->irq);
0639 
0640     ath10k_core_napi_sync_disable(ar);
0641 
0642     ath10k_pci_flush(ar);
0643 }
0644 
0645 static int ath10k_ahb_hif_power_up(struct ath10k *ar,
0646                    enum ath10k_firmware_mode fw_mode)
0647 {
0648     int ret;
0649 
0650     ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n");
0651 
0652     ret = ath10k_ahb_chip_reset(ar);
0653     if (ret) {
0654         ath10k_err(ar, "failed to reset chip: %d\n", ret);
0655         goto out;
0656     }
0657 
0658     ret = ath10k_pci_init_pipes(ar);
0659     if (ret) {
0660         ath10k_err(ar, "failed to initialize CE: %d\n", ret);
0661         goto out;
0662     }
0663 
0664     ret = ath10k_pci_init_config(ar);
0665     if (ret) {
0666         ath10k_err(ar, "failed to setup init config: %d\n", ret);
0667         goto err_ce_deinit;
0668     }
0669 
0670     ret = ath10k_ahb_wake_target_cpu(ar);
0671     if (ret) {
0672         ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
0673         goto err_ce_deinit;
0674     }
0675 
0676     return 0;
0677 
0678 err_ce_deinit:
0679     ath10k_pci_ce_deinit(ar);
0680 out:
0681     return ret;
0682 }
0683 
0684 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
0685 {
0686     u32 val = 0, region = addr & 0xfffff;
0687 
0688     val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
0689 
0690     if (region >= QCA4019_SRAM_ADDR && region <=
0691         (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) {
0692         /* SRAM contents for QCA4019 can be directly accessed and
0693          * no conversions are required
0694          */
0695         val |= region;
0696     } else {
0697         val |= 0x100000 | region;
0698     }
0699 
0700     return val;
0701 }
0702 
0703 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = {
0704     .tx_sg                  = ath10k_pci_hif_tx_sg,
0705     .diag_read              = ath10k_pci_hif_diag_read,
0706     .diag_write             = ath10k_pci_diag_write_mem,
0707     .exchange_bmi_msg       = ath10k_pci_hif_exchange_bmi_msg,
0708     .start                  = ath10k_ahb_hif_start,
0709     .stop                   = ath10k_ahb_hif_stop,
0710     .map_service_to_pipe    = ath10k_pci_hif_map_service_to_pipe,
0711     .get_default_pipe       = ath10k_pci_hif_get_default_pipe,
0712     .send_complete_check    = ath10k_pci_hif_send_complete_check,
0713     .get_free_queue_number  = ath10k_pci_hif_get_free_queue_number,
0714     .power_up               = ath10k_ahb_hif_power_up,
0715     .power_down             = ath10k_pci_hif_power_down,
0716     .read32                 = ath10k_ahb_read32,
0717     .write32                = ath10k_ahb_write32,
0718 };
0719 
0720 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = {
0721     .read32     = ath10k_ahb_read32,
0722     .write32    = ath10k_ahb_write32,
0723     .get_num_banks  = ath10k_ahb_get_num_banks,
0724 };
0725 
0726 static int ath10k_ahb_probe(struct platform_device *pdev)
0727 {
0728     struct ath10k *ar;
0729     struct ath10k_ahb *ar_ahb;
0730     struct ath10k_pci *ar_pci;
0731     enum ath10k_hw_rev hw_rev;
0732     size_t size;
0733     int ret;
0734     struct ath10k_bus_params bus_params = {};
0735 
0736     hw_rev = (enum ath10k_hw_rev)of_device_get_match_data(&pdev->dev);
0737     if (!hw_rev) {
0738         dev_err(&pdev->dev, "OF data missing\n");
0739         return -EINVAL;
0740     }
0741 
0742     size = sizeof(*ar_pci) + sizeof(*ar_ahb);
0743     ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,
0744                 hw_rev, &ath10k_ahb_hif_ops);
0745     if (!ar) {
0746         dev_err(&pdev->dev, "failed to allocate core\n");
0747         return -ENOMEM;
0748     }
0749 
0750     ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n");
0751 
0752     ar_pci = ath10k_pci_priv(ar);
0753     ar_ahb = ath10k_ahb_priv(ar);
0754 
0755     ar_ahb->pdev = pdev;
0756     platform_set_drvdata(pdev, ar);
0757 
0758     ret = ath10k_ahb_resource_init(ar);
0759     if (ret)
0760         goto err_core_destroy;
0761 
0762     ar->dev_id = 0;
0763     ar_pci->mem = ar_ahb->mem;
0764     ar_pci->mem_len = ar_ahb->mem_len;
0765     ar_pci->ar = ar;
0766     ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops;
0767     ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr;
0768     ar->ce_priv = &ar_pci->ce;
0769 
0770     ret = ath10k_pci_setup_resource(ar);
0771     if (ret) {
0772         ath10k_err(ar, "failed to setup resource: %d\n", ret);
0773         goto err_resource_deinit;
0774     }
0775 
0776     ath10k_pci_init_napi(ar);
0777 
0778     ret = ath10k_ahb_request_irq_legacy(ar);
0779     if (ret)
0780         goto err_free_pipes;
0781 
0782     ret = ath10k_ahb_prepare_device(ar);
0783     if (ret)
0784         goto err_free_irq;
0785 
0786     ath10k_pci_ce_deinit(ar);
0787 
0788     bus_params.dev_type = ATH10K_DEV_TYPE_LL;
0789     bus_params.chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
0790     if (bus_params.chip_id == 0xffffffff) {
0791         ath10k_err(ar, "failed to get chip id\n");
0792         ret = -ENODEV;
0793         goto err_halt_device;
0794     }
0795 
0796     ret = ath10k_core_register(ar, &bus_params);
0797     if (ret) {
0798         ath10k_err(ar, "failed to register driver core: %d\n", ret);
0799         goto err_halt_device;
0800     }
0801 
0802     return 0;
0803 
0804 err_halt_device:
0805     ath10k_ahb_halt_chip(ar);
0806     ath10k_ahb_clock_disable(ar);
0807 
0808 err_free_irq:
0809     ath10k_ahb_release_irq_legacy(ar);
0810 
0811 err_free_pipes:
0812     ath10k_pci_release_resource(ar);
0813 
0814 err_resource_deinit:
0815     ath10k_ahb_resource_deinit(ar);
0816 
0817 err_core_destroy:
0818     ath10k_core_destroy(ar);
0819     platform_set_drvdata(pdev, NULL);
0820 
0821     return ret;
0822 }
0823 
0824 static int ath10k_ahb_remove(struct platform_device *pdev)
0825 {
0826     struct ath10k *ar = platform_get_drvdata(pdev);
0827     struct ath10k_ahb *ar_ahb;
0828 
0829     if (!ar)
0830         return -EINVAL;
0831 
0832     ar_ahb = ath10k_ahb_priv(ar);
0833 
0834     if (!ar_ahb)
0835         return -EINVAL;
0836 
0837     ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");
0838 
0839     ath10k_core_unregister(ar);
0840     ath10k_ahb_irq_disable(ar);
0841     ath10k_ahb_release_irq_legacy(ar);
0842     ath10k_pci_release_resource(ar);
0843     ath10k_ahb_halt_chip(ar);
0844     ath10k_ahb_clock_disable(ar);
0845     ath10k_ahb_resource_deinit(ar);
0846     ath10k_core_destroy(ar);
0847 
0848     platform_set_drvdata(pdev, NULL);
0849 
0850     return 0;
0851 }
0852 
0853 static struct platform_driver ath10k_ahb_driver = {
0854     .driver         = {
0855         .name   = "ath10k_ahb",
0856         .of_match_table = ath10k_ahb_of_match,
0857     },
0858     .probe  = ath10k_ahb_probe,
0859     .remove = ath10k_ahb_remove,
0860 };
0861 
0862 int ath10k_ahb_init(void)
0863 {
0864     int ret;
0865 
0866     ret = platform_driver_register(&ath10k_ahb_driver);
0867     if (ret)
0868         printk(KERN_ERR "failed to register ath10k ahb driver: %d\n",
0869                ret);
0870     return ret;
0871 }
0872 
0873 void ath10k_ahb_exit(void)
0874 {
0875     platform_driver_unregister(&ath10k_ahb_driver);
0876 }
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