wireless/ath/ath.h

0001 /*
0002  * Copyright (c) 2008-2009 Atheros Communications Inc.
0003  *
0004  * Permission to use, copy, modify, and/or distribute this software for any
0005  * purpose with or without fee is hereby granted, provided that the above
0006  * copyright notice and this permission notice appear in all copies.
0007  *
0008  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
0009  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
0010  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
0011  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
0012  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
0013  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
0014  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
0015  */
0016
0017 #ifndef ATH_H
0018 #define ATH_H
0019
0020 #include <linux/etherdevice.h>
0021 #include <linux/skbuff.h>
0022 #include <linux/if_ether.h>
0023 #include <linux/spinlock.h>
0024 #include <net/mac80211.h>
0025
0026 /*
0027  * The key cache is used for h/w cipher state and also for
0028  * tracking station state such as the current tx antenna.
0029  * We also setup a mapping table between key cache slot indices
0030  * and station state to short-circuit node lookups on rx.
0031  * Different parts have different size key caches.  We handle
0032  * up to ATH_KEYMAX entries (could dynamically allocate state).
0033  */
0034 #define ATH_KEYMAX          128     /* max key cache size we handle */
0035
0036 struct ath_ani {
0037     bool caldone;
0038     unsigned int longcal_timer;
0039     unsigned int shortcal_timer;
0040     unsigned int resetcal_timer;
0041     unsigned int checkani_timer;
0042     struct timer_list timer;
0043 };
0044
0045 struct ath_cycle_counters {
0046     u32 cycles;
0047     u32 rx_busy;
0048     u32 rx_frame;
0049     u32 tx_frame;
0050 };
0051
0052 enum ath_device_state {
0053     ATH_HW_UNAVAILABLE,
0054     ATH_HW_INITIALIZED,
0055 };
0056
0057 enum ath_op_flags {
0058     ATH_OP_INVALID,
0059     ATH_OP_BEACONS,
0060     ATH_OP_ANI_RUN,
0061     ATH_OP_PRIM_STA_VIF,
0062     ATH_OP_HW_RESET,
0063     ATH_OP_SCANNING,
0064     ATH_OP_MULTI_CHANNEL,
0065     ATH_OP_WOW_ENABLED,
0066 };
0067
0068 enum ath_bus_type {
0069     ATH_PCI,
0070     ATH_AHB,
0071     ATH_USB,
0072 };
0073
0074 struct reg_dmn_pair_mapping {
0075     u16 reg_domain;
0076     u16 reg_5ghz_ctl;
0077     u16 reg_2ghz_ctl;
0078 };
0079
0080 struct ath_regulatory {
0081     char alpha2[2];
0082     enum nl80211_dfs_regions region;
0083     u16 country_code;
0084     u16 max_power_level;
0085     u16 current_rd;
0086     int16_t power_limit;
0087     struct reg_dmn_pair_mapping *regpair;
0088 };
0089
0090 enum ath_crypt_caps {
0091     ATH_CRYPT_CAP_CIPHER_AESCCM     = BIT(0),
0092     ATH_CRYPT_CAP_MIC_COMBINED      = BIT(1),
0093 };
0094
0095 struct ath_keyval {
0096     u8 kv_type;
0097     u8 kv_pad;
0098     u16 kv_len;
0099     u8 kv_val[16]; /* TK */
0100     u8 kv_mic[8]; /* Michael MIC key */
0101     u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
0102              * supports both MIC keys in the same key cache entry;
0103              * in that case, kv_mic is the RX key) */
0104 };
0105
0106 enum ath_cipher {
0107     ATH_CIPHER_WEP = 0,
0108     ATH_CIPHER_AES_OCB = 1,
0109     ATH_CIPHER_AES_CCM = 2,
0110     ATH_CIPHER_CKIP = 3,
0111     ATH_CIPHER_TKIP = 4,
0112     ATH_CIPHER_CLR = 5,
0113     ATH_CIPHER_MIC = 127
0114 };
0115
0116 /**
0117  * struct ath_ops - Register read/write operations
0118  *
0119  * @read: Register read
0120  * @multi_read: Multiple register read
0121  * @write: Register write
0122  * @enable_write_buffer: Enable multiple register writes
0123  * @write_flush: flush buffered register writes and disable buffering
0124  */
0125 struct ath_ops {
0126     unsigned int (*read)(void *, u32 reg_offset);
0127     void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
0128     void (*write)(void *, u32 val, u32 reg_offset);
0129     void (*enable_write_buffer)(void *);
0130     void (*write_flush) (void *);
0131     u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
0132     void (*enable_rmw_buffer)(void *);
0133     void (*rmw_flush) (void *);
0134
0135 };
0136
0137 struct ath_common;
0138 struct ath_bus_ops;
0139
0140 struct ath_ps_ops {
0141     void (*wakeup)(struct ath_common *common);
0142     void (*restore)(struct ath_common *common);
0143 };
0144
0145 struct ath_common {
0146     void *ah;
0147     void *priv;
0148     struct ieee80211_hw *hw;
0149     int debug_mask;
0150     enum ath_device_state state;
0151     unsigned long op_flags;
0152
0153     struct ath_ani ani;
0154
0155     u16 cachelsz;
0156     u16 curaid;
0157     u8 macaddr[ETH_ALEN];
0158     u8 curbssid[ETH_ALEN] __aligned(2);
0159     u8 bssidmask[ETH_ALEN];
0160
0161     u32 rx_bufsize;
0162
0163     u32 keymax;
0164     DECLARE_BITMAP(keymap, ATH_KEYMAX);
0165     DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
0166     DECLARE_BITMAP(ccmp_keymap, ATH_KEYMAX);
0167     enum ath_crypt_caps crypt_caps;
0168
0169     unsigned int clockrate;
0170
0171     spinlock_t cc_lock;
0172     struct ath_cycle_counters cc_ani;
0173     struct ath_cycle_counters cc_survey;
0174
0175     struct ath_regulatory regulatory;
0176     struct ath_regulatory reg_world_copy;
0177     const struct ath_ops *ops;
0178     const struct ath_bus_ops *bus_ops;
0179     const struct ath_ps_ops *ps_ops;
0180
0181     bool btcoex_enabled;
0182     bool disable_ani;
0183     bool bt_ant_diversity;
0184
0185     int last_rssi;
0186     struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
0187 };
0188
0189 static inline const struct ath_ps_ops *ath_ps_ops(struct ath_common *common)
0190 {
0191     return common->ps_ops;
0192 }
0193
0194 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
0195                 u32 len,
0196                 gfp_t gfp_mask);
0197 bool ath_is_mybeacon(struct ath_common *common, struct ieee80211_hdr *hdr);
0198
0199 void ath_hw_setbssidmask(struct ath_common *common);
0200 void ath_key_delete(struct ath_common *common, u8 hw_key_idx);
0201 int ath_key_config(struct ath_common *common,
0202               struct ieee80211_vif *vif,
0203               struct ieee80211_sta *sta,
0204               struct ieee80211_key_conf *key);
0205 bool ath_hw_keyreset(struct ath_common *common, u16 entry);
0206 bool ath_hw_keysetmac(struct ath_common *common, u16 entry, const u8 *mac);
0207 void ath_hw_cycle_counters_update(struct ath_common *common);
0208 int32_t ath_hw_get_listen_time(struct ath_common *common);
0209
0210 __printf(3, 4)
0211 void ath_printk(const char *level, const struct ath_common *common,
0212         const char *fmt, ...);
0213
0214 #define ath_emerg(common, fmt, ...)             \
0215     ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
0216 #define ath_alert(common, fmt, ...)             \
0217     ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
0218 #define ath_crit(common, fmt, ...)              \
0219     ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
0220 #define ath_err(common, fmt, ...)               \
0221     ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
0222 #define ath_warn(common, fmt, ...)              \
0223     ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
0224 #define ath_notice(common, fmt, ...)                \
0225     ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
0226 #define ath_info(common, fmt, ...)              \
0227     ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
0228
0229 /**
0230  * enum ath_debug_level - atheros wireless debug level
0231  *
0232  * @ATH_DBG_RESET: reset processing
0233  * @ATH_DBG_QUEUE: hardware queue management
0234  * @ATH_DBG_EEPROM: eeprom processing
0235  * @ATH_DBG_CALIBRATE: periodic calibration
0236  * @ATH_DBG_INTERRUPT: interrupt processing
0237  * @ATH_DBG_REGULATORY: regulatory processing
0238  * @ATH_DBG_ANI: adaptive noise immunitive processing
0239  * @ATH_DBG_XMIT: basic xmit operation
0240  * @ATH_DBG_BEACON: beacon handling
0241  * @ATH_DBG_CONFIG: configuration of the hardware
0242  * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
0243  * @ATH_DBG_PS: power save processing
0244  * @ATH_DBG_HWTIMER: hardware timer handling
0245  * @ATH_DBG_BTCOEX: bluetooth coexistance
0246  * @ATH_DBG_BSTUCK: stuck beacons
0247  * @ATH_DBG_MCI: Message Coexistence Interface, a private protocol
0248  *  used exclusively for WLAN-BT coexistence starting from
0249  *  AR9462.
0250  * @ATH_DBG_DFS: radar datection
0251  * @ATH_DBG_WOW: Wake on Wireless
0252  * @ATH_DBG_DYNACK: dynack handling
0253  * @ATH_DBG_SPECTRAL_SCAN: FFT spectral scan
0254  * @ATH_DBG_ANY: enable all debugging
0255  *
0256  * The debug level is used to control the amount and type of debugging output
0257  * we want to see. Each driver has its own method for enabling debugging and
0258  * modifying debug level states -- but this is typically done through a
0259  * module parameter 'debug' along with a respective 'debug' debugfs file
0260  * entry.
0261  */
0262 enum ATH_DEBUG {
0263     ATH_DBG_RESET       = 0x00000001,
0264     ATH_DBG_QUEUE       = 0x00000002,
0265     ATH_DBG_EEPROM      = 0x00000004,
0266     ATH_DBG_CALIBRATE   = 0x00000008,
0267     ATH_DBG_INTERRUPT   = 0x00000010,
0268     ATH_DBG_REGULATORY  = 0x00000020,
0269     ATH_DBG_ANI     = 0x00000040,
0270     ATH_DBG_XMIT        = 0x00000080,
0271     ATH_DBG_BEACON      = 0x00000100,
0272     ATH_DBG_CONFIG      = 0x00000200,
0273     ATH_DBG_FATAL       = 0x00000400,
0274     ATH_DBG_PS      = 0x00000800,
0275     ATH_DBG_BTCOEX      = 0x00001000,
0276     ATH_DBG_WMI     = 0x00002000,
0277     ATH_DBG_BSTUCK      = 0x00004000,
0278     ATH_DBG_MCI     = 0x00008000,
0279     ATH_DBG_DFS     = 0x00010000,
0280     ATH_DBG_WOW     = 0x00020000,
0281     ATH_DBG_CHAN_CTX    = 0x00040000,
0282     ATH_DBG_DYNACK      = 0x00080000,
0283     ATH_DBG_SPECTRAL_SCAN   = 0x00100000,
0284     ATH_DBG_ANY     = 0xffffffff
0285 };
0286
0287 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
0288 #define ATH_DBG_MAX_LEN 512
0289
0290 #ifdef CONFIG_ATH_DEBUG
0291
0292 #define ath_dbg(common, dbg_mask, fmt, ...)             \
0293 do {                                    \
0294     if ((common)->debug_mask & ATH_DBG_##dbg_mask)          \
0295         ath_printk(KERN_DEBUG, common, fmt, ##__VA_ARGS__); \
0296 } while (0)
0297
0298 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
0299 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
0300
0301 #else
0302
0303 static inline  __attribute__ ((format (printf, 3, 4)))
0304 void _ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
0305          const char *fmt, ...)
0306 {
0307 }
0308 #define ath_dbg(common, dbg_mask, fmt, ...)             \
0309     _ath_dbg(common, ATH_DBG_##dbg_mask, fmt, ##__VA_ARGS__)
0310
0311 #define ATH_DBG_WARN(foo, arg...) do {} while (0)
0312 #define ATH_DBG_WARN_ON_ONCE(foo) ({                \
0313     int __ret_warn_once = !!(foo);              \
0314     unlikely(__ret_warn_once);              \
0315 })
0316
0317 #endif /* CONFIG_ATH_DEBUG */
0318
0319 /** Returns string describing opmode, or NULL if unknown mode. */
0320 #ifdef CONFIG_ATH_DEBUG
0321 const char *ath_opmode_to_string(enum nl80211_iftype opmode);
0322 #else
0323 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)
0324 {
0325     return "UNKNOWN";
0326 }
0327 #endif
0328
0329 extern const char *ath_bus_type_strings[];
0330 static inline const char *ath_bus_type_to_string(enum ath_bus_type bustype)
0331 {
0332     return ath_bus_type_strings[bustype];
0333 }
0334
0335 #endif /* ATH_H */