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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef ADM8211_H
0003 #define ADM8211_H
0004 
0005 /* ADM8211 Registers */
0006 
0007 /* CR32 (SIG) signature */
0008 #define ADM8211_SIG1        0x82011317 /* ADM8211A */
0009 #define ADM8211_SIG2        0x82111317 /* ADM8211B/ADM8211C */
0010 
0011 #define ADM8211_CSR_READ(r) ioread32(&priv->map->r)
0012 #define ADM8211_CSR_WRITE(r, val) iowrite32((val), &priv->map->r)
0013 
0014 /* CSR (Host Control and Status Registers) */
0015 struct adm8211_csr {
0016     __le32 PAR;     /* 0x00 CSR0 */
0017     __le32 FRCTL;       /* 0x04 CSR0A */
0018     __le32 TDR;     /* 0x08 CSR1 */
0019     __le32 WTDP;        /* 0x0C CSR1A */
0020     __le32 RDR;     /* 0x10 CSR2 */
0021     __le32 WRDP;        /* 0x14 CSR2A */
0022     __le32 RDB;     /* 0x18 CSR3 */
0023     __le32 TDBH;        /* 0x1C CSR3A */
0024     __le32 TDBD;        /* 0x20 CSR4 */
0025     __le32 TDBP;        /* 0x24 CSR4A */
0026     __le32 STSR;        /* 0x28 CSR5 */
0027     __le32 TDBB;        /* 0x2C CSR5A */
0028     __le32 NAR;     /* 0x30 CSR6 */
0029     __le32 CSR6A;       /* reserved */
0030     __le32 IER;     /* 0x38 CSR7 */
0031     __le32 TKIPSCEP;    /* 0x3C CSR7A */
0032     __le32 LPC;     /* 0x40 CSR8 */
0033     __le32 CSR_TEST1;   /* 0x44 CSR8A */
0034     __le32 SPR;     /* 0x48 CSR9 */
0035     __le32 CSR_TEST0;   /* 0x4C CSR9A */
0036     __le32 WCSR;        /* 0x50 CSR10 */
0037     __le32 WPDR;        /* 0x54 CSR10A */
0038     __le32 GPTMR;       /* 0x58 CSR11 */
0039     __le32 GPIO;        /* 0x5C CSR11A */
0040     __le32 BBPCTL;      /* 0x60 CSR12 */
0041     __le32 SYNCTL;      /* 0x64 CSR12A */
0042     __le32 PLCPHD;      /* 0x68 CSR13 */
0043     __le32 MMIWA;       /* 0x6C CSR13A */
0044     __le32 MMIRD0;      /* 0x70 CSR14 */
0045     __le32 MMIRD1;      /* 0x74 CSR14A */
0046     __le32 TXBR;        /* 0x78 CSR15 */
0047     __le32 SYNDATA;     /* 0x7C CSR15A */
0048     __le32 ALCS;        /* 0x80 CSR16 */
0049     __le32 TOFS2;       /* 0x84 CSR17 */
0050     __le32 CMDR;        /* 0x88 CSR18 */
0051     __le32 PCIC;        /* 0x8C CSR19 */
0052     __le32 PMCSR;       /* 0x90 CSR20 */
0053     __le32 PAR0;        /* 0x94 CSR21 */
0054     __le32 PAR1;        /* 0x98 CSR22 */
0055     __le32 MAR0;        /* 0x9C CSR23 */
0056     __le32 MAR1;        /* 0xA0 CSR24 */
0057     __le32 ATIMDA0;     /* 0xA4 CSR25 */
0058     __le32 ABDA1;       /* 0xA8 CSR26 */
0059     __le32 BSSID0;      /* 0xAC CSR27 */
0060     __le32 TXLMT;       /* 0xB0 CSR28 */
0061     __le32 MIBCNT;      /* 0xB4 CSR29 */
0062     __le32 BCNT;        /* 0xB8 CSR30 */
0063     __le32 TSFTH;       /* 0xBC CSR31 */
0064     __le32 TSC;     /* 0xC0 CSR32 */
0065     __le32 SYNRF;       /* 0xC4 CSR33 */
0066     __le32 BPLI;        /* 0xC8 CSR34 */
0067     __le32 CAP0;        /* 0xCC CSR35 */
0068     __le32 CAP1;        /* 0xD0 CSR36 */
0069     __le32 RMD;     /* 0xD4 CSR37 */
0070     __le32 CFPP;        /* 0xD8 CSR38 */
0071     __le32 TOFS0;       /* 0xDC CSR39 */
0072     __le32 TOFS1;       /* 0xE0 CSR40 */
0073     __le32 IFST;        /* 0xE4 CSR41 */
0074     __le32 RSPT;        /* 0xE8 CSR42 */
0075     __le32 TSFTL;       /* 0xEC CSR43 */
0076     __le32 WEPCTL;      /* 0xF0 CSR44 */
0077     __le32 WESK;        /* 0xF4 CSR45 */
0078     __le32 WEPCNT;      /* 0xF8 CSR46 */
0079     __le32 MACTEST;     /* 0xFC CSR47 */
0080     __le32 FER;     /* 0x100 */
0081     __le32 FEMR;        /* 0x104 */
0082     __le32 FPSR;        /* 0x108 */
0083     __le32 FFER;        /* 0x10C */
0084 } __packed;
0085 
0086 /* CSR0 - PAR (PCI Address Register) */
0087 #define ADM8211_PAR_MWIE    (1 << 24)
0088 #define ADM8211_PAR_MRLE    (1 << 23)
0089 #define ADM8211_PAR_MRME    (1 << 21)
0090 #define ADM8211_PAR_RAP     ((1 << 18) | (1 << 17))
0091 #define ADM8211_PAR_CAL     ((1 << 15) | (1 << 14))
0092 #define ADM8211_PAR_PBL     0x00003f00
0093 #define ADM8211_PAR_BLE     (1 << 7)
0094 #define ADM8211_PAR_DSL     0x0000007c
0095 #define ADM8211_PAR_BAR     (1 << 1)
0096 #define ADM8211_PAR_SWR     (1 << 0)
0097 
0098 /* CSR1 - FRCTL (Frame Control Register) */
0099 #define ADM8211_FRCTL_PWRMGT    (1 << 31)
0100 #define ADM8211_FRCTL_MAXPSP    (1 << 27)
0101 #define ADM8211_FRCTL_DRVPRSP   (1 << 26)
0102 #define ADM8211_FRCTL_DRVBCON   (1 << 25)
0103 #define ADM8211_FRCTL_AID   0x0000ffff
0104 #define ADM8211_FRCTL_AID_ON    0x0000c000
0105 
0106 /* CSR5 - STSR (Status Register) */
0107 #define ADM8211_STSR_PCF    (1 << 31)
0108 #define ADM8211_STSR_BCNTC  (1 << 30)
0109 #define ADM8211_STSR_GPINT  (1 << 29)
0110 #define ADM8211_STSR_LinkOff    (1 << 28)
0111 #define ADM8211_STSR_ATIMTC (1 << 27)
0112 #define ADM8211_STSR_TSFTF  (1 << 26)
0113 #define ADM8211_STSR_TSCZ   (1 << 25)
0114 #define ADM8211_STSR_LinkOn (1 << 24)
0115 #define ADM8211_STSR_SQL    (1 << 23)
0116 #define ADM8211_STSR_WEPTD  (1 << 22)
0117 #define ADM8211_STSR_ATIME  (1 << 21)
0118 #define ADM8211_STSR_TBTT   (1 << 20)
0119 #define ADM8211_STSR_NISS   (1 << 16)
0120 #define ADM8211_STSR_AISS   (1 << 15)
0121 #define ADM8211_STSR_TEIS   (1 << 14)
0122 #define ADM8211_STSR_FBE    (1 << 13)
0123 #define ADM8211_STSR_REIS   (1 << 12)
0124 #define ADM8211_STSR_GPTT   (1 << 11)
0125 #define ADM8211_STSR_RPS    (1 << 8)
0126 #define ADM8211_STSR_RDU    (1 << 7)
0127 #define ADM8211_STSR_RCI    (1 << 6)
0128 #define ADM8211_STSR_TUF    (1 << 5)
0129 #define ADM8211_STSR_TRT    (1 << 4)
0130 #define ADM8211_STSR_TLT    (1 << 3)
0131 #define ADM8211_STSR_TDU    (1 << 2)
0132 #define ADM8211_STSR_TPS    (1 << 1)
0133 #define ADM8211_STSR_TCI    (1 << 0)
0134 
0135 /* CSR6 - NAR (Network Access Register) */
0136 #define ADM8211_NAR_TXCF    (1 << 31)
0137 #define ADM8211_NAR_HF      (1 << 30)
0138 #define ADM8211_NAR_UTR     (1 << 29)
0139 #define ADM8211_NAR_SQ      (1 << 28)
0140 #define ADM8211_NAR_CFP     (1 << 27)
0141 #define ADM8211_NAR_SF      (1 << 21)
0142 #define ADM8211_NAR_TR      ((1 << 15) | (1 << 14))
0143 #define ADM8211_NAR_ST      (1 << 13)
0144 #define ADM8211_NAR_OM      ((1 << 11) | (1 << 10))
0145 #define ADM8211_NAR_MM      (1 << 7)
0146 #define ADM8211_NAR_PR      (1 << 6)
0147 #define ADM8211_NAR_EA      (1 << 5)
0148 #define ADM8211_NAR_PB      (1 << 3)
0149 #define ADM8211_NAR_STPDMA  (1 << 2)
0150 #define ADM8211_NAR_SR      (1 << 1)
0151 #define ADM8211_NAR_CTX     (1 << 0)
0152 
0153 #define ADM8211_IDLE()                             \
0154 do {                                       \
0155     if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST)) {           \
0156         ADM8211_CSR_WRITE(NAR, priv->nar &             \
0157                        ~(ADM8211_NAR_SR | ADM8211_NAR_ST));\
0158         ADM8211_CSR_READ(NAR);                     \
0159         msleep(20);                        \
0160     }                                  \
0161 } while (0)
0162 
0163 #define ADM8211_IDLE_RX()                       \
0164 do {                                    \
0165     if (priv->nar & ADM8211_NAR_SR) {               \
0166         ADM8211_CSR_WRITE(NAR, priv->nar & ~ADM8211_NAR_SR);    \
0167         ADM8211_CSR_READ(NAR);                  \
0168         mdelay(20);                     \
0169     }                               \
0170 } while (0)
0171 
0172 #define ADM8211_RESTORE()                   \
0173 do {                                \
0174     if (priv->nar & (ADM8211_NAR_SR | ADM8211_NAR_ST))  \
0175         ADM8211_CSR_WRITE(NAR, priv->nar);      \
0176 } while (0)
0177 
0178 /* CSR7 - IER (Interrupt Enable Register) */
0179 #define ADM8211_IER_PCFIE   (1 << 31)
0180 #define ADM8211_IER_BCNTCIE (1 << 30)
0181 #define ADM8211_IER_GPIE    (1 << 29)
0182 #define ADM8211_IER_LinkOffIE   (1 << 28)
0183 #define ADM8211_IER_ATIMTCIE    (1 << 27)
0184 #define ADM8211_IER_TSFTFIE (1 << 26)
0185 #define ADM8211_IER_TSCZE   (1 << 25)
0186 #define ADM8211_IER_LinkOnIE    (1 << 24)
0187 #define ADM8211_IER_SQLIE   (1 << 23)
0188 #define ADM8211_IER_WEPIE   (1 << 22)
0189 #define ADM8211_IER_ATIMEIE (1 << 21)
0190 #define ADM8211_IER_TBTTIE  (1 << 20)
0191 #define ADM8211_IER_NIE     (1 << 16)
0192 #define ADM8211_IER_AIE     (1 << 15)
0193 #define ADM8211_IER_TEIE    (1 << 14)
0194 #define ADM8211_IER_FBEIE   (1 << 13)
0195 #define ADM8211_IER_REIE    (1 << 12)
0196 #define ADM8211_IER_GPTIE   (1 << 11)
0197 #define ADM8211_IER_RSIE    (1 << 8)
0198 #define ADM8211_IER_RUIE    (1 << 7)
0199 #define ADM8211_IER_RCIE    (1 << 6)
0200 #define ADM8211_IER_TUIE    (1 << 5)
0201 #define ADM8211_IER_TRTIE   (1 << 4)
0202 #define ADM8211_IER_TLTTIE  (1 << 3)
0203 #define ADM8211_IER_TDUIE   (1 << 2)
0204 #define ADM8211_IER_TPSIE   (1 << 1)
0205 #define ADM8211_IER_TCIE    (1 << 0)
0206 
0207 /* CSR9 - SPR (Serial Port Register) */
0208 #define ADM8211_SPR_SRS     (1 << 11)
0209 #define ADM8211_SPR_SDO     (1 << 3)
0210 #define ADM8211_SPR_SDI     (1 << 2)
0211 #define ADM8211_SPR_SCLK    (1 << 1)
0212 #define ADM8211_SPR_SCS     (1 << 0)
0213 
0214 /* CSR9A - CSR_TEST0 */
0215 #define ADM8211_CSR_TEST0_EPNE  (1 << 18)
0216 #define ADM8211_CSR_TEST0_EPSNM (1 << 17)
0217 #define ADM8211_CSR_TEST0_EPTYP (1 << 16)
0218 #define ADM8211_CSR_TEST0_EPRLD (1 << 15)
0219 
0220 /* CSR10 - WCSR (Wake-up Control/Status Register) */
0221 #define ADM8211_WCSR_CRCT   (1 << 30)
0222 #define ADM8211_WCSR_TSFTWE (1 << 20)
0223 #define ADM8211_WCSR_TIMWE  (1 << 19)
0224 #define ADM8211_WCSR_ATIMWE (1 << 18)
0225 #define ADM8211_WCSR_KEYWE  (1 << 17)
0226 #define ADM8211_WCSR_MPRE   (1 << 9)
0227 #define ADM8211_WCSR_LSOE   (1 << 8)
0228 #define ADM8211_WCSR_KEYUP  (1 << 6)
0229 #define ADM8211_WCSR_TSFTW  (1 << 5)
0230 #define ADM8211_WCSR_TIMW   (1 << 4)
0231 #define ADM8211_WCSR_ATIMW  (1 << 3)
0232 #define ADM8211_WCSR_MPR    (1 << 1)
0233 #define ADM8211_WCSR_LSO    (1 << 0)
0234 
0235 /* CSR11A - GPIO */
0236 #define ADM8211_CSR_GPIO_EN5    (1 << 17)
0237 #define ADM8211_CSR_GPIO_EN4    (1 << 16)
0238 #define ADM8211_CSR_GPIO_EN3    (1 << 15)
0239 #define ADM8211_CSR_GPIO_EN2    (1 << 14)
0240 #define ADM8211_CSR_GPIO_EN1    (1 << 13)
0241 #define ADM8211_CSR_GPIO_EN0    (1 << 12)
0242 #define ADM8211_CSR_GPIO_O5 (1 << 11)
0243 #define ADM8211_CSR_GPIO_O4 (1 << 10)
0244 #define ADM8211_CSR_GPIO_O3 (1 << 9)
0245 #define ADM8211_CSR_GPIO_O2 (1 << 8)
0246 #define ADM8211_CSR_GPIO_O1 (1 << 7)
0247 #define ADM8211_CSR_GPIO_O0 (1 << 6)
0248 #define ADM8211_CSR_GPIO_IN 0x0000003f
0249 
0250 /* CSR12 - BBPCTL (BBP Control port) */
0251 #define ADM8211_BBPCTL_MMISEL   (1 << 31)
0252 #define ADM8211_BBPCTL_SPICADD  (0x7F << 24)
0253 #define ADM8211_BBPCTL_RF3000   (0x20 << 24)
0254 #define ADM8211_BBPCTL_TXCE (1 << 23)
0255 #define ADM8211_BBPCTL_RXCE (1 << 22)
0256 #define ADM8211_BBPCTL_CCAP (1 << 21)
0257 #define ADM8211_BBPCTL_TYPE 0x001c0000
0258 #define ADM8211_BBPCTL_WR   (1 << 17)
0259 #define ADM8211_BBPCTL_RD   (1 << 16)
0260 #define ADM8211_BBPCTL_ADDR 0x0000ff00
0261 #define ADM8211_BBPCTL_DATA 0x000000ff
0262 
0263 /* CSR12A - SYNCTL (Synthesizer Control port) */
0264 #define ADM8211_SYNCTL_WR   (1 << 31)
0265 #define ADM8211_SYNCTL_RD   (1 << 30)
0266 #define ADM8211_SYNCTL_CS0  (1 << 29)
0267 #define ADM8211_SYNCTL_CS1  (1 << 28)
0268 #define ADM8211_SYNCTL_CAL  (1 << 27)
0269 #define ADM8211_SYNCTL_SELCAL   (1 << 26)
0270 #define ADM8211_SYNCTL_RFtype   ((1 << 24) | (1 << 23) | (1 << 22))
0271 #define ADM8211_SYNCTL_RFMD (1 << 22)
0272 #define ADM8211_SYNCTL_GENERAL  (0x7 << 22)
0273 /* SYNCTL 21:0 Data (Si4126: 18-bit data, 4-bit address) */
0274 
0275 /* CSR18 - CMDR (Command Register) */
0276 #define ADM8211_CMDR_PM     (1 << 19)
0277 #define ADM8211_CMDR_APM    (1 << 18)
0278 #define ADM8211_CMDR_RTE    (1 << 4)
0279 #define ADM8211_CMDR_DRT    ((1 << 3) | (1 << 2))
0280 #define ADM8211_CMDR_DRT_8DW    (0x0 << 2)
0281 #define ADM8211_CMDR_DRT_16DW   (0x1 << 2)
0282 #define ADM8211_CMDR_DRT_SF (0x2 << 2)
0283 
0284 /* CSR33 - SYNRF (SYNRF direct control) */
0285 #define ADM8211_SYNRF_SELSYN    (1 << 31)
0286 #define ADM8211_SYNRF_SELRF (1 << 30)
0287 #define ADM8211_SYNRF_LERF  (1 << 29)
0288 #define ADM8211_SYNRF_LEIF  (1 << 28)
0289 #define ADM8211_SYNRF_SYNCLK    (1 << 27)
0290 #define ADM8211_SYNRF_SYNDATA   (1 << 26)
0291 #define ADM8211_SYNRF_PE1   (1 << 25)
0292 #define ADM8211_SYNRF_PE2   (1 << 24)
0293 #define ADM8211_SYNRF_PA_PE (1 << 23)
0294 #define ADM8211_SYNRF_TR_SW (1 << 22)
0295 #define ADM8211_SYNRF_TR_SWN    (1 << 21)
0296 #define ADM8211_SYNRF_RADIO (1 << 20)
0297 #define ADM8211_SYNRF_CAL_EN    (1 << 19)
0298 #define ADM8211_SYNRF_PHYRST    (1 << 18)
0299 
0300 #define ADM8211_SYNRF_IF_SELECT_0   (1 << 31)
0301 #define ADM8211_SYNRF_IF_SELECT_1   ((1 << 31) | (1 << 28))
0302 #define ADM8211_SYNRF_WRITE_SYNDATA_0   (1 << 31)
0303 #define ADM8211_SYNRF_WRITE_SYNDATA_1   ((1 << 31) | (1 << 26))
0304 #define ADM8211_SYNRF_WRITE_CLOCK_0 (1 << 31)
0305 #define ADM8211_SYNRF_WRITE_CLOCK_1 ((1 << 31) | (1 << 27))
0306 
0307 /* CSR44 - WEPCTL (WEP Control) */
0308 #define ADM8211_WEPCTL_WEPENABLE   (1 << 31)
0309 #define ADM8211_WEPCTL_WPAENABLE   (1 << 30)
0310 #define ADM8211_WEPCTL_CURRENT_TABLE (1 << 29)
0311 #define ADM8211_WEPCTL_TABLE_WR (1 << 28)
0312 #define ADM8211_WEPCTL_TABLE_RD (1 << 27)
0313 #define ADM8211_WEPCTL_WEPRXBYP (1 << 25)
0314 #define ADM8211_WEPCTL_SEL_WEPTABLE (1 << 23)
0315 #define ADM8211_WEPCTL_ADDR (0x000001ff)
0316 
0317 /* CSR45 - WESK (Data Entry for Share/Individual Key) */
0318 #define ADM8211_WESK_DATA   (0x0000ffff)
0319 
0320 /* FER (Function Event Register) */
0321 #define ADM8211_FER_INTR_EV_ENT (1 << 15)
0322 
0323 
0324 /* Si4126 RF Synthesizer - Control Registers */
0325 #define SI4126_MAIN_CONF    0
0326 #define SI4126_PHASE_DET_GAIN   1
0327 #define SI4126_POWERDOWN    2
0328 #define SI4126_RF1_N_DIV    3 /* only Si4136 */
0329 #define SI4126_RF2_N_DIV    4
0330 #define SI4126_IF_N_DIV     5
0331 #define SI4126_RF1_R_DIV    6 /* only Si4136 */
0332 #define SI4126_RF2_R_DIV    7
0333 #define SI4126_IF_R_DIV     8
0334 
0335 /* Main Configuration */
0336 #define SI4126_MAIN_XINDIV2 (1 << 6)
0337 #define SI4126_MAIN_IFDIV   ((1 << 11) | (1 << 10))
0338 /* Powerdown */
0339 #define SI4126_POWERDOWN_PDIB   (1 << 1)
0340 #define SI4126_POWERDOWN_PDRB   (1 << 0)
0341 
0342 
0343 /* RF3000 BBP - Control Port Registers */
0344 /* 0x00 - reserved */
0345 #define RF3000_MODEM_CTRL__RX_STATUS 0x01
0346 #define RF3000_CCA_CTRL 0x02
0347 #define RF3000_DIVERSITY__RSSI 0x03
0348 #define RF3000_RX_SIGNAL_FIELD 0x04
0349 #define RF3000_RX_LEN_MSB 0x05
0350 #define RF3000_RX_LEN_LSB 0x06
0351 #define RF3000_RX_SERVICE_FIELD 0x07
0352 #define RF3000_TX_VAR_GAIN__TX_LEN_EXT 0x11
0353 #define RF3000_TX_LEN_MSB 0x12
0354 #define RF3000_TX_LEN_LSB 0x13
0355 #define RF3000_LOW_GAIN_CALIB 0x14
0356 #define RF3000_HIGH_GAIN_CALIB 0x15
0357 
0358 /* ADM8211 revisions */
0359 #define ADM8211_REV_AB 0x11
0360 #define ADM8211_REV_AF 0x15
0361 #define ADM8211_REV_BA 0x20
0362 #define ADM8211_REV_CA 0x30
0363 
0364 struct adm8211_desc {
0365     __le32 status;
0366     __le32 length;
0367     __le32 buffer1;
0368     __le32 buffer2;
0369 };
0370 
0371 #define RDES0_STATUS_OWN    (1 << 31)
0372 #define RDES0_STATUS_ES     (1 << 30)
0373 #define RDES0_STATUS_SQL    (1 << 29)
0374 #define RDES0_STATUS_DE     (1 << 28)
0375 #define RDES0_STATUS_FS     (1 << 27)
0376 #define RDES0_STATUS_LS     (1 << 26)
0377 #define RDES0_STATUS_PCF    (1 << 25)
0378 #define RDES0_STATUS_SFDE   (1 << 24)
0379 #define RDES0_STATUS_SIGE   (1 << 23)
0380 #define RDES0_STATUS_CRC16E (1 << 22)
0381 #define RDES0_STATUS_RXTOE  (1 << 21)
0382 #define RDES0_STATUS_CRC32E (1 << 20)
0383 #define RDES0_STATUS_ICVE   (1 << 19)
0384 #define RDES0_STATUS_DA1    (1 << 17)
0385 #define RDES0_STATUS_DA0    (1 << 16)
0386 #define RDES0_STATUS_RXDR   ((1 << 15) | (1 << 14) | (1 << 13) | (1 << 12))
0387 #define RDES0_STATUS_FL     (0x00000fff)
0388 
0389 #define RDES1_CONTROL_RER   (1 << 25)
0390 #define RDES1_CONTROL_RCH   (1 << 24)
0391 #define RDES1_CONTROL_RBS2  (0x00fff000)
0392 #define RDES1_CONTROL_RBS1  (0x00000fff)
0393 
0394 #define RDES1_STATUS_RSSI   (0x0000007f)
0395 
0396 
0397 #define TDES0_CONTROL_OWN   (1 << 31)
0398 #define TDES0_CONTROL_DONE  (1 << 30)
0399 #define TDES0_CONTROL_TXDR  (0x0ff00000)
0400 
0401 #define TDES0_STATUS_OWN    (1 << 31)
0402 #define TDES0_STATUS_DONE   (1 << 30)
0403 #define TDES0_STATUS_ES     (1 << 29)
0404 #define TDES0_STATUS_TLT    (1 << 28)
0405 #define TDES0_STATUS_TRT    (1 << 27)
0406 #define TDES0_STATUS_TUF    (1 << 26)
0407 #define TDES0_STATUS_TRO    (1 << 25)
0408 #define TDES0_STATUS_SOFBR  (1 << 24)
0409 #define TDES0_STATUS_ACR    (0x00000fff)
0410 
0411 #define TDES1_CONTROL_IC    (1 << 31)
0412 #define TDES1_CONTROL_LS    (1 << 30)
0413 #define TDES1_CONTROL_FS    (1 << 29)
0414 #define TDES1_CONTROL_TER   (1 << 25)
0415 #define TDES1_CONTROL_TCH   (1 << 24)
0416 #define TDES1_CONTROL_RBS2  (0x00fff000)
0417 #define TDES1_CONTROL_RBS1  (0x00000fff)
0418 
0419 /* SRAM offsets */
0420 #define ADM8211_SRAM(x) (priv->pdev->revision < ADM8211_REV_BA ? \
0421         ADM8211_SRAM_A_ ## x : ADM8211_SRAM_B_ ## x)
0422 
0423 #define ADM8211_SRAM_INDIV_KEY   0x0000
0424 #define ADM8211_SRAM_A_SHARE_KEY 0x0160
0425 #define ADM8211_SRAM_B_SHARE_KEY 0x00c0
0426 
0427 #define ADM8211_SRAM_A_SSID      0x0180
0428 #define ADM8211_SRAM_B_SSID      0x00d4
0429 #define ADM8211_SRAM_SSID ADM8211_SRAM(SSID)
0430 
0431 #define ADM8211_SRAM_A_SUPP_RATE 0x0191
0432 #define ADM8211_SRAM_B_SUPP_RATE 0x00dd
0433 #define ADM8211_SRAM_SUPP_RATE ADM8211_SRAM(SUPP_RATE)
0434 
0435 #define ADM8211_SRAM_A_SIZE      0x0200
0436 #define ADM8211_SRAM_B_SIZE      0x01c0
0437 #define ADM8211_SRAM_SIZE ADM8211_SRAM(SIZE)
0438 
0439 struct adm8211_rx_ring_info {
0440     struct sk_buff *skb;
0441     dma_addr_t mapping;
0442 };
0443 
0444 struct adm8211_tx_ring_info {
0445     struct sk_buff *skb;
0446     dma_addr_t mapping;
0447     size_t hdrlen;
0448 };
0449 
0450 #define PLCP_SIGNAL_1M      0x0a
0451 #define PLCP_SIGNAL_2M      0x14
0452 #define PLCP_SIGNAL_5M5     0x37
0453 #define PLCP_SIGNAL_11M     0x6e
0454 
0455 struct adm8211_tx_hdr {
0456     u8 da[6];
0457     u8 signal; /* PLCP signal / TX rate in 100 Kbps */
0458     u8 service;
0459     __le16 frame_body_size;
0460     __le16 frame_control;
0461     __le16 plcp_frag_tail_len;
0462     __le16 plcp_frag_head_len;
0463     __le16 dur_frag_tail;
0464     __le16 dur_frag_head;
0465     u8 addr4[6];
0466 
0467 #define ADM8211_TXHDRCTL_SHORT_PREAMBLE     (1 <<  0)
0468 #define ADM8211_TXHDRCTL_MORE_FRAG      (1 <<  1)
0469 #define ADM8211_TXHDRCTL_MORE_DATA      (1 <<  2)
0470 #define ADM8211_TXHDRCTL_FRAG_NO        (1 <<  3) /* ? */
0471 #define ADM8211_TXHDRCTL_ENABLE_RTS     (1 <<  4)
0472 #define ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE  (1 <<  5)
0473 #define ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER   (1 << 15) /* ? */
0474     __le16 header_control;
0475     __le16 frag;
0476     u8 reserved_0;
0477     u8 retry_limit;
0478 
0479     u32 wep2key0;
0480     u32 wep2key1;
0481     u32 wep2key2;
0482     u32 wep2key3;
0483 
0484     u8 keyid;
0485     u8 entry_control;   // huh??
0486     u16 reserved_1;
0487     u32 reserved_2;
0488 } __packed;
0489 
0490 
0491 #define RX_COPY_BREAK 128
0492 #define RX_PKT_SIZE 2500
0493 
0494 struct adm8211_eeprom {
0495     __le16  signature;      /* 0x00 */
0496     u8  major_version;      /* 0x02 */
0497     u8  minor_version;      /* 0x03 */
0498     u8  reserved_1[4];      /* 0x04 */
0499     u8  hwaddr[6];      /* 0x08 */
0500     u8  reserved_2[8];      /* 0x1E */
0501     __le16  cr49;           /* 0x16 */
0502     u8  cr03;           /* 0x18 */
0503     u8  cr28;           /* 0x19 */
0504     u8  cr29;           /* 0x1A */
0505     u8  country_code;       /* 0x1B */
0506 
0507 /* specific bbp types */
0508 #define ADM8211_BBP_RFMD3000    0x00
0509 #define ADM8211_BBP_RFMD3002    0x01
0510 #define ADM8211_BBP_ADM8011 0x04
0511     u8  specific_bbptype;   /* 0x1C */
0512     u8  specific_rftype;    /* 0x1D */
0513     u8  reserved_3[2];      /* 0x1E */
0514     __le16  device_id;      /* 0x20 */
0515     __le16  vendor_id;      /* 0x22 */
0516     __le16  subsystem_id;       /* 0x24 */
0517     __le16  subsystem_vendor_id;    /* 0x26 */
0518     u8  maxlat;         /* 0x28 */
0519     u8  mingnt;         /* 0x29 */
0520     __le16  cis_pointer_low;    /* 0x2A */
0521     __le16  cis_pointer_high;   /* 0x2C */
0522     __le16  csr18;          /* 0x2E */
0523     u8  reserved_4[16];     /* 0x30 */
0524     u8  d1_pwrdara;     /* 0x40 */
0525     u8  d0_pwrdara;     /* 0x41 */
0526     u8  d3_pwrdara;     /* 0x42 */
0527     u8  d2_pwrdara;     /* 0x43 */
0528     u8  antenna_power[14];  /* 0x44 */
0529     __le16  cis_wordcnt;        /* 0x52 */
0530     u8  tx_power[14];       /* 0x54 */
0531     u8  lpf_cutoff[14];     /* 0x62 */
0532     u8  lnags_threshold[14];    /* 0x70 */
0533     __le16  checksum;       /* 0x7E */
0534     u8  cis_data[];     /* 0x80, 384 bytes */
0535 } __packed;
0536 
0537 struct adm8211_priv {
0538     struct pci_dev *pdev;
0539     spinlock_t lock;
0540     struct adm8211_csr __iomem *map;
0541     struct adm8211_desc *rx_ring;
0542     struct adm8211_desc *tx_ring;
0543     dma_addr_t rx_ring_dma;
0544     dma_addr_t tx_ring_dma;
0545     struct adm8211_rx_ring_info *rx_buffers;
0546     struct adm8211_tx_ring_info *tx_buffers;
0547     unsigned int rx_ring_size, tx_ring_size;
0548     unsigned int cur_tx, dirty_tx, cur_rx;
0549 
0550     struct ieee80211_low_level_stats stats;
0551     struct ieee80211_supported_band band;
0552     struct ieee80211_channel channels[14];
0553     int mode;
0554 
0555     int channel;
0556     u8 bssid[ETH_ALEN];
0557 
0558     u8 soft_rx_crc;
0559     u8 retry_limit;
0560 
0561     u8 ant_power;
0562     u8 tx_power;
0563     u8 lpf_cutoff;
0564     u8 lnags_threshold;
0565     struct adm8211_eeprom *eeprom;
0566     size_t eeprom_len;
0567 
0568     u32 nar;
0569 
0570 #define ADM8211_TYPE_INTERSIL   0x00
0571 #define ADM8211_TYPE_RFMD   0x01
0572 #define ADM8211_TYPE_MARVEL 0x02
0573 #define ADM8211_TYPE_AIROHA 0x03
0574 #define ADM8211_TYPE_ADMTEK     0x05
0575     unsigned int rf_type:3;
0576     unsigned int bbp_type:3;
0577 
0578     u8 specific_bbptype;
0579     enum {
0580         ADM8211_RFMD2948 = 0x0,
0581         ADM8211_RFMD2958 = 0x1,
0582         ADM8211_RFMD2958_RF3000_CONTROL_POWER = 0x2,
0583         ADM8211_MAX2820 = 0x8,
0584         ADM8211_AL2210L = 0xC,  /* Airoha */
0585     } transceiver_type;
0586 };
0587 
0588 struct ieee80211_chan_range {
0589     u8 min;
0590     u8 max;
0591 };
0592 
0593 static const struct ieee80211_chan_range cranges[] = {
0594     {1,  11},   /* FCC */
0595     {1,  11},   /* IC */
0596     {1,  13},   /* ETSI */
0597     {10, 11},   /* SPAIN */
0598     {10, 13},   /* FRANCE */
0599     {14, 14},   /* MMK */
0600     {1,  14},   /* MMK2 */
0601 };
0602 
0603 #endif /* ADM8211_H */
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