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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 
0003 /*
0004  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
0005  *
0006  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
0007  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
0008  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
0009  * and used with permission.
0010  *
0011  * Much thanks to Infineon-ADMtek for their support of this driver.
0012  */
0013 
0014 #include <linux/interrupt.h>
0015 #include <linux/if.h>
0016 #include <linux/skbuff.h>
0017 #include <linux/slab.h>
0018 #include <linux/etherdevice.h>
0019 #include <linux/pci.h>
0020 #include <linux/delay.h>
0021 #include <linux/crc32.h>
0022 #include <linux/eeprom_93cx6.h>
0023 #include <linux/module.h>
0024 #include <net/mac80211.h>
0025 
0026 #include "adm8211.h"
0027 
0028 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
0029 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
0030 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
0031 MODULE_LICENSE("GPL");
0032 
0033 static unsigned int tx_ring_size __read_mostly = 16;
0034 static unsigned int rx_ring_size __read_mostly = 16;
0035 
0036 module_param(tx_ring_size, uint, 0);
0037 module_param(rx_ring_size, uint, 0);
0038 
0039 static const struct pci_device_id adm8211_pci_id_table[] = {
0040     /* ADMtek ADM8211 */
0041     { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
0042     { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
0043     { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
0044     { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
0045     { 0 }
0046 };
0047 
0048 static struct ieee80211_rate adm8211_rates[] = {
0049     { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
0050     { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
0051     { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
0052     { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
0053     { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
0054 };
0055 
0056 static const struct ieee80211_channel adm8211_channels[] = {
0057     { .center_freq = 2412},
0058     { .center_freq = 2417},
0059     { .center_freq = 2422},
0060     { .center_freq = 2427},
0061     { .center_freq = 2432},
0062     { .center_freq = 2437},
0063     { .center_freq = 2442},
0064     { .center_freq = 2447},
0065     { .center_freq = 2452},
0066     { .center_freq = 2457},
0067     { .center_freq = 2462},
0068     { .center_freq = 2467},
0069     { .center_freq = 2472},
0070     { .center_freq = 2484},
0071 };
0072 
0073 
0074 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
0075 {
0076     struct adm8211_priv *priv = eeprom->data;
0077     u32 reg = ADM8211_CSR_READ(SPR);
0078 
0079     eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
0080     eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
0081     eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
0082     eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
0083 }
0084 
0085 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
0086 {
0087     struct adm8211_priv *priv = eeprom->data;
0088     u32 reg = 0x4000 | ADM8211_SPR_SRS;
0089 
0090     if (eeprom->reg_data_in)
0091         reg |= ADM8211_SPR_SDI;
0092     if (eeprom->reg_data_out)
0093         reg |= ADM8211_SPR_SDO;
0094     if (eeprom->reg_data_clock)
0095         reg |= ADM8211_SPR_SCLK;
0096     if (eeprom->reg_chip_select)
0097         reg |= ADM8211_SPR_SCS;
0098 
0099     ADM8211_CSR_WRITE(SPR, reg);
0100     ADM8211_CSR_READ(SPR);      /* eeprom_delay */
0101 }
0102 
0103 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
0104 {
0105     struct adm8211_priv *priv = dev->priv;
0106     unsigned int words, i;
0107     struct ieee80211_chan_range chan_range;
0108     u16 cr49;
0109     struct eeprom_93cx6 eeprom = {
0110         .data       = priv,
0111         .register_read  = adm8211_eeprom_register_read,
0112         .register_write = adm8211_eeprom_register_write
0113     };
0114 
0115     if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
0116         /* 256 * 16-bit = 512 bytes */
0117         eeprom.width = PCI_EEPROM_WIDTH_93C66;
0118         words = 256;
0119     } else {
0120         /* 64 * 16-bit = 128 bytes */
0121         eeprom.width = PCI_EEPROM_WIDTH_93C46;
0122         words = 64;
0123     }
0124 
0125     priv->eeprom_len = words * 2;
0126     priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
0127     if (!priv->eeprom)
0128         return -ENOMEM;
0129 
0130     eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
0131 
0132     cr49 = le16_to_cpu(priv->eeprom->cr49);
0133     priv->rf_type = (cr49 >> 3) & 0x7;
0134     switch (priv->rf_type) {
0135     case ADM8211_TYPE_INTERSIL:
0136     case ADM8211_TYPE_RFMD:
0137     case ADM8211_TYPE_MARVEL:
0138     case ADM8211_TYPE_AIROHA:
0139     case ADM8211_TYPE_ADMTEK:
0140         break;
0141 
0142     default:
0143         if (priv->pdev->revision < ADM8211_REV_CA)
0144             priv->rf_type = ADM8211_TYPE_RFMD;
0145         else
0146             priv->rf_type = ADM8211_TYPE_AIROHA;
0147 
0148         printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
0149                pci_name(priv->pdev), (cr49 >> 3) & 0x7);
0150     }
0151 
0152     priv->bbp_type = cr49 & 0x7;
0153     switch (priv->bbp_type) {
0154     case ADM8211_TYPE_INTERSIL:
0155     case ADM8211_TYPE_RFMD:
0156     case ADM8211_TYPE_MARVEL:
0157     case ADM8211_TYPE_AIROHA:
0158     case ADM8211_TYPE_ADMTEK:
0159         break;
0160     default:
0161         if (priv->pdev->revision < ADM8211_REV_CA)
0162             priv->bbp_type = ADM8211_TYPE_RFMD;
0163         else
0164             priv->bbp_type = ADM8211_TYPE_ADMTEK;
0165 
0166         printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
0167                pci_name(priv->pdev), cr49 >> 3);
0168     }
0169 
0170     if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
0171         printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
0172                pci_name(priv->pdev), priv->eeprom->country_code);
0173 
0174         chan_range = cranges[2];
0175     } else
0176         chan_range = cranges[priv->eeprom->country_code];
0177 
0178     printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
0179            pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
0180 
0181     BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
0182 
0183     memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
0184     priv->band.channels = priv->channels;
0185     priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
0186     priv->band.bitrates = adm8211_rates;
0187     priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
0188 
0189     for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
0190         if (i < chan_range.min || i > chan_range.max)
0191             priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
0192 
0193     switch (priv->eeprom->specific_bbptype) {
0194     case ADM8211_BBP_RFMD3000:
0195     case ADM8211_BBP_RFMD3002:
0196     case ADM8211_BBP_ADM8011:
0197         priv->specific_bbptype = priv->eeprom->specific_bbptype;
0198         break;
0199 
0200     default:
0201         if (priv->pdev->revision < ADM8211_REV_CA)
0202             priv->specific_bbptype = ADM8211_BBP_RFMD3000;
0203         else
0204             priv->specific_bbptype = ADM8211_BBP_ADM8011;
0205 
0206         printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
0207                pci_name(priv->pdev), priv->eeprom->specific_bbptype);
0208     }
0209 
0210     switch (priv->eeprom->specific_rftype) {
0211     case ADM8211_RFMD2948:
0212     case ADM8211_RFMD2958:
0213     case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
0214     case ADM8211_MAX2820:
0215     case ADM8211_AL2210L:
0216         priv->transceiver_type = priv->eeprom->specific_rftype;
0217         break;
0218 
0219     default:
0220         if (priv->pdev->revision == ADM8211_REV_BA)
0221             priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
0222         else if (priv->pdev->revision == ADM8211_REV_CA)
0223             priv->transceiver_type = ADM8211_AL2210L;
0224         else if (priv->pdev->revision == ADM8211_REV_AB)
0225             priv->transceiver_type = ADM8211_RFMD2948;
0226 
0227         printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
0228                pci_name(priv->pdev), priv->eeprom->specific_rftype);
0229 
0230         break;
0231     }
0232 
0233     printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
0234                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
0235            priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
0236 
0237     return 0;
0238 }
0239 
0240 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
0241                       u32 addr, u32 data)
0242 {
0243     struct adm8211_priv *priv = dev->priv;
0244 
0245     ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
0246               (priv->pdev->revision < ADM8211_REV_BA ?
0247                0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
0248     ADM8211_CSR_READ(WEPCTL);
0249     msleep(1);
0250 
0251     ADM8211_CSR_WRITE(WESK, data);
0252     ADM8211_CSR_READ(WESK);
0253     msleep(1);
0254 }
0255 
0256 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
0257                      unsigned int addr, u8 *buf,
0258                      unsigned int len)
0259 {
0260     struct adm8211_priv *priv = dev->priv;
0261     u32 reg = ADM8211_CSR_READ(WEPCTL);
0262     unsigned int i;
0263 
0264     if (priv->pdev->revision < ADM8211_REV_BA) {
0265         for (i = 0; i < len; i += 2) {
0266             u16 val = buf[i] | (buf[i + 1] << 8);
0267             adm8211_write_sram(dev, addr + i / 2, val);
0268         }
0269     } else {
0270         for (i = 0; i < len; i += 4) {
0271             u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
0272                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
0273             adm8211_write_sram(dev, addr + i / 4, val);
0274         }
0275     }
0276 
0277     ADM8211_CSR_WRITE(WEPCTL, reg);
0278 }
0279 
0280 static void adm8211_clear_sram(struct ieee80211_hw *dev)
0281 {
0282     struct adm8211_priv *priv = dev->priv;
0283     u32 reg = ADM8211_CSR_READ(WEPCTL);
0284     unsigned int addr;
0285 
0286     for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
0287         adm8211_write_sram(dev, addr, 0);
0288 
0289     ADM8211_CSR_WRITE(WEPCTL, reg);
0290 }
0291 
0292 static int adm8211_get_stats(struct ieee80211_hw *dev,
0293                  struct ieee80211_low_level_stats *stats)
0294 {
0295     struct adm8211_priv *priv = dev->priv;
0296 
0297     memcpy(stats, &priv->stats, sizeof(*stats));
0298 
0299     return 0;
0300 }
0301 
0302 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
0303 {
0304     struct adm8211_priv *priv = dev->priv;
0305     unsigned int dirty_tx;
0306 
0307     spin_lock(&priv->lock);
0308 
0309     for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
0310         unsigned int entry = dirty_tx % priv->tx_ring_size;
0311         u32 status = le32_to_cpu(priv->tx_ring[entry].status);
0312         struct ieee80211_tx_info *txi;
0313         struct adm8211_tx_ring_info *info;
0314         struct sk_buff *skb;
0315 
0316         if (status & TDES0_CONTROL_OWN ||
0317             !(status & TDES0_CONTROL_DONE))
0318             break;
0319 
0320         info = &priv->tx_buffers[entry];
0321         skb = info->skb;
0322         txi = IEEE80211_SKB_CB(skb);
0323 
0324         /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
0325 
0326         dma_unmap_single(&priv->pdev->dev, info->mapping,
0327                  info->skb->len, DMA_TO_DEVICE);
0328 
0329         ieee80211_tx_info_clear_status(txi);
0330 
0331         skb_pull(skb, sizeof(struct adm8211_tx_hdr));
0332         memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
0333         if (!(txi->flags & IEEE80211_TX_CTL_NO_ACK) &&
0334             !(status & TDES0_STATUS_ES))
0335             txi->flags |= IEEE80211_TX_STAT_ACK;
0336 
0337         ieee80211_tx_status_irqsafe(dev, skb);
0338 
0339         info->skb = NULL;
0340     }
0341 
0342     if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
0343         ieee80211_wake_queue(dev, 0);
0344 
0345     priv->dirty_tx = dirty_tx;
0346     spin_unlock(&priv->lock);
0347 }
0348 
0349 
0350 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
0351 {
0352     struct adm8211_priv *priv = dev->priv;
0353     unsigned int entry = priv->cur_rx % priv->rx_ring_size;
0354     u32 status;
0355     unsigned int pktlen;
0356     struct sk_buff *skb, *newskb;
0357     unsigned int limit = priv->rx_ring_size;
0358     u8 rssi, rate;
0359 
0360     while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
0361         if (!limit--)
0362             break;
0363 
0364         status = le32_to_cpu(priv->rx_ring[entry].status);
0365         rate = (status & RDES0_STATUS_RXDR) >> 12;
0366         rssi = le32_to_cpu(priv->rx_ring[entry].length) &
0367             RDES1_STATUS_RSSI;
0368 
0369         pktlen = status & RDES0_STATUS_FL;
0370         if (pktlen > RX_PKT_SIZE) {
0371             if (net_ratelimit())
0372                 wiphy_debug(dev->wiphy, "frame too long (%d)\n",
0373                         pktlen);
0374             pktlen = RX_PKT_SIZE;
0375         }
0376 
0377         if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
0378             skb = NULL; /* old buffer will be reused */
0379             /* TODO: update RX error stats */
0380             /* TODO: check RDES0_STATUS_CRC*E */
0381         } else if (pktlen < RX_COPY_BREAK) {
0382             skb = dev_alloc_skb(pktlen);
0383             if (skb) {
0384                 dma_sync_single_for_cpu(&priv->pdev->dev,
0385                             priv->rx_buffers[entry].mapping,
0386                             pktlen,
0387                             DMA_FROM_DEVICE);
0388                 skb_put_data(skb,
0389                          skb_tail_pointer(priv->rx_buffers[entry].skb),
0390                          pktlen);
0391                 dma_sync_single_for_device(&priv->pdev->dev,
0392                                priv->rx_buffers[entry].mapping,
0393                                RX_PKT_SIZE,
0394                                DMA_FROM_DEVICE);
0395             }
0396         } else {
0397             newskb = dev_alloc_skb(RX_PKT_SIZE);
0398             if (newskb) {
0399                 skb = priv->rx_buffers[entry].skb;
0400                 skb_put(skb, pktlen);
0401                 dma_unmap_single(&priv->pdev->dev,
0402                          priv->rx_buffers[entry].mapping,
0403                          RX_PKT_SIZE, DMA_FROM_DEVICE);
0404                 priv->rx_buffers[entry].skb = newskb;
0405                 priv->rx_buffers[entry].mapping =
0406                     dma_map_single(&priv->pdev->dev,
0407                                skb_tail_pointer(newskb),
0408                                RX_PKT_SIZE,
0409                                DMA_FROM_DEVICE);
0410                 if (dma_mapping_error(&priv->pdev->dev,
0411                               priv->rx_buffers[entry].mapping)) {
0412                     priv->rx_buffers[entry].skb = NULL;
0413                     dev_kfree_skb(newskb);
0414                     skb = NULL;
0415                     /* TODO: update rx dropped stats */
0416                 }
0417             } else {
0418                 skb = NULL;
0419                 /* TODO: update rx dropped stats */
0420             }
0421 
0422             priv->rx_ring[entry].buffer1 =
0423                 cpu_to_le32(priv->rx_buffers[entry].mapping);
0424         }
0425 
0426         priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
0427                               RDES0_STATUS_SQL);
0428         priv->rx_ring[entry].length =
0429             cpu_to_le32(RX_PKT_SIZE |
0430                     (entry == priv->rx_ring_size - 1 ?
0431                      RDES1_CONTROL_RER : 0));
0432 
0433         if (skb) {
0434             struct ieee80211_rx_status rx_status = {0};
0435 
0436             if (priv->pdev->revision < ADM8211_REV_CA)
0437                 rx_status.signal = rssi;
0438             else
0439                 rx_status.signal = 100 - rssi;
0440 
0441             rx_status.rate_idx = rate;
0442 
0443             rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
0444             rx_status.band = NL80211_BAND_2GHZ;
0445 
0446             memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
0447             ieee80211_rx_irqsafe(dev, skb);
0448         }
0449 
0450         entry = (++priv->cur_rx) % priv->rx_ring_size;
0451     }
0452 
0453     /* TODO: check LPC and update stats? */
0454 }
0455 
0456 
0457 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
0458 {
0459 #define ADM8211_INT(x)                      \
0460 do {                                \
0461     if (unlikely(stsr & ADM8211_STSR_ ## x))        \
0462         wiphy_debug(dev->wiphy, "%s\n", #x);        \
0463 } while (0)
0464 
0465     struct ieee80211_hw *dev = dev_id;
0466     struct adm8211_priv *priv = dev->priv;
0467     u32 stsr = ADM8211_CSR_READ(STSR);
0468     ADM8211_CSR_WRITE(STSR, stsr);
0469     if (stsr == 0xffffffff)
0470         return IRQ_HANDLED;
0471 
0472     if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
0473         return IRQ_HANDLED;
0474 
0475     if (stsr & ADM8211_STSR_RCI)
0476         adm8211_interrupt_rci(dev);
0477     if (stsr & ADM8211_STSR_TCI)
0478         adm8211_interrupt_tci(dev);
0479 
0480     ADM8211_INT(PCF);
0481     ADM8211_INT(BCNTC);
0482     ADM8211_INT(GPINT);
0483     ADM8211_INT(ATIMTC);
0484     ADM8211_INT(TSFTF);
0485     ADM8211_INT(TSCZ);
0486     ADM8211_INT(SQL);
0487     ADM8211_INT(WEPTD);
0488     ADM8211_INT(ATIME);
0489     ADM8211_INT(TEIS);
0490     ADM8211_INT(FBE);
0491     ADM8211_INT(REIS);
0492     ADM8211_INT(GPTT);
0493     ADM8211_INT(RPS);
0494     ADM8211_INT(RDU);
0495     ADM8211_INT(TUF);
0496     ADM8211_INT(TPS);
0497 
0498     return IRQ_HANDLED;
0499 
0500 #undef ADM8211_INT
0501 }
0502 
0503 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
0504 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
0505                        u16 addr, u32 value) {        \
0506     struct adm8211_priv *priv = dev->priv;                   \
0507     unsigned int i;                              \
0508     u32 reg, bitbuf;                             \
0509                                          \
0510     value &= v_mask;                             \
0511     addr &= a_mask;                              \
0512     bitbuf = (value << v_shift) | (addr << a_shift);             \
0513                                          \
0514     ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);             \
0515     ADM8211_CSR_READ(SYNRF);                         \
0516     ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);             \
0517     ADM8211_CSR_READ(SYNRF);                         \
0518                                          \
0519     if (prewrite) {                              \
0520         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
0521         ADM8211_CSR_READ(SYNRF);                     \
0522     }                                    \
0523                                          \
0524     for (i = 0; i <= bits; i++) {                        \
0525         if (bitbuf & (1 << (bits - i)))                  \
0526             reg = ADM8211_SYNRF_WRITE_SYNDATA_1;             \
0527         else                                 \
0528             reg = ADM8211_SYNRF_WRITE_SYNDATA_0;             \
0529                                          \
0530         ADM8211_CSR_WRITE(SYNRF, reg);                   \
0531         ADM8211_CSR_READ(SYNRF);                     \
0532                                          \
0533         ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
0534         ADM8211_CSR_READ(SYNRF);                     \
0535         ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
0536         ADM8211_CSR_READ(SYNRF);                     \
0537     }                                    \
0538                                          \
0539     if (postwrite == 1) {                            \
0540         ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
0541         ADM8211_CSR_READ(SYNRF);                     \
0542     }                                    \
0543     if (postwrite == 2) {                            \
0544         ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
0545         ADM8211_CSR_READ(SYNRF);                     \
0546     }                                    \
0547                                          \
0548     ADM8211_CSR_WRITE(SYNRF, 0);                         \
0549     ADM8211_CSR_READ(SYNRF);                         \
0550 }
0551 
0552 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
0553 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
0554 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
0555 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
0556 
0557 #undef WRITE_SYN
0558 
0559 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
0560 {
0561     struct adm8211_priv *priv = dev->priv;
0562     unsigned int timeout;
0563     u32 reg;
0564 
0565     timeout = 10;
0566     while (timeout > 0) {
0567         reg = ADM8211_CSR_READ(BBPCTL);
0568         if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
0569             break;
0570         timeout--;
0571         msleep(2);
0572     }
0573 
0574     if (timeout == 0) {
0575         wiphy_debug(dev->wiphy,
0576                 "adm8211_write_bbp(%d,%d) failed prewrite (reg=0x%08x)\n",
0577                 addr, data, reg);
0578         return -ETIMEDOUT;
0579     }
0580 
0581     switch (priv->bbp_type) {
0582     case ADM8211_TYPE_INTERSIL:
0583         reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
0584         break;
0585     case ADM8211_TYPE_RFMD:
0586         reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
0587               (0x01 << 18);
0588         break;
0589     case ADM8211_TYPE_ADMTEK:
0590         reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
0591               (0x05 << 18);
0592         break;
0593     }
0594     reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
0595 
0596     ADM8211_CSR_WRITE(BBPCTL, reg);
0597 
0598     timeout = 10;
0599     while (timeout > 0) {
0600         reg = ADM8211_CSR_READ(BBPCTL);
0601         if (!(reg & ADM8211_BBPCTL_WR))
0602             break;
0603         timeout--;
0604         msleep(2);
0605     }
0606 
0607     if (timeout == 0) {
0608         ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
0609                   ~ADM8211_BBPCTL_WR);
0610         wiphy_debug(dev->wiphy,
0611                 "adm8211_write_bbp(%d,%d) failed postwrite (reg=0x%08x)\n",
0612                 addr, data, reg);
0613         return -ETIMEDOUT;
0614     }
0615 
0616     return 0;
0617 }
0618 
0619 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
0620 {
0621     static const u32 adm8211_rfmd2958_reg5[] =
0622         {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
0623          0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
0624     static const u32 adm8211_rfmd2958_reg6[] =
0625         {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
0626          0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
0627 
0628     struct adm8211_priv *priv = dev->priv;
0629     u8 ant_power = priv->ant_power > 0x3F ?
0630         priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
0631     u8 tx_power = priv->tx_power > 0x3F ?
0632         priv->eeprom->tx_power[chan - 1] : priv->tx_power;
0633     u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
0634         priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
0635     u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
0636         priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
0637     u32 reg;
0638 
0639     ADM8211_IDLE();
0640 
0641     /* Program synthesizer to new channel */
0642     switch (priv->transceiver_type) {
0643     case ADM8211_RFMD2958:
0644     case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
0645         adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
0646         adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
0647 
0648         adm8211_rf_write_syn_rfmd2958(dev, 0x05,
0649             adm8211_rfmd2958_reg5[chan - 1]);
0650         adm8211_rf_write_syn_rfmd2958(dev, 0x06,
0651             adm8211_rfmd2958_reg6[chan - 1]);
0652         break;
0653 
0654     case ADM8211_RFMD2948:
0655         adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
0656                           SI4126_MAIN_XINDIV2);
0657         adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
0658                           SI4126_POWERDOWN_PDIB |
0659                           SI4126_POWERDOWN_PDRB);
0660         adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
0661         adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
0662                           (chan == 14 ?
0663                            2110 : (2033 + (chan * 5))));
0664         adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
0665         adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
0666         adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
0667         break;
0668 
0669     case ADM8211_MAX2820:
0670         adm8211_rf_write_syn_max2820(dev, 0x3,
0671             (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
0672         break;
0673 
0674     case ADM8211_AL2210L:
0675         adm8211_rf_write_syn_al2210l(dev, 0x0,
0676             (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
0677         break;
0678 
0679     default:
0680         wiphy_debug(dev->wiphy, "unsupported transceiver type %d\n",
0681                 priv->transceiver_type);
0682         break;
0683     }
0684 
0685     /* write BBP regs */
0686     if (priv->bbp_type == ADM8211_TYPE_RFMD) {
0687 
0688     /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
0689     /* TODO: remove if SMC 2635W doesn't need this */
0690     if (priv->transceiver_type == ADM8211_RFMD2948) {
0691         reg = ADM8211_CSR_READ(GPIO);
0692         reg &= 0xfffc0000;
0693         reg |= ADM8211_CSR_GPIO_EN0;
0694         if (chan != 14)
0695             reg |= ADM8211_CSR_GPIO_O0;
0696         ADM8211_CSR_WRITE(GPIO, reg);
0697     }
0698 
0699     if (priv->transceiver_type == ADM8211_RFMD2958) {
0700         /* set PCNT2 */
0701         adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
0702         /* set PCNT1 P_DESIRED/MID_BIAS */
0703         reg = le16_to_cpu(priv->eeprom->cr49);
0704         reg >>= 13;
0705         reg <<= 15;
0706         reg |= ant_power << 9;
0707         adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
0708         /* set TXRX TX_GAIN */
0709         adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
0710             (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
0711     } else {
0712         reg = ADM8211_CSR_READ(PLCPHD);
0713         reg &= 0xff00ffff;
0714         reg |= tx_power << 18;
0715         ADM8211_CSR_WRITE(PLCPHD, reg);
0716     }
0717 
0718     ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
0719               ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
0720     ADM8211_CSR_READ(SYNRF);
0721     msleep(30);
0722 
0723     /* RF3000 BBP */
0724     if (priv->transceiver_type != ADM8211_RFMD2958)
0725         adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
0726                   tx_power<<2);
0727     adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
0728     adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
0729     adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
0730                      priv->eeprom->cr28 : 0);
0731     adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
0732 
0733     ADM8211_CSR_WRITE(SYNRF, 0);
0734 
0735     /* Nothing to do for ADMtek BBP */
0736     } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
0737         wiphy_debug(dev->wiphy, "unsupported BBP type %d\n",
0738                 priv->bbp_type);
0739 
0740     ADM8211_RESTORE();
0741 
0742     /* update current channel for adhoc (and maybe AP mode) */
0743     reg = ADM8211_CSR_READ(CAP0);
0744     reg &= ~0xF;
0745     reg |= chan;
0746     ADM8211_CSR_WRITE(CAP0, reg);
0747 
0748     return 0;
0749 }
0750 
0751 static void adm8211_update_mode(struct ieee80211_hw *dev)
0752 {
0753     struct adm8211_priv *priv = dev->priv;
0754 
0755     ADM8211_IDLE();
0756 
0757     priv->soft_rx_crc = 0;
0758     switch (priv->mode) {
0759     case NL80211_IFTYPE_STATION:
0760         priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
0761         priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
0762         break;
0763     case NL80211_IFTYPE_ADHOC:
0764         priv->nar &= ~ADM8211_NAR_PR;
0765         priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
0766 
0767         /* don't trust the error bits on rev 0x20 and up in adhoc */
0768         if (priv->pdev->revision >= ADM8211_REV_BA)
0769             priv->soft_rx_crc = 1;
0770         break;
0771     case NL80211_IFTYPE_MONITOR:
0772         priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
0773         priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
0774         break;
0775     }
0776 
0777     ADM8211_RESTORE();
0778 }
0779 
0780 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
0781 {
0782     struct adm8211_priv *priv = dev->priv;
0783 
0784     switch (priv->transceiver_type) {
0785     case ADM8211_RFMD2958:
0786     case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
0787         /* comments taken from ADMtek vendor driver */
0788 
0789         /* Reset RF2958 after power on */
0790         adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
0791         /* Initialize RF VCO Core Bias to maximum */
0792         adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
0793         /* Initialize IF PLL */
0794         adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
0795         /* Initialize IF PLL Coarse Tuning */
0796         adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
0797         /* Initialize RF PLL */
0798         adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
0799         /* Initialize RF PLL Coarse Tuning */
0800         adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
0801         /* Initialize TX gain and filter BW (R9) */
0802         adm8211_rf_write_syn_rfmd2958(dev, 0x09,
0803             (priv->transceiver_type == ADM8211_RFMD2958 ?
0804              0x10050 : 0x00050));
0805         /* Initialize CAL register */
0806         adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
0807         break;
0808 
0809     case ADM8211_MAX2820:
0810         adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
0811         adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
0812         adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
0813         adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
0814         adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
0815         break;
0816 
0817     case ADM8211_AL2210L:
0818         adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
0819         adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
0820         adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
0821         adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
0822         adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
0823         adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
0824         adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
0825         adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
0826         adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
0827         adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
0828         adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
0829         adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
0830         break;
0831 
0832     case ADM8211_RFMD2948:
0833     default:
0834         break;
0835     }
0836 }
0837 
0838 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
0839 {
0840     struct adm8211_priv *priv = dev->priv;
0841     u32 reg;
0842 
0843     /* write addresses */
0844     if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
0845         ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
0846         ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
0847         ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
0848     } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
0849            priv->bbp_type == ADM8211_TYPE_ADMTEK) {
0850         /* check specific BBP type */
0851         switch (priv->specific_bbptype) {
0852         case ADM8211_BBP_RFMD3000:
0853         case ADM8211_BBP_RFMD3002:
0854             ADM8211_CSR_WRITE(MMIWA,  0x00009101);
0855             ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
0856             break;
0857 
0858         case ADM8211_BBP_ADM8011:
0859             ADM8211_CSR_WRITE(MMIWA,  0x00008903);
0860             ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
0861 
0862             reg = ADM8211_CSR_READ(BBPCTL);
0863             reg &= ~ADM8211_BBPCTL_TYPE;
0864             reg |= 0x5 << 18;
0865             ADM8211_CSR_WRITE(BBPCTL, reg);
0866             break;
0867         }
0868 
0869         switch (priv->pdev->revision) {
0870         case ADM8211_REV_CA:
0871             if (priv->transceiver_type == ADM8211_RFMD2958 ||
0872                 priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
0873                 priv->transceiver_type == ADM8211_RFMD2948)
0874                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
0875             else if (priv->transceiver_type == ADM8211_MAX2820 ||
0876                  priv->transceiver_type == ADM8211_AL2210L)
0877                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
0878             break;
0879 
0880         case ADM8211_REV_BA:
0881             reg  = ADM8211_CSR_READ(MMIRD1);
0882             reg &= 0x0000FFFF;
0883             reg |= 0x7e100000;
0884             ADM8211_CSR_WRITE(MMIRD1, reg);
0885             break;
0886 
0887         case ADM8211_REV_AB:
0888         case ADM8211_REV_AF:
0889         default:
0890             ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
0891             break;
0892         }
0893 
0894         /* For RFMD */
0895         ADM8211_CSR_WRITE(MACTEST, 0x800);
0896     }
0897 
0898     adm8211_hw_init_syn(dev);
0899 
0900     /* Set RF Power control IF pin to PE1+PHYRST# */
0901     ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
0902               ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
0903     ADM8211_CSR_READ(SYNRF);
0904     msleep(20);
0905 
0906     /* write BBP regs */
0907     if (priv->bbp_type == ADM8211_TYPE_RFMD) {
0908         /* RF3000 BBP */
0909         /* another set:
0910          * 11: c8
0911          * 14: 14
0912          * 15: 50 (chan 1..13; chan 14: d0)
0913          * 1c: 00
0914          * 1d: 84
0915          */
0916         adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
0917         /* antenna selection: diversity */
0918         adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
0919         adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
0920         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
0921         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
0922 
0923         if (priv->eeprom->major_version < 2) {
0924             adm8211_write_bbp(dev, 0x1c, 0x00);
0925             adm8211_write_bbp(dev, 0x1d, 0x80);
0926         } else {
0927             if (priv->pdev->revision == ADM8211_REV_BA)
0928                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
0929             else
0930                 adm8211_write_bbp(dev, 0x1c, 0x00);
0931 
0932             adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
0933         }
0934     } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
0935         /* reset baseband */
0936         adm8211_write_bbp(dev, 0x00, 0xFF);
0937         /* antenna selection: diversity */
0938         adm8211_write_bbp(dev, 0x07, 0x0A);
0939 
0940         /* TODO: find documentation for this */
0941         switch (priv->transceiver_type) {
0942         case ADM8211_RFMD2958:
0943         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
0944             adm8211_write_bbp(dev, 0x00, 0x00);
0945             adm8211_write_bbp(dev, 0x01, 0x00);
0946             adm8211_write_bbp(dev, 0x02, 0x00);
0947             adm8211_write_bbp(dev, 0x03, 0x00);
0948             adm8211_write_bbp(dev, 0x06, 0x0f);
0949             adm8211_write_bbp(dev, 0x09, 0x00);
0950             adm8211_write_bbp(dev, 0x0a, 0x00);
0951             adm8211_write_bbp(dev, 0x0b, 0x00);
0952             adm8211_write_bbp(dev, 0x0c, 0x00);
0953             adm8211_write_bbp(dev, 0x0f, 0xAA);
0954             adm8211_write_bbp(dev, 0x10, 0x8c);
0955             adm8211_write_bbp(dev, 0x11, 0x43);
0956             adm8211_write_bbp(dev, 0x18, 0x40);
0957             adm8211_write_bbp(dev, 0x20, 0x23);
0958             adm8211_write_bbp(dev, 0x21, 0x02);
0959             adm8211_write_bbp(dev, 0x22, 0x28);
0960             adm8211_write_bbp(dev, 0x23, 0x30);
0961             adm8211_write_bbp(dev, 0x24, 0x2d);
0962             adm8211_write_bbp(dev, 0x28, 0x35);
0963             adm8211_write_bbp(dev, 0x2a, 0x8c);
0964             adm8211_write_bbp(dev, 0x2b, 0x81);
0965             adm8211_write_bbp(dev, 0x2c, 0x44);
0966             adm8211_write_bbp(dev, 0x2d, 0x0A);
0967             adm8211_write_bbp(dev, 0x29, 0x40);
0968             adm8211_write_bbp(dev, 0x60, 0x08);
0969             adm8211_write_bbp(dev, 0x64, 0x01);
0970             break;
0971 
0972         case ADM8211_MAX2820:
0973             adm8211_write_bbp(dev, 0x00, 0x00);
0974             adm8211_write_bbp(dev, 0x01, 0x00);
0975             adm8211_write_bbp(dev, 0x02, 0x00);
0976             adm8211_write_bbp(dev, 0x03, 0x00);
0977             adm8211_write_bbp(dev, 0x06, 0x0f);
0978             adm8211_write_bbp(dev, 0x09, 0x05);
0979             adm8211_write_bbp(dev, 0x0a, 0x02);
0980             adm8211_write_bbp(dev, 0x0b, 0x00);
0981             adm8211_write_bbp(dev, 0x0c, 0x0f);
0982             adm8211_write_bbp(dev, 0x0f, 0x55);
0983             adm8211_write_bbp(dev, 0x10, 0x8d);
0984             adm8211_write_bbp(dev, 0x11, 0x43);
0985             adm8211_write_bbp(dev, 0x18, 0x4a);
0986             adm8211_write_bbp(dev, 0x20, 0x20);
0987             adm8211_write_bbp(dev, 0x21, 0x02);
0988             adm8211_write_bbp(dev, 0x22, 0x23);
0989             adm8211_write_bbp(dev, 0x23, 0x30);
0990             adm8211_write_bbp(dev, 0x24, 0x2d);
0991             adm8211_write_bbp(dev, 0x2a, 0x8c);
0992             adm8211_write_bbp(dev, 0x2b, 0x81);
0993             adm8211_write_bbp(dev, 0x2c, 0x44);
0994             adm8211_write_bbp(dev, 0x29, 0x4a);
0995             adm8211_write_bbp(dev, 0x60, 0x2b);
0996             adm8211_write_bbp(dev, 0x64, 0x01);
0997             break;
0998 
0999         case ADM8211_AL2210L:
1000             adm8211_write_bbp(dev, 0x00, 0x00);
1001             adm8211_write_bbp(dev, 0x01, 0x00);
1002             adm8211_write_bbp(dev, 0x02, 0x00);
1003             adm8211_write_bbp(dev, 0x03, 0x00);
1004             adm8211_write_bbp(dev, 0x06, 0x0f);
1005             adm8211_write_bbp(dev, 0x07, 0x05);
1006             adm8211_write_bbp(dev, 0x08, 0x03);
1007             adm8211_write_bbp(dev, 0x09, 0x00);
1008             adm8211_write_bbp(dev, 0x0a, 0x00);
1009             adm8211_write_bbp(dev, 0x0b, 0x00);
1010             adm8211_write_bbp(dev, 0x0c, 0x10);
1011             adm8211_write_bbp(dev, 0x0f, 0x55);
1012             adm8211_write_bbp(dev, 0x10, 0x8d);
1013             adm8211_write_bbp(dev, 0x11, 0x43);
1014             adm8211_write_bbp(dev, 0x18, 0x4a);
1015             adm8211_write_bbp(dev, 0x20, 0x20);
1016             adm8211_write_bbp(dev, 0x21, 0x02);
1017             adm8211_write_bbp(dev, 0x22, 0x23);
1018             adm8211_write_bbp(dev, 0x23, 0x30);
1019             adm8211_write_bbp(dev, 0x24, 0x2d);
1020             adm8211_write_bbp(dev, 0x2a, 0xaa);
1021             adm8211_write_bbp(dev, 0x2b, 0x81);
1022             adm8211_write_bbp(dev, 0x2c, 0x44);
1023             adm8211_write_bbp(dev, 0x29, 0xfa);
1024             adm8211_write_bbp(dev, 0x60, 0x2d);
1025             adm8211_write_bbp(dev, 0x64, 0x01);
1026             break;
1027 
1028         case ADM8211_RFMD2948:
1029             break;
1030 
1031         default:
1032             wiphy_debug(dev->wiphy, "unsupported transceiver %d\n",
1033                     priv->transceiver_type);
1034             break;
1035         }
1036     } else
1037         wiphy_debug(dev->wiphy, "unsupported BBP %d\n", priv->bbp_type);
1038 
1039     ADM8211_CSR_WRITE(SYNRF, 0);
1040 
1041     /* Set RF CAL control source to MAC control */
1042     reg = ADM8211_CSR_READ(SYNCTL);
1043     reg |= ADM8211_SYNCTL_SELCAL;
1044     ADM8211_CSR_WRITE(SYNCTL, reg);
1045 
1046     return 0;
1047 }
1048 
1049 /* configures hw beacons/probe responses */
1050 static int adm8211_set_rate(struct ieee80211_hw *dev)
1051 {
1052     struct adm8211_priv *priv = dev->priv;
1053     u32 reg;
1054     int i = 0;
1055     u8 rate_buf[12] = {0};
1056 
1057     /* write supported rates */
1058     if (priv->pdev->revision != ADM8211_REV_BA) {
1059         rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1060         for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1061             rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1062     } else {
1063         /* workaround for rev BA specific bug */
1064         rate_buf[0] = 0x04;
1065         rate_buf[1] = 0x82;
1066         rate_buf[2] = 0x04;
1067         rate_buf[3] = 0x0b;
1068         rate_buf[4] = 0x16;
1069     }
1070 
1071     adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1072                  ARRAY_SIZE(adm8211_rates) + 1);
1073 
1074     reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1075     reg |= 1 << 15; /* short preamble */
1076     reg |= 110 << 24;
1077     ADM8211_CSR_WRITE(PLCPHD, reg);
1078 
1079     /* MTMLT   = 512 TU (max TX MSDU lifetime)
1080      * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1081      * SRTYLIM = 224 (short retry limit, TX header value is default) */
1082     ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1083 
1084     return 0;
1085 }
1086 
1087 static void adm8211_hw_init(struct ieee80211_hw *dev)
1088 {
1089     struct adm8211_priv *priv = dev->priv;
1090     u32 reg;
1091     u8 cline;
1092 
1093     reg = ADM8211_CSR_READ(PAR);
1094     reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1095     reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1096 
1097     if (!pci_set_mwi(priv->pdev)) {
1098         reg |= 0x1 << 24;
1099         pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1100 
1101         switch (cline) {
1102         case  0x8:
1103             reg |= (0x1 << 14);
1104             break;
1105         case 0x10:
1106             reg |= (0x2 << 14);
1107             break;
1108         case 0x20:
1109             reg |= (0x3 << 14);
1110             break;
1111         default:
1112             reg |= (0x0 << 14);
1113             break;
1114         }
1115     }
1116 
1117     ADM8211_CSR_WRITE(PAR, reg);
1118 
1119     reg = ADM8211_CSR_READ(CSR_TEST1);
1120     reg &= ~(0xF << 28);
1121     reg |= (1 << 28) | (1 << 31);
1122     ADM8211_CSR_WRITE(CSR_TEST1, reg);
1123 
1124     /* lose link after 4 lost beacons */
1125     reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1126     ADM8211_CSR_WRITE(WCSR, reg);
1127 
1128     /* Disable APM, enable receive FIFO threshold, and set drain receive
1129      * threshold to store-and-forward */
1130     reg = ADM8211_CSR_READ(CMDR);
1131     reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1132     reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1133     ADM8211_CSR_WRITE(CMDR, reg);
1134 
1135     adm8211_set_rate(dev);
1136 
1137     /* 4-bit values:
1138      * PWR1UP   = 8 * 2 ms
1139      * PWR0PAPE = 8 us or 5 us
1140      * PWR1PAPE = 1 us or 3 us
1141      * PWR0TRSW = 5 us
1142      * PWR1TRSW = 12 us
1143      * PWR0PE2  = 13 us
1144      * PWR1PE2  = 1 us
1145      * PWR0TXPE = 8 or 6 */
1146     if (priv->pdev->revision < ADM8211_REV_CA)
1147         ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1148     else
1149         ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1150 
1151     /* Enable store and forward for transmit */
1152     priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1153     ADM8211_CSR_WRITE(NAR, priv->nar);
1154 
1155     /* Reset RF */
1156     ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1157     ADM8211_CSR_READ(SYNRF);
1158     msleep(10);
1159     ADM8211_CSR_WRITE(SYNRF, 0);
1160     ADM8211_CSR_READ(SYNRF);
1161     msleep(5);
1162 
1163     /* Set CFP Max Duration to 0x10 TU */
1164     reg = ADM8211_CSR_READ(CFPP);
1165     reg &= ~(0xffff << 8);
1166     reg |= 0x0010 << 8;
1167     ADM8211_CSR_WRITE(CFPP, reg);
1168 
1169     /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1170      * TUCNT = 0x3ff - Tu counter 1024 us  */
1171     ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1172 
1173     /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1174      * DIFS=50 us, EIFS=100 us */
1175     if (priv->pdev->revision < ADM8211_REV_CA)
1176         ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1177                     (50 << 9)  | 100);
1178     else
1179         ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1180                     (50 << 9)  | 100);
1181 
1182     /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1183      * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1184     ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1185 
1186     /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1187     ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1188 
1189     /* Initialize BBP (and SYN) */
1190     adm8211_hw_init_bbp(dev);
1191 
1192     /* make sure interrupts are off */
1193     ADM8211_CSR_WRITE(IER, 0);
1194 
1195     /* ACK interrupts */
1196     ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1197 
1198     /* Setup WEP (turns it off for now) */
1199     reg = ADM8211_CSR_READ(MACTEST);
1200     reg &= ~(7 << 20);
1201     ADM8211_CSR_WRITE(MACTEST, reg);
1202 
1203     reg = ADM8211_CSR_READ(WEPCTL);
1204     reg &= ~ADM8211_WEPCTL_WEPENABLE;
1205     reg |= ADM8211_WEPCTL_WEPRXBYP;
1206     ADM8211_CSR_WRITE(WEPCTL, reg);
1207 
1208     /* Clear the missed-packet counter. */
1209     ADM8211_CSR_READ(LPC);
1210 }
1211 
1212 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1213 {
1214     struct adm8211_priv *priv = dev->priv;
1215     u32 reg, tmp;
1216     int timeout = 100;
1217 
1218     /* Power-on issue */
1219     /* TODO: check if this is necessary */
1220     ADM8211_CSR_WRITE(FRCTL, 0);
1221 
1222     /* Reset the chip */
1223     tmp = ADM8211_CSR_READ(PAR);
1224     ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1225 
1226     while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1227         msleep(50);
1228 
1229     if (timeout <= 0)
1230         return -ETIMEDOUT;
1231 
1232     ADM8211_CSR_WRITE(PAR, tmp);
1233 
1234     if (priv->pdev->revision == ADM8211_REV_BA &&
1235         (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1236          priv->transceiver_type == ADM8211_RFMD2958)) {
1237         reg = ADM8211_CSR_READ(CSR_TEST1);
1238         reg |= (1 << 4) | (1 << 5);
1239         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1240     } else if (priv->pdev->revision == ADM8211_REV_CA) {
1241         reg = ADM8211_CSR_READ(CSR_TEST1);
1242         reg &= ~((1 << 4) | (1 << 5));
1243         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1244     }
1245 
1246     ADM8211_CSR_WRITE(FRCTL, 0);
1247 
1248     reg = ADM8211_CSR_READ(CSR_TEST0);
1249     reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1250     ADM8211_CSR_WRITE(CSR_TEST0, reg);
1251 
1252     adm8211_clear_sram(dev);
1253 
1254     return 0;
1255 }
1256 
1257 static u64 adm8211_get_tsft(struct ieee80211_hw *dev,
1258                 struct ieee80211_vif *vif)
1259 {
1260     struct adm8211_priv *priv = dev->priv;
1261     u32 tsftl;
1262     u64 tsft;
1263 
1264     tsftl = ADM8211_CSR_READ(TSFTL);
1265     tsft = ADM8211_CSR_READ(TSFTH);
1266     tsft <<= 32;
1267     tsft |= tsftl;
1268 
1269     return tsft;
1270 }
1271 
1272 static void adm8211_set_interval(struct ieee80211_hw *dev,
1273                  unsigned short bi, unsigned short li)
1274 {
1275     struct adm8211_priv *priv = dev->priv;
1276     u32 reg;
1277 
1278     /* BP (beacon interval) = data->beacon_interval
1279      * LI (listen interval) = data->listen_interval (in beacon intervals) */
1280     reg = (bi << 16) | li;
1281     ADM8211_CSR_WRITE(BPLI, reg);
1282 }
1283 
1284 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1285 {
1286     struct adm8211_priv *priv = dev->priv;
1287     u32 reg;
1288 
1289     ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1290     reg = ADM8211_CSR_READ(ABDA1);
1291     reg &= 0x0000ffff;
1292     reg |= (bssid[4] << 16) | (bssid[5] << 24);
1293     ADM8211_CSR_WRITE(ABDA1, reg);
1294 }
1295 
1296 static int adm8211_config(struct ieee80211_hw *dev, u32 changed)
1297 {
1298     struct adm8211_priv *priv = dev->priv;
1299     struct ieee80211_conf *conf = &dev->conf;
1300     int channel =
1301         ieee80211_frequency_to_channel(conf->chandef.chan->center_freq);
1302 
1303     if (channel != priv->channel) {
1304         priv->channel = channel;
1305         adm8211_rf_set_channel(dev, priv->channel);
1306     }
1307 
1308     return 0;
1309 }
1310 
1311 static void adm8211_bss_info_changed(struct ieee80211_hw *dev,
1312                      struct ieee80211_vif *vif,
1313                      struct ieee80211_bss_conf *conf,
1314                      u64 changes)
1315 {
1316     struct adm8211_priv *priv = dev->priv;
1317 
1318     if (!(changes & BSS_CHANGED_BSSID))
1319         return;
1320 
1321     if (!ether_addr_equal(conf->bssid, priv->bssid)) {
1322         adm8211_set_bssid(dev, conf->bssid);
1323         memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1324     }
1325 }
1326 
1327 static u64 adm8211_prepare_multicast(struct ieee80211_hw *hw,
1328                      struct netdev_hw_addr_list *mc_list)
1329 {
1330     unsigned int bit_nr;
1331     u32 mc_filter[2];
1332     struct netdev_hw_addr *ha;
1333 
1334     mc_filter[1] = mc_filter[0] = 0;
1335 
1336     netdev_hw_addr_list_for_each(ha, mc_list) {
1337         bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1338 
1339         bit_nr &= 0x3F;
1340         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1341     }
1342 
1343     return mc_filter[0] | ((u64)(mc_filter[1]) << 32);
1344 }
1345 
1346 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1347                      unsigned int changed_flags,
1348                      unsigned int *total_flags,
1349                      u64 multicast)
1350 {
1351     static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1352     struct adm8211_priv *priv = dev->priv;
1353     unsigned int new_flags;
1354     u32 mc_filter[2];
1355 
1356     mc_filter[0] = multicast;
1357     mc_filter[1] = multicast >> 32;
1358 
1359     new_flags = 0;
1360 
1361     if (*total_flags & FIF_ALLMULTI || multicast == ~(0ULL)) {
1362         new_flags |= FIF_ALLMULTI;
1363         priv->nar &= ~ADM8211_NAR_PR;
1364         priv->nar |= ADM8211_NAR_MM;
1365         mc_filter[1] = mc_filter[0] = ~0;
1366     } else {
1367         priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1368     }
1369 
1370     ADM8211_IDLE_RX();
1371 
1372     ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1373     ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1374     ADM8211_CSR_READ(NAR);
1375 
1376     if (priv->nar & ADM8211_NAR_PR)
1377         ieee80211_hw_set(dev, RX_INCLUDES_FCS);
1378     else
1379         __clear_bit(IEEE80211_HW_RX_INCLUDES_FCS, dev->flags);
1380 
1381     if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1382         adm8211_set_bssid(dev, bcast);
1383     else
1384         adm8211_set_bssid(dev, priv->bssid);
1385 
1386     ADM8211_RESTORE();
1387 
1388     *total_flags = new_flags;
1389 }
1390 
1391 static int adm8211_add_interface(struct ieee80211_hw *dev,
1392                  struct ieee80211_vif *vif)
1393 {
1394     struct adm8211_priv *priv = dev->priv;
1395     if (priv->mode != NL80211_IFTYPE_MONITOR)
1396         return -EOPNOTSUPP;
1397 
1398     switch (vif->type) {
1399     case NL80211_IFTYPE_STATION:
1400         priv->mode = vif->type;
1401         break;
1402     default:
1403         return -EOPNOTSUPP;
1404     }
1405 
1406     ADM8211_IDLE();
1407 
1408     ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)vif->addr));
1409     ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1410 
1411     adm8211_update_mode(dev);
1412 
1413     ADM8211_RESTORE();
1414 
1415     return 0;
1416 }
1417 
1418 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1419                      struct ieee80211_vif *vif)
1420 {
1421     struct adm8211_priv *priv = dev->priv;
1422     priv->mode = NL80211_IFTYPE_MONITOR;
1423 }
1424 
1425 static int adm8211_init_rings(struct ieee80211_hw *dev)
1426 {
1427     struct adm8211_priv *priv = dev->priv;
1428     struct adm8211_desc *desc = NULL;
1429     struct adm8211_rx_ring_info *rx_info;
1430     struct adm8211_tx_ring_info *tx_info;
1431     unsigned int i;
1432 
1433     for (i = 0; i < priv->rx_ring_size; i++) {
1434         desc = &priv->rx_ring[i];
1435         desc->status = 0;
1436         desc->length = cpu_to_le32(RX_PKT_SIZE);
1437         priv->rx_buffers[i].skb = NULL;
1438     }
1439     /* Mark the end of RX ring; hw returns to base address after this
1440      * descriptor */
1441     desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1442 
1443     for (i = 0; i < priv->rx_ring_size; i++) {
1444         desc = &priv->rx_ring[i];
1445         rx_info = &priv->rx_buffers[i];
1446 
1447         rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1448         if (rx_info->skb == NULL)
1449             break;
1450         rx_info->mapping = dma_map_single(&priv->pdev->dev,
1451                           skb_tail_pointer(rx_info->skb),
1452                           RX_PKT_SIZE,
1453                           DMA_FROM_DEVICE);
1454         if (dma_mapping_error(&priv->pdev->dev, rx_info->mapping)) {
1455             dev_kfree_skb(rx_info->skb);
1456             rx_info->skb = NULL;
1457             break;
1458         }
1459 
1460         desc->buffer1 = cpu_to_le32(rx_info->mapping);
1461         desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1462     }
1463 
1464     /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1465     for (i = 0; i < priv->tx_ring_size; i++) {
1466         desc = &priv->tx_ring[i];
1467         tx_info = &priv->tx_buffers[i];
1468 
1469         tx_info->skb = NULL;
1470         tx_info->mapping = 0;
1471         desc->status = 0;
1472     }
1473     desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1474 
1475     priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1476     ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1477     ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1478 
1479     return 0;
1480 }
1481 
1482 static void adm8211_free_rings(struct ieee80211_hw *dev)
1483 {
1484     struct adm8211_priv *priv = dev->priv;
1485     unsigned int i;
1486 
1487     for (i = 0; i < priv->rx_ring_size; i++) {
1488         if (!priv->rx_buffers[i].skb)
1489             continue;
1490 
1491         dma_unmap_single(&priv->pdev->dev,
1492                  priv->rx_buffers[i].mapping, RX_PKT_SIZE,
1493                  DMA_FROM_DEVICE);
1494 
1495         dev_kfree_skb(priv->rx_buffers[i].skb);
1496     }
1497 
1498     for (i = 0; i < priv->tx_ring_size; i++) {
1499         if (!priv->tx_buffers[i].skb)
1500             continue;
1501 
1502         dma_unmap_single(&priv->pdev->dev,
1503                  priv->tx_buffers[i].mapping,
1504                  priv->tx_buffers[i].skb->len, DMA_TO_DEVICE);
1505 
1506         dev_kfree_skb(priv->tx_buffers[i].skb);
1507     }
1508 }
1509 
1510 static int adm8211_start(struct ieee80211_hw *dev)
1511 {
1512     struct adm8211_priv *priv = dev->priv;
1513     int retval;
1514 
1515     /* Power up MAC and RF chips */
1516     retval = adm8211_hw_reset(dev);
1517     if (retval) {
1518         wiphy_err(dev->wiphy, "hardware reset failed\n");
1519         goto fail;
1520     }
1521 
1522     retval = adm8211_init_rings(dev);
1523     if (retval) {
1524         wiphy_err(dev->wiphy, "failed to initialize rings\n");
1525         goto fail;
1526     }
1527 
1528     /* Init hardware */
1529     adm8211_hw_init(dev);
1530     adm8211_rf_set_channel(dev, priv->channel);
1531 
1532     retval = request_irq(priv->pdev->irq, adm8211_interrupt,
1533                  IRQF_SHARED, "adm8211", dev);
1534     if (retval) {
1535         wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1536         goto fail;
1537     }
1538 
1539     ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1540                    ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1541                    ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1542     priv->mode = NL80211_IFTYPE_MONITOR;
1543     adm8211_update_mode(dev);
1544     ADM8211_CSR_WRITE(RDR, 0);
1545 
1546     adm8211_set_interval(dev, 100, 10);
1547     return 0;
1548 
1549 fail:
1550     return retval;
1551 }
1552 
1553 static void adm8211_stop(struct ieee80211_hw *dev)
1554 {
1555     struct adm8211_priv *priv = dev->priv;
1556 
1557     priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1558     priv->nar = 0;
1559     ADM8211_CSR_WRITE(NAR, 0);
1560     ADM8211_CSR_WRITE(IER, 0);
1561     ADM8211_CSR_READ(NAR);
1562 
1563     free_irq(priv->pdev->irq, dev);
1564 
1565     adm8211_free_rings(dev);
1566 }
1567 
1568 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1569                    int plcp_signal, int short_preamble)
1570 {
1571     /* Alternative calculation from NetBSD: */
1572 
1573 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1574 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1575 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1576 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1577 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1578 #define IEEE80211_DUR_DS_SLOW_ACK   112
1579 #define IEEE80211_DUR_DS_FAST_ACK   56
1580 #define IEEE80211_DUR_DS_SLOW_CTS   112
1581 #define IEEE80211_DUR_DS_FAST_CTS   56
1582 #define IEEE80211_DUR_DS_SLOT       20
1583 #define IEEE80211_DUR_DS_SIFS       10
1584 
1585     int remainder;
1586 
1587     *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1588         / plcp_signal;
1589 
1590     if (plcp_signal <= PLCP_SIGNAL_2M)
1591         /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1592         *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1593                  IEEE80211_DUR_DS_SHORT_PREAMBLE +
1594                  IEEE80211_DUR_DS_FAST_PLCPHDR) +
1595                  IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1596     else
1597         /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1598         *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1599                  IEEE80211_DUR_DS_SHORT_PREAMBLE +
1600                  IEEE80211_DUR_DS_FAST_PLCPHDR) +
1601                  IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1602 
1603     /* lengthen duration if long preamble */
1604     if (!short_preamble)
1605         *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1606                  IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1607             3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1608                  IEEE80211_DUR_DS_FAST_PLCPHDR);
1609 
1610 
1611     *plcp = (80 * len) / plcp_signal;
1612     remainder = (80 * len) % plcp_signal;
1613     if (plcp_signal == PLCP_SIGNAL_11M &&
1614         remainder <= 30 && remainder > 0)
1615         *plcp = (*plcp | 0x8000) + 1;
1616     else if (remainder)
1617         (*plcp)++;
1618 }
1619 
1620 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1621 static int adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1622                u16 plcp_signal,
1623                size_t hdrlen)
1624 {
1625     struct adm8211_priv *priv = dev->priv;
1626     unsigned long flags;
1627     dma_addr_t mapping;
1628     unsigned int entry;
1629     u32 flag;
1630 
1631     mapping = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
1632                  DMA_TO_DEVICE);
1633     if (dma_mapping_error(&priv->pdev->dev, mapping))
1634         return -ENOMEM;
1635 
1636     spin_lock_irqsave(&priv->lock, flags);
1637 
1638     if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1639         flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1640     else
1641         flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1642 
1643     if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1644         ieee80211_stop_queue(dev, 0);
1645 
1646     entry = priv->cur_tx % priv->tx_ring_size;
1647 
1648     priv->tx_buffers[entry].skb = skb;
1649     priv->tx_buffers[entry].mapping = mapping;
1650     priv->tx_buffers[entry].hdrlen = hdrlen;
1651     priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1652 
1653     if (entry == priv->tx_ring_size - 1)
1654         flag |= TDES1_CONTROL_TER;
1655     priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1656 
1657     /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1658     flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1659     priv->tx_ring[entry].status = cpu_to_le32(flag);
1660 
1661     priv->cur_tx++;
1662 
1663     spin_unlock_irqrestore(&priv->lock, flags);
1664 
1665     /* Trigger transmit poll */
1666     ADM8211_CSR_WRITE(TDR, 0);
1667 
1668     return 0;
1669 }
1670 
1671 /* Put adm8211_tx_hdr on skb and transmit */
1672 static void adm8211_tx(struct ieee80211_hw *dev,
1673                struct ieee80211_tx_control *control,
1674                struct sk_buff *skb)
1675 {
1676     struct adm8211_tx_hdr *txhdr;
1677     size_t payload_len, hdrlen;
1678     int plcp, dur, len, plcp_signal, short_preamble;
1679     struct ieee80211_hdr *hdr;
1680     struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1681     struct ieee80211_rate *txrate = ieee80211_get_tx_rate(dev, info);
1682     u8 rc_flags;
1683 
1684     rc_flags = info->control.rates[0].flags;
1685     short_preamble = !!(rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1686     plcp_signal = txrate->bitrate;
1687 
1688     hdr = (struct ieee80211_hdr *)skb->data;
1689     hdrlen = ieee80211_hdrlen(hdr->frame_control);
1690     memcpy(skb->cb, skb->data, hdrlen);
1691     hdr = (struct ieee80211_hdr *)skb->cb;
1692     skb_pull(skb, hdrlen);
1693     payload_len = skb->len;
1694 
1695     txhdr = skb_push(skb, sizeof(*txhdr));
1696     memset(txhdr, 0, sizeof(*txhdr));
1697     memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1698     txhdr->signal = plcp_signal;
1699     txhdr->frame_body_size = cpu_to_le16(payload_len);
1700     txhdr->frame_control = hdr->frame_control;
1701 
1702     len = hdrlen + payload_len + FCS_LEN;
1703 
1704     txhdr->frag = cpu_to_le16(0x0FFF);
1705     adm8211_calc_durations(&dur, &plcp, payload_len,
1706                    len, plcp_signal, short_preamble);
1707     txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1708     txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1709     txhdr->dur_frag_head = cpu_to_le16(dur);
1710     txhdr->dur_frag_tail = cpu_to_le16(dur);
1711 
1712     txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1713 
1714     if (short_preamble)
1715         txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1716 
1717     if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
1718         txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1719 
1720     txhdr->retry_limit = info->control.rates[0].count;
1721 
1722     if (adm8211_tx_raw(dev, skb, plcp_signal, hdrlen)) {
1723         /* Drop packet */
1724         ieee80211_free_txskb(dev, skb);
1725     }
1726 }
1727 
1728 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1729 {
1730     struct adm8211_priv *priv = dev->priv;
1731     unsigned int ring_size;
1732 
1733     priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1734                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1735     if (!priv->rx_buffers)
1736         return -ENOMEM;
1737 
1738     priv->tx_buffers = (void *)priv->rx_buffers +
1739                sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1740 
1741     /* Allocate TX/RX descriptors */
1742     ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1743             sizeof(struct adm8211_desc) * priv->tx_ring_size;
1744     priv->rx_ring = dma_alloc_coherent(&priv->pdev->dev, ring_size,
1745                        &priv->rx_ring_dma, GFP_KERNEL);
1746 
1747     if (!priv->rx_ring) {
1748         kfree(priv->rx_buffers);
1749         priv->rx_buffers = NULL;
1750         priv->tx_buffers = NULL;
1751         return -ENOMEM;
1752     }
1753 
1754     priv->tx_ring = priv->rx_ring + priv->rx_ring_size;
1755     priv->tx_ring_dma = priv->rx_ring_dma +
1756                 sizeof(struct adm8211_desc) * priv->rx_ring_size;
1757 
1758     return 0;
1759 }
1760 
1761 static const struct ieee80211_ops adm8211_ops = {
1762     .tx         = adm8211_tx,
1763     .start          = adm8211_start,
1764     .stop           = adm8211_stop,
1765     .add_interface      = adm8211_add_interface,
1766     .remove_interface   = adm8211_remove_interface,
1767     .config         = adm8211_config,
1768     .bss_info_changed   = adm8211_bss_info_changed,
1769     .prepare_multicast  = adm8211_prepare_multicast,
1770     .configure_filter   = adm8211_configure_filter,
1771     .get_stats      = adm8211_get_stats,
1772     .get_tsf        = adm8211_get_tsft
1773 };
1774 
1775 static int adm8211_probe(struct pci_dev *pdev,
1776                    const struct pci_device_id *id)
1777 {
1778     struct ieee80211_hw *dev;
1779     struct adm8211_priv *priv;
1780     unsigned long mem_len;
1781     unsigned int io_len;
1782     int err;
1783     u32 reg;
1784     u8 perm_addr[ETH_ALEN];
1785 
1786     err = pci_enable_device(pdev);
1787     if (err) {
1788         printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1789                pci_name(pdev));
1790         return err;
1791     }
1792 
1793     io_len = pci_resource_len(pdev, 0);
1794     mem_len = pci_resource_len(pdev, 1);
1795     if (io_len < 256 || mem_len < 1024) {
1796         printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1797                pci_name(pdev));
1798         err = -ENOMEM;
1799         goto err_disable_pdev;
1800     }
1801 
1802 
1803     /* check signature */
1804     pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1805     if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1806         printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1807                pci_name(pdev), reg);
1808         err = -EINVAL;
1809         goto err_disable_pdev;
1810     }
1811 
1812     err = pci_request_regions(pdev, "adm8211");
1813     if (err) {
1814         printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1815                pci_name(pdev));
1816         return err; /* someone else grabbed it? don't disable it */
1817     }
1818 
1819     err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1820     if (err) {
1821         printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1822                pci_name(pdev));
1823         goto err_free_reg;
1824     }
1825 
1826     pci_set_master(pdev);
1827 
1828     dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1829     if (!dev) {
1830         printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1831                pci_name(pdev));
1832         err = -ENOMEM;
1833         goto err_free_reg;
1834     }
1835     priv = dev->priv;
1836     priv->pdev = pdev;
1837 
1838     spin_lock_init(&priv->lock);
1839 
1840     SET_IEEE80211_DEV(dev, &pdev->dev);
1841 
1842     pci_set_drvdata(pdev, dev);
1843 
1844     priv->map = pci_iomap(pdev, 1, mem_len);
1845     if (!priv->map)
1846         priv->map = pci_iomap(pdev, 0, io_len);
1847 
1848     if (!priv->map) {
1849         printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1850                pci_name(pdev));
1851         err = -ENOMEM;
1852         goto err_free_dev;
1853     }
1854 
1855     priv->rx_ring_size = rx_ring_size;
1856     priv->tx_ring_size = tx_ring_size;
1857 
1858     err = adm8211_alloc_rings(dev);
1859     if (err) {
1860         printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1861                pci_name(pdev));
1862         goto err_iounmap;
1863     }
1864 
1865     *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1866     *(__le16 *)&perm_addr[4] =
1867         cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1868 
1869     if (!is_valid_ether_addr(perm_addr)) {
1870         printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1871                pci_name(pdev));
1872         eth_random_addr(perm_addr);
1873     }
1874     SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1875 
1876     dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1877     /* dev->flags = RX_INCLUDES_FCS in promisc mode */
1878     ieee80211_hw_set(dev, SIGNAL_UNSPEC);
1879     dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
1880 
1881     dev->max_signal = 100;    /* FIXME: find better value */
1882 
1883     dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1884 
1885     priv->retry_limit = 3;
1886     priv->ant_power = 0x40;
1887     priv->tx_power = 0x40;
1888     priv->lpf_cutoff = 0xFF;
1889     priv->lnags_threshold = 0xFF;
1890     priv->mode = NL80211_IFTYPE_UNSPECIFIED;
1891 
1892     /* Power-on issue. EEPROM won't read correctly without */
1893     if (pdev->revision >= ADM8211_REV_BA) {
1894         ADM8211_CSR_WRITE(FRCTL, 0);
1895         ADM8211_CSR_READ(FRCTL);
1896         ADM8211_CSR_WRITE(FRCTL, 1);
1897         ADM8211_CSR_READ(FRCTL);
1898         msleep(100);
1899     }
1900 
1901     err = adm8211_read_eeprom(dev);
1902     if (err) {
1903         printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1904                pci_name(pdev));
1905         goto err_free_desc;
1906     }
1907 
1908     priv->channel = 1;
1909 
1910     dev->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band;
1911 
1912     wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1913 
1914     err = ieee80211_register_hw(dev);
1915     if (err) {
1916         printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1917                pci_name(pdev));
1918         goto err_free_eeprom;
1919     }
1920 
1921     wiphy_info(dev->wiphy, "hwaddr %pM, Rev 0x%02x\n",
1922            dev->wiphy->perm_addr, pdev->revision);
1923 
1924     return 0;
1925 
1926  err_free_eeprom:
1927     kfree(priv->eeprom);
1928 
1929  err_free_desc:
1930     dma_free_coherent(&pdev->dev,
1931               sizeof(struct adm8211_desc) * priv->rx_ring_size +
1932               sizeof(struct adm8211_desc) * priv->tx_ring_size,
1933               priv->rx_ring, priv->rx_ring_dma);
1934     kfree(priv->rx_buffers);
1935 
1936  err_iounmap:
1937     pci_iounmap(pdev, priv->map);
1938 
1939  err_free_dev:
1940     ieee80211_free_hw(dev);
1941 
1942  err_free_reg:
1943     pci_release_regions(pdev);
1944 
1945  err_disable_pdev:
1946     pci_disable_device(pdev);
1947     return err;
1948 }
1949 
1950 
1951 static void adm8211_remove(struct pci_dev *pdev)
1952 {
1953     struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1954     struct adm8211_priv *priv;
1955 
1956     if (!dev)
1957         return;
1958 
1959     ieee80211_unregister_hw(dev);
1960 
1961     priv = dev->priv;
1962 
1963     dma_free_coherent(&pdev->dev,
1964               sizeof(struct adm8211_desc) * priv->rx_ring_size +
1965               sizeof(struct adm8211_desc) * priv->tx_ring_size,
1966               priv->rx_ring, priv->rx_ring_dma);
1967 
1968     kfree(priv->rx_buffers);
1969     kfree(priv->eeprom);
1970     pci_iounmap(pdev, priv->map);
1971     pci_release_regions(pdev);
1972     pci_disable_device(pdev);
1973     ieee80211_free_hw(dev);
1974 }
1975 
1976 
1977 #define adm8211_suspend NULL
1978 #define adm8211_resume NULL
1979 
1980 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
1981 
1982 static SIMPLE_DEV_PM_OPS(adm8211_pm_ops, adm8211_suspend, adm8211_resume);
1983 
1984 /* TODO: implement enable_wake */
1985 static struct pci_driver adm8211_driver = {
1986     .name       = "adm8211",
1987     .id_table   = adm8211_pci_id_table,
1988     .probe      = adm8211_probe,
1989     .remove     = adm8211_remove,
1990     .driver.pm  = &adm8211_pm_ops,
1991 };
1992 
1993 module_pci_driver(adm8211_driver);
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