net/wan/wanxl.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * wanXL serial card driver for Linux
0004  * definitions common to host driver and card firmware
0005  *
0006  * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
0007  */
0008
0009 #define RESET_WHILE_LOADING 0
0010
0011 /* you must rebuild the firmware if any of the following is changed */
0012 #define DETECT_RAM 0        /* needed for > 4MB RAM, 16 MB maximum */
0013 #define QUICC_MEMCPY_USES_PLX 1 /* must be used if the host has > 256 MB RAM */
0014
0015
0016 #define STATUS_CABLE_V35    2
0017 #define STATUS_CABLE_X21    3
0018 #define STATUS_CABLE_V24    4
0019 #define STATUS_CABLE_EIA530 5
0020 #define STATUS_CABLE_INVALID    6
0021 #define STATUS_CABLE_NONE   7
0022
0023 #define STATUS_CABLE_DCE    0x8000
0024 #define STATUS_CABLE_DSR    0x0010
0025 #define STATUS_CABLE_DCD    0x0008
0026 #define STATUS_CABLE_PM_SHIFT   5
0027
0028 #define PDM_OFFSET 0x1000
0029
0030 #define TX_BUFFERS 10       /* per port */
0031 #define RX_BUFFERS 30
0032 #define RX_QUEUE_LENGTH 40  /* card->host queue length - per card */
0033
0034 #define PACKET_EMPTY        0x00
0035 #define PACKET_FULL     0x10
0036 #define PACKET_SENT     0x20 /* TX only */
0037 #define PACKET_UNDERRUN     0x30 /* TX only */
0038 #define PACKET_PORT_MASK    0x03 /* RX only */
0039
0040 /* bit numbers in PLX9060 doorbell registers */
0041 #define DOORBELL_FROM_CARD_TX_0     0 /* packet sent by the card */
0042 #define DOORBELL_FROM_CARD_TX_1     1
0043 #define DOORBELL_FROM_CARD_TX_2     2
0044 #define DOORBELL_FROM_CARD_TX_3     3
0045 #define DOORBELL_FROM_CARD_RX       4
0046 #define DOORBELL_FROM_CARD_CABLE_0  5 /* cable/PM/etc. changed */
0047 #define DOORBELL_FROM_CARD_CABLE_1  6
0048 #define DOORBELL_FROM_CARD_CABLE_2  7
0049 #define DOORBELL_FROM_CARD_CABLE_3  8
0050
0051 #define DOORBELL_TO_CARD_OPEN_0     0
0052 #define DOORBELL_TO_CARD_OPEN_1     1
0053 #define DOORBELL_TO_CARD_OPEN_2     2
0054 #define DOORBELL_TO_CARD_OPEN_3     3
0055 #define DOORBELL_TO_CARD_CLOSE_0    4
0056 #define DOORBELL_TO_CARD_CLOSE_1    5
0057 #define DOORBELL_TO_CARD_CLOSE_2    6
0058 #define DOORBELL_TO_CARD_CLOSE_3    7
0059 #define DOORBELL_TO_CARD_TX_0       8 /* outbound packet queued */
0060 #define DOORBELL_TO_CARD_TX_1       9
0061 #define DOORBELL_TO_CARD_TX_2       10
0062 #define DOORBELL_TO_CARD_TX_3       11
0063
0064 /* firmware-only status bits, starting from last DOORBELL_TO_CARD + 1 */
0065 #define TASK_SCC_0          12
0066 #define TASK_SCC_1          13
0067 #define TASK_SCC_2          14
0068 #define TASK_SCC_3          15
0069
0070 #define ALIGN32(x) (((x) + 3) & 0xFFFFFFFC)
0071 #define BUFFER_LENGTH   ALIGN32(HDLC_MAX_MRU + 4) /* 4 bytes for 32-bit CRC */
0072
0073 /* Address of TX and RX buffers in 68360 address space */
0074 #define BUFFERS_ADDR    0x4000  /* 16 KB */
0075
0076 #ifndef __ASSEMBLER__
0077 #define PLX_OFFSET      0
0078 #else
0079 #define PLX_OFFSET      PLX + 0x80
0080 #endif
0081
0082 #define PLX_MAILBOX_0       (PLX_OFFSET + 0x40)
0083 #define PLX_MAILBOX_1       (PLX_OFFSET + 0x44)
0084 #define PLX_MAILBOX_2       (PLX_OFFSET + 0x48)
0085 #define PLX_MAILBOX_3       (PLX_OFFSET + 0x4C)
0086 #define PLX_MAILBOX_4       (PLX_OFFSET + 0x50)
0087 #define PLX_MAILBOX_5       (PLX_OFFSET + 0x54)
0088 #define PLX_MAILBOX_6       (PLX_OFFSET + 0x58)
0089 #define PLX_MAILBOX_7       (PLX_OFFSET + 0x5C)
0090 #define PLX_DOORBELL_TO_CARD    (PLX_OFFSET + 0x60)
0091 #define PLX_DOORBELL_FROM_CARD  (PLX_OFFSET + 0x64)
0092 #define PLX_INTERRUPT_CS    (PLX_OFFSET + 0x68)
0093 #define PLX_CONTROL     (PLX_OFFSET + 0x6C)
0094
0095 #ifdef __ASSEMBLER__
0096 #define PLX_DMA_0_MODE      (PLX + 0x100)
0097 #define PLX_DMA_0_PCI       (PLX + 0x104)
0098 #define PLX_DMA_0_LOCAL     (PLX + 0x108)
0099 #define PLX_DMA_0_LENGTH    (PLX + 0x10C)
0100 #define PLX_DMA_0_DESC      (PLX + 0x110)
0101 #define PLX_DMA_1_MODE      (PLX + 0x114)
0102 #define PLX_DMA_1_PCI       (PLX + 0x118)
0103 #define PLX_DMA_1_LOCAL     (PLX + 0x11C)
0104 #define PLX_DMA_1_LENGTH    (PLX + 0x120)
0105 #define PLX_DMA_1_DESC      (PLX + 0x124)
0106 #define PLX_DMA_CMD_STS     (PLX + 0x128)
0107 #define PLX_DMA_ARBITR_0    (PLX + 0x12C)
0108 #define PLX_DMA_ARBITR_1    (PLX + 0x130)
0109 #endif
0110
0111 #define DESC_LENGTH 12
0112
0113 /* offsets from start of status_t */
0114 /* card to host */
0115 #define STATUS_OPEN     0
0116 #define STATUS_CABLE        (STATUS_OPEN + 4)
0117 #define STATUS_RX_OVERRUNS  (STATUS_CABLE + 4)
0118 #define STATUS_RX_FRAME_ERRORS  (STATUS_RX_OVERRUNS + 4)
0119
0120 /* host to card */
0121 #define STATUS_PARITY       (STATUS_RX_FRAME_ERRORS + 4)
0122 #define STATUS_ENCODING     (STATUS_PARITY + 4)
0123 #define STATUS_CLOCKING     (STATUS_ENCODING + 4)
0124 #define STATUS_TX_DESCS     (STATUS_CLOCKING + 4)
0125
0126 #ifndef __ASSEMBLER__
0127
0128 typedef struct {
0129     volatile u32 stat;
0130     u32 address;        /* PCI address */
0131     volatile u32 length;
0132 }desc_t;
0133
0134
0135 typedef struct {
0136 // Card to host
0137     volatile u32 open;
0138     volatile u32 cable;
0139     volatile u32 rx_overruns;
0140     volatile u32 rx_frame_errors;
0141
0142 // Host to card
0143     u32 parity;
0144     u32 encoding;
0145     u32 clocking;
0146     desc_t tx_descs[TX_BUFFERS];
0147 }port_status_t;
0148
0149 #endif /* __ASSEMBLER__ */