net/wan/slic_ds26522.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * drivers/tdm/line_ctrl/slic_ds26522.h
0004  *
0005  * Copyright 2016 Freescale Semiconductor, Inc.
0006  *
0007  * Author: Zhao Qiang <B45475@freescale.com>
0008  */
0009
0010 #define DS26522_RF_ADDR_START   0x00
0011 #define DS26522_RF_ADDR_END 0xef
0012 #define DS26522_GLB_ADDR_START  0xf0
0013 #define DS26522_GLB_ADDR_END    0xff
0014 #define DS26522_TF_ADDR_START   0x100
0015 #define DS26522_TF_ADDR_END 0x1ef
0016 #define DS26522_LIU_ADDR_START  0x1000
0017 #define DS26522_LIU_ADDR_END    0x101f
0018 #define DS26522_TEST_ADDR_START 0x1008
0019 #define DS26522_TEST_ADDR_END   0x101f
0020 #define DS26522_BERT_ADDR_START 0x1100
0021 #define DS26522_BERT_ADDR_END   0x110f
0022
0023 #define DS26522_RMMR_ADDR   0x80
0024 #define DS26522_RCR1_ADDR   0x81
0025 #define DS26522_RCR3_ADDR   0x83
0026 #define DS26522_RIOCR_ADDR  0x84
0027
0028 #define DS26522_GTCR1_ADDR  0xf0
0029 #define DS26522_GFCR_ADDR   0xf1
0030 #define DS26522_GTCR2_ADDR  0xf2
0031 #define DS26522_GTCCR_ADDR  0xf3
0032 #define DS26522_GLSRR_ADDR  0xf5
0033 #define DS26522_GFSRR_ADDR  0xf6
0034 #define DS26522_IDR_ADDR    0xf8
0035
0036 #define DS26522_E1TAF_ADDR  0x164
0037 #define DS26522_E1TNAF_ADDR 0x165
0038 #define DS26522_TMMR_ADDR   0x180
0039 #define DS26522_TCR1_ADDR   0x181
0040 #define DS26522_TIOCR_ADDR  0x184
0041
0042 #define DS26522_LTRCR_ADDR  0x1000
0043 #define DS26522_LTITSR_ADDR 0x1001
0044 #define DS26522_LMCR_ADDR   0x1002
0045 #define DS26522_LRISMR_ADDR 0x1007
0046
0047 #define MAX_NUM_OF_CHANNELS 8
0048 #define PQ_MDS_8E1T1_BRD_REV    0x00
0049 #define PQ_MDS_8E1T1_PLD_REV    0x00
0050
0051 #define DS26522_GTCCR_BPREFSEL_REFCLKIN 0xa0
0052 #define DS26522_GTCCR_BFREQSEL_1544KHZ  0x08
0053 #define DS26522_GTCCR_FREQSEL_1544KHZ   0x04
0054 #define DS26522_GTCCR_BFREQSEL_2048KHZ  0x00
0055 #define DS26522_GTCCR_FREQSEL_2048KHZ   0x00
0056
0057 #define DS26522_GFCR_BPCLK_2048KHZ  0x00
0058
0059 #define DS26522_GTCR2_TSSYNCOUT 0x02
0060 #define DS26522_GTCR1   0x00
0061
0062 #define DS26522_GFSRR_RESET 0x01
0063 #define DS26522_GFSRR_NORMAL    0x00
0064
0065 #define DS26522_GLSRR_RESET 0x01
0066 #define DS26522_GLSRR_NORMAL    0x00
0067
0068 #define DS26522_RMMR_SFTRST 0x02
0069 #define DS26522_RMMR_FRM_EN 0x80
0070 #define DS26522_RMMR_INIT_DONE  0x40
0071 #define DS26522_RMMR_T1     0x00
0072 #define DS26522_RMMR_E1     0x01
0073
0074 #define DS26522_E1TAF_DEFAULT   0x1b
0075 #define DS26522_E1TNAF_DEFAULT  0x40
0076
0077 #define DS26522_TMMR_SFTRST 0x02
0078 #define DS26522_TMMR_FRM_EN 0x80
0079 #define DS26522_TMMR_INIT_DONE  0x40
0080 #define DS26522_TMMR_T1     0x00
0081 #define DS26522_TMMR_E1     0x01
0082
0083 #define DS26522_RCR1_T1_SYNCT   0x80
0084 #define DS26522_RCR1_T1_RB8ZS   0x40
0085 #define DS26522_RCR1_T1_SYNCC   0x08
0086
0087 #define DS26522_RCR1_E1_HDB3    0x40
0088 #define DS26522_RCR1_E1_CCS 0x20
0089
0090 #define DS26522_RIOCR_1544KHZ   0x00
0091 #define DS26522_RIOCR_2048KHZ   0x10
0092 #define DS26522_RIOCR_RSIO_OUT  0x00
0093
0094 #define DS26522_RCR3_FLB    0x01
0095
0096 #define DS26522_TIOCR_1544KHZ   0x00
0097 #define DS26522_TIOCR_2048KHZ   0x10
0098 #define DS26522_TIOCR_TSIO_OUT  0x04
0099
0100 #define DS26522_TCR1_TB8ZS  0x04
0101
0102 #define DS26522_LTRCR_T1    0x02
0103 #define DS26522_LTRCR_E1    0x00
0104
0105 #define DS26522_LTITSR_TLIS_75OHM   0x00
0106 #define DS26522_LTITSR_LBOS_75OHM   0x00
0107 #define DS26522_LTITSR_TLIS_100OHM  0x10
0108 #define DS26522_LTITSR_TLIS_0DB_CSU 0x00
0109
0110 #define DS26522_LRISMR_75OHM    0x00
0111 #define DS26522_LRISMR_100OHM   0x10
0112 #define DS26522_LRISMR_MAX  0x03
0113
0114 #define DS26522_LMCR_TE 0x01
0115
0116 enum line_rate {
0117     LINE_RATE_T1,   /* T1 line rate (1.544 Mbps)      */
0118     LINE_RATE_E1    /* E1 line rate (2.048 Mbps)     */
0119 };
0120
0121 enum tdm_trans_mode {
0122     NORMAL = 0,
0123     FRAMER_LB
0124 };
0125
0126 enum card_support_type {
0127     LM_CARD = 0,
0128     DS26522_CARD,
0129     NO_CARD
0130 };