net/wan/slic_ds26522.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * drivers/net/wan/slic_ds26522.c
0004  *
0005  * Copyright (C) 2016 Freescale Semiconductor, Inc.
0006  *
0007  * Author:Zhao Qiang<qiang.zhao@nxp.com>
0008  */
0009
0010 #include <linux/bitrev.h>
0011 #include <linux/module.h>
0012 #include <linux/device.h>
0013 #include <linux/kernel.h>
0014 #include <linux/sched.h>
0015 #include <linux/kthread.h>
0016 #include <linux/spi/spi.h>
0017 #include <linux/wait.h>
0018 #include <linux/param.h>
0019 #include <linux/delay.h>
0020 #include <linux/of.h>
0021 #include <linux/of_address.h>
0022 #include <linux/io.h>
0023 #include "slic_ds26522.h"
0024
0025 #define SLIC_TRANS_LEN 1
0026 #define SLIC_TWO_LEN 2
0027 #define SLIC_THREE_LEN 3
0028
0029 static struct spi_device *g_spi;
0030
0031 MODULE_LICENSE("GPL");
0032 MODULE_AUTHOR("Zhao Qiang<B45475@freescale.com>");
0033
0034 /* the read/write format of address is
0035  * w/r|A13|A12|A11|A10|A9|A8|A7|A6|A5|A4|A3|A2|A1|A0|x
0036  */
0037 static void slic_write(struct spi_device *spi, u16 addr,
0038                u8 data)
0039 {
0040     u8 temp[3];
0041
0042     addr = bitrev16(addr) >> 1;
0043     data = bitrev8(data);
0044     temp[0] = (u8)((addr >> 8) & 0x7f);
0045     temp[1] = (u8)(addr & 0xfe);
0046     temp[2] = data;
0047
0048     /* write spi addr and value */
0049     spi_write(spi, &temp[0], SLIC_THREE_LEN);
0050 }
0051
0052 static u8 slic_read(struct spi_device *spi, u16 addr)
0053 {
0054     u8 temp[2];
0055     u8 data;
0056
0057     addr = bitrev16(addr) >> 1;
0058     temp[0] = (u8)(((addr >> 8) & 0x7f) | 0x80);
0059     temp[1] = (u8)(addr & 0xfe);
0060
0061     spi_write_then_read(spi, &temp[0], SLIC_TWO_LEN, &data,
0062                 SLIC_TRANS_LEN);
0063
0064     data = bitrev8(data);
0065     return data;
0066 }
0067
0068 static bool get_slic_product_code(struct spi_device *spi)
0069 {
0070     u8 device_id;
0071
0072     device_id = slic_read(spi, DS26522_IDR_ADDR);
0073     if ((device_id & 0xf8) == 0x68)
0074         return true;
0075     else
0076         return false;
0077 }
0078
0079 static void ds26522_e1_spec_config(struct spi_device *spi)
0080 {
0081     /* Receive E1 Mode, Framer Disabled */
0082     slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_E1);
0083
0084     /* Transmit E1 Mode, Framer Disable */
0085     slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_E1);
0086
0087     /* Receive E1 Mode Framer Enable */
0088     slic_write(spi, DS26522_RMMR_ADDR,
0089            slic_read(spi, DS26522_RMMR_ADDR) | DS26522_RMMR_FRM_EN);
0090
0091     /* Transmit E1 Mode Framer Enable */
0092     slic_write(spi, DS26522_TMMR_ADDR,
0093            slic_read(spi, DS26522_TMMR_ADDR) | DS26522_TMMR_FRM_EN);
0094
0095     /* RCR1, receive E1 B8zs & ESF */
0096     slic_write(spi, DS26522_RCR1_ADDR,
0097            DS26522_RCR1_E1_HDB3 | DS26522_RCR1_E1_CCS);
0098
0099     /* RSYSCLK=2.048MHz, RSYNC-Output */
0100     slic_write(spi, DS26522_RIOCR_ADDR,
0101            DS26522_RIOCR_2048KHZ | DS26522_RIOCR_RSIO_OUT);
0102
0103     /* TCR1 Transmit E1 b8zs */
0104     slic_write(spi, DS26522_TCR1_ADDR, DS26522_TCR1_TB8ZS);
0105
0106     /* TSYSCLK=2.048MHz, TSYNC-Output */
0107     slic_write(spi, DS26522_TIOCR_ADDR,
0108            DS26522_TIOCR_2048KHZ | DS26522_TIOCR_TSIO_OUT);
0109
0110     /* Set E1TAF */
0111     slic_write(spi, DS26522_E1TAF_ADDR, DS26522_E1TAF_DEFAULT);
0112
0113     /* Set E1TNAF register */
0114     slic_write(spi, DS26522_E1TNAF_ADDR, DS26522_E1TNAF_DEFAULT);
0115
0116     /* Receive E1 Mode Framer Enable & init Done */
0117     slic_write(spi, DS26522_RMMR_ADDR, slic_read(spi, DS26522_RMMR_ADDR) |
0118            DS26522_RMMR_INIT_DONE);
0119
0120     /* Transmit E1 Mode Framer Enable & init Done */
0121     slic_write(spi, DS26522_TMMR_ADDR, slic_read(spi, DS26522_TMMR_ADDR) |
0122            DS26522_TMMR_INIT_DONE);
0123
0124     /* Configure LIU E1 mode */
0125     slic_write(spi, DS26522_LTRCR_ADDR, DS26522_LTRCR_E1);
0126
0127     /* E1 Mode default 75 ohm w/Transmit Impedance Matlinking */
0128     slic_write(spi, DS26522_LTITSR_ADDR,
0129            DS26522_LTITSR_TLIS_75OHM | DS26522_LTITSR_LBOS_75OHM);
0130
0131     /* E1 Mode default 75 ohm Long Haul w/Receive Impedance Matlinking */
0132     slic_write(spi, DS26522_LRISMR_ADDR,
0133            DS26522_LRISMR_75OHM | DS26522_LRISMR_MAX);
0134
0135     /* Enable Transmit output */
0136     slic_write(spi, DS26522_LMCR_ADDR, DS26522_LMCR_TE);
0137 }
0138
0139 static int slic_ds26522_init_configure(struct spi_device *spi)
0140 {
0141     u16 addr;
0142
0143     /* set clock */
0144     slic_write(spi, DS26522_GTCCR_ADDR, DS26522_GTCCR_BPREFSEL_REFCLKIN |
0145             DS26522_GTCCR_BFREQSEL_2048KHZ |
0146             DS26522_GTCCR_FREQSEL_2048KHZ);
0147     slic_write(spi, DS26522_GTCR2_ADDR, DS26522_GTCR2_TSSYNCOUT);
0148     slic_write(spi, DS26522_GFCR_ADDR, DS26522_GFCR_BPCLK_2048KHZ);
0149
0150     /* set gtcr */
0151     slic_write(spi, DS26522_GTCR1_ADDR, DS26522_GTCR1);
0152
0153     /* Global LIU Software Reset Register */
0154     slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_RESET);
0155
0156     /* Global Framer and BERT Software Reset Register */
0157     slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_RESET);
0158
0159     usleep_range(100, 120);
0160
0161     slic_write(spi, DS26522_GLSRR_ADDR, DS26522_GLSRR_NORMAL);
0162     slic_write(spi, DS26522_GFSRR_ADDR, DS26522_GFSRR_NORMAL);
0163
0164     /* Perform RX/TX SRESET,Reset receiver */
0165     slic_write(spi, DS26522_RMMR_ADDR, DS26522_RMMR_SFTRST);
0166
0167     /* Reset tranceiver */
0168     slic_write(spi, DS26522_TMMR_ADDR, DS26522_TMMR_SFTRST);
0169
0170     usleep_range(100, 120);
0171
0172     /* Zero all Framer Registers */
0173     for (addr = DS26522_RF_ADDR_START; addr <= DS26522_RF_ADDR_END;
0174          addr++)
0175         slic_write(spi, addr, 0);
0176
0177     for (addr = DS26522_TF_ADDR_START; addr <= DS26522_TF_ADDR_END;
0178          addr++)
0179         slic_write(spi, addr, 0);
0180
0181     for (addr = DS26522_LIU_ADDR_START; addr <= DS26522_LIU_ADDR_END;
0182          addr++)
0183         slic_write(spi, addr, 0);
0184
0185     for (addr = DS26522_BERT_ADDR_START; addr <= DS26522_BERT_ADDR_END;
0186          addr++)
0187         slic_write(spi, addr, 0);
0188
0189     /* setup ds26522 for E1 specification */
0190     ds26522_e1_spec_config(spi);
0191
0192     slic_write(spi, DS26522_GTCR1_ADDR, 0x00);
0193
0194     return 0;
0195 }
0196
0197 static void slic_ds26522_remove(struct spi_device *spi)
0198 {
0199     pr_info("DS26522 module uninstalled\n");
0200 }
0201
0202 static int slic_ds26522_probe(struct spi_device *spi)
0203 {
0204     int ret = 0;
0205
0206     g_spi = spi;
0207     spi->bits_per_word = 8;
0208
0209     if (!get_slic_product_code(spi))
0210         return ret;
0211
0212     ret = slic_ds26522_init_configure(spi);
0213     if (ret == 0)
0214         pr_info("DS26522 cs%d configured\n", spi->chip_select);
0215
0216     return ret;
0217 }
0218
0219 static const struct spi_device_id slic_ds26522_id[] = {
0220     { .name = "ds26522" },
0221     { /* sentinel */ },
0222 };
0223 MODULE_DEVICE_TABLE(spi, slic_ds26522_id);
0224
0225 static const struct of_device_id slic_ds26522_match[] = {
0226     {
0227      .compatible = "maxim,ds26522",
0228      },
0229     {},
0230 };
0231 MODULE_DEVICE_TABLE(of, slic_ds26522_match);
0232
0233 static struct spi_driver slic_ds26522_driver = {
0234     .driver = {
0235            .name = "ds26522",
0236            .bus = &spi_bus_type,
0237            .of_match_table = slic_ds26522_match,
0238            },
0239     .probe = slic_ds26522_probe,
0240     .remove = slic_ds26522_remove,
0241     .id_table = slic_ds26522_id,
0242 };
0243
0244 module_spi_driver(slic_ds26522_driver);