net/wan/pci200syn.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Goramo PCI200SYN synchronous serial card driver for Linux
0004  *
0005  * Copyright (C) 2002-2008 Krzysztof Halasa <khc@pm.waw.pl>
0006  *
0007  * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>
0008  *
0009  * Sources of information:
0010  *    Hitachi HD64572 SCA-II User's Manual
0011  *    PLX Technology Inc. PCI9052 Data Book
0012  */
0013
0014 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0015
0016 #include <linux/module.h>
0017 #include <linux/kernel.h>
0018 #include <linux/capability.h>
0019 #include <linux/slab.h>
0020 #include <linux/types.h>
0021 #include <linux/fcntl.h>
0022 #include <linux/in.h>
0023 #include <linux/string.h>
0024 #include <linux/errno.h>
0025 #include <linux/init.h>
0026 #include <linux/ioport.h>
0027 #include <linux/netdevice.h>
0028 #include <linux/hdlc.h>
0029 #include <linux/pci.h>
0030 #include <linux/delay.h>
0031 #include <asm/io.h>
0032
0033 #include "hd64572.h"
0034
0035 #undef DEBUG_PKT
0036 #define DEBUG_RINGS
0037
0038 #define PCI200SYN_PLX_SIZE  0x80    /* PLX control window size (128b) */
0039 #define PCI200SYN_SCA_SIZE  0x400   /* SCA window size (1Kb) */
0040 #define MAX_TX_BUFFERS      10
0041
0042 static int pci_clock_freq = 33000000;
0043 #define CLOCK_BASE pci_clock_freq
0044
0045 /*      PLX PCI9052 local configuration and shared runtime registers.
0046  *      This structure can be used to access 9052 registers (memory mapped).
0047  */
0048 typedef struct {
0049     u32 loc_addr_range[4];  /* 00-0Ch : Local Address Ranges */
0050     u32 loc_rom_range;  /* 10h : Local ROM Range */
0051     u32 loc_addr_base[4];   /* 14-20h : Local Address Base Addrs */
0052     u32 loc_rom_base;   /* 24h : Local ROM Base */
0053     u32 loc_bus_descr[4];   /* 28-34h : Local Bus Descriptors */
0054     u32 rom_bus_descr;  /* 38h : ROM Bus Descriptor */
0055     u32 cs_base[4];     /* 3C-48h : Chip Select Base Addrs */
0056     u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
0057     u32 init_ctrl;      /* 50h : EEPROM ctrl, Init Ctrl, etc */
0058 } plx9052;
0059
0060 typedef struct port_s {
0061     struct napi_struct napi;
0062     struct net_device *netdev;
0063     struct card_s *card;
0064     spinlock_t lock;    /* TX lock */
0065     sync_serial_settings settings;
0066     int rxpart;     /* partial frame received, next frame invalid*/
0067     unsigned short encoding;
0068     unsigned short parity;
0069     u16 rxin;       /* rx ring buffer 'in' pointer */
0070     u16 txin;       /* tx ring buffer 'in' and 'last' pointers */
0071     u16 txlast;
0072     u8 rxs, txs, tmc;   /* SCA registers */
0073     u8 chan;        /* physical port # - 0 or 1 */
0074 } port_t;
0075
0076 typedef struct card_s {
0077     u8 __iomem *rambase;    /* buffer memory base (virtual) */
0078     u8 __iomem *scabase;    /* SCA memory base (virtual) */
0079     plx9052 __iomem *plxbase;/* PLX registers memory base (virtual) */
0080     u16 rx_ring_buffers;    /* number of buffers in a ring */
0081     u16 tx_ring_buffers;
0082     u16 buff_offset;    /* offset of first buffer of first channel */
0083     u8 irq;         /* interrupt request level */
0084
0085     port_t ports[2];
0086 } card_t;
0087
0088 #define get_port(card, port)         (&(card)->ports[port])
0089 #define sca_flush(card)          (sca_in(IER0, card))
0090
0091 static inline void new_memcpy_toio(char __iomem *dest, char *src, int length)
0092 {
0093     int len;
0094
0095     do {
0096         len = length > 256 ? 256 : length;
0097         memcpy_toio(dest, src, len);
0098         dest += len;
0099         src += len;
0100         length -= len;
0101         readb(dest);
0102     } while (len);
0103 }
0104
0105 #undef memcpy_toio
0106 #define memcpy_toio new_memcpy_toio
0107
0108 #include "hd64572.c"
0109
0110 static void pci200_set_iface(port_t *port)
0111 {
0112     card_t *card = port->card;
0113     u16 msci = get_msci(port);
0114     u8 rxs = port->rxs & CLK_BRG_MASK;
0115     u8 txs = port->txs & CLK_BRG_MASK;
0116
0117     sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
0118         port->card);
0119     switch (port->settings.clock_type) {
0120     case CLOCK_INT:
0121         rxs |= CLK_BRG; /* BRG output */
0122         txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
0123         break;
0124
0125     case CLOCK_TXINT:
0126         rxs |= CLK_LINE; /* RXC input */
0127         txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
0128         break;
0129
0130     case CLOCK_TXFROMRX:
0131         rxs |= CLK_LINE; /* RXC input */
0132         txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
0133         break;
0134
0135     default:        /* EXTernal clock */
0136         rxs |= CLK_LINE; /* RXC input */
0137         txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
0138         break;
0139     }
0140
0141     port->rxs = rxs;
0142     port->txs = txs;
0143     sca_out(rxs, msci + RXS, card);
0144     sca_out(txs, msci + TXS, card);
0145     sca_set_port(port);
0146 }
0147
0148 static int pci200_open(struct net_device *dev)
0149 {
0150     port_t *port = dev_to_port(dev);
0151     int result = hdlc_open(dev);
0152
0153     if (result)
0154         return result;
0155
0156     sca_open(dev);
0157     pci200_set_iface(port);
0158     sca_flush(port->card);
0159     return 0;
0160 }
0161
0162 static int pci200_close(struct net_device *dev)
0163 {
0164     sca_close(dev);
0165     sca_flush(dev_to_port(dev)->card);
0166     hdlc_close(dev);
0167     return 0;
0168 }
0169
0170 static int pci200_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
0171                  void __user *data, int cmd)
0172 {
0173 #ifdef DEBUG_RINGS
0174     if (cmd == SIOCDEVPRIVATE) {
0175         sca_dump_rings(dev);
0176         return 0;
0177     }
0178 #endif
0179     return -EOPNOTSUPP;
0180 }
0181
0182 static int pci200_ioctl(struct net_device *dev, struct if_settings *ifs)
0183 {
0184     const size_t size = sizeof(sync_serial_settings);
0185     sync_serial_settings new_line;
0186     sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
0187     port_t *port = dev_to_port(dev);
0188
0189     switch (ifs->type) {
0190     case IF_GET_IFACE:
0191         ifs->type = IF_IFACE_V35;
0192         if (ifs->size < size) {
0193             ifs->size = size; /* data size wanted */
0194             return -ENOBUFS;
0195         }
0196         if (copy_to_user(line, &port->settings, size))
0197             return -EFAULT;
0198         return 0;
0199
0200     case IF_IFACE_V35:
0201     case IF_IFACE_SYNC_SERIAL:
0202         if (!capable(CAP_NET_ADMIN))
0203             return -EPERM;
0204
0205         if (copy_from_user(&new_line, line, size))
0206             return -EFAULT;
0207
0208         if (new_line.clock_type != CLOCK_EXT &&
0209             new_line.clock_type != CLOCK_TXFROMRX &&
0210             new_line.clock_type != CLOCK_INT &&
0211             new_line.clock_type != CLOCK_TXINT)
0212             return -EINVAL; /* No such clock setting */
0213
0214         if (new_line.loopback != 0 && new_line.loopback != 1)
0215             return -EINVAL;
0216
0217         memcpy(&port->settings, &new_line, size); /* Update settings */
0218         pci200_set_iface(port);
0219         sca_flush(port->card);
0220         return 0;
0221
0222     default:
0223         return hdlc_ioctl(dev, ifs);
0224     }
0225 }
0226
0227 static void pci200_pci_remove_one(struct pci_dev *pdev)
0228 {
0229     int i;
0230     card_t *card = pci_get_drvdata(pdev);
0231
0232     for (i = 0; i < 2; i++)
0233         if (card->ports[i].card)
0234             unregister_hdlc_device(card->ports[i].netdev);
0235
0236     if (card->irq)
0237         free_irq(card->irq, card);
0238
0239     if (card->rambase)
0240         iounmap(card->rambase);
0241     if (card->scabase)
0242         iounmap(card->scabase);
0243     if (card->plxbase)
0244         iounmap(card->plxbase);
0245
0246     pci_release_regions(pdev);
0247     pci_disable_device(pdev);
0248     if (card->ports[0].netdev)
0249         free_netdev(card->ports[0].netdev);
0250     if (card->ports[1].netdev)
0251         free_netdev(card->ports[1].netdev);
0252     kfree(card);
0253 }
0254
0255 static const struct net_device_ops pci200_ops = {
0256     .ndo_open       = pci200_open,
0257     .ndo_stop       = pci200_close,
0258     .ndo_start_xmit = hdlc_start_xmit,
0259     .ndo_siocwandev = pci200_ioctl,
0260     .ndo_siocdevprivate = pci200_siocdevprivate,
0261 };
0262
0263 static int pci200_pci_init_one(struct pci_dev *pdev,
0264                    const struct pci_device_id *ent)
0265 {
0266     card_t *card;
0267     u32 __iomem *p;
0268     int i;
0269     u32 ramsize;
0270     u32 ramphys;        /* buffer memory base */
0271     u32 scaphys;        /* SCA memory base */
0272     u32 plxphys;        /* PLX registers memory base */
0273
0274     i = pci_enable_device(pdev);
0275     if (i)
0276         return i;
0277
0278     i = pci_request_regions(pdev, "PCI200SYN");
0279     if (i) {
0280         pci_disable_device(pdev);
0281         return i;
0282     }
0283
0284     card = kzalloc(sizeof(card_t), GFP_KERNEL);
0285     if (!card) {
0286         pci_release_regions(pdev);
0287         pci_disable_device(pdev);
0288         return -ENOBUFS;
0289     }
0290     pci_set_drvdata(pdev, card);
0291     card->ports[0].netdev = alloc_hdlcdev(&card->ports[0]);
0292     card->ports[1].netdev = alloc_hdlcdev(&card->ports[1]);
0293     if (!card->ports[0].netdev || !card->ports[1].netdev) {
0294         pr_err("unable to allocate memory\n");
0295         pci200_pci_remove_one(pdev);
0296         return -ENOMEM;
0297     }
0298
0299     if (pci_resource_len(pdev, 0) != PCI200SYN_PLX_SIZE ||
0300         pci_resource_len(pdev, 2) != PCI200SYN_SCA_SIZE ||
0301         pci_resource_len(pdev, 3) < 16384) {
0302         pr_err("invalid card EEPROM parameters\n");
0303         pci200_pci_remove_one(pdev);
0304         return -EFAULT;
0305     }
0306
0307     plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
0308     card->plxbase = ioremap(plxphys, PCI200SYN_PLX_SIZE);
0309
0310     scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
0311     card->scabase = ioremap(scaphys, PCI200SYN_SCA_SIZE);
0312
0313     ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
0314     card->rambase = pci_ioremap_bar(pdev, 3);
0315
0316     if (!card->plxbase || !card->scabase || !card->rambase) {
0317         pr_err("ioremap() failed\n");
0318         pci200_pci_remove_one(pdev);
0319         return -EFAULT;
0320     }
0321
0322     /* Reset PLX */
0323     p = &card->plxbase->init_ctrl;
0324     writel(readl(p) | 0x40000000, p);
0325     readl(p);       /* Flush the write - do not use sca_flush */
0326     udelay(1);
0327
0328     writel(readl(p) & ~0x40000000, p);
0329     readl(p);       /* Flush the write - do not use sca_flush */
0330     udelay(1);
0331
0332     ramsize = sca_detect_ram(card, card->rambase,
0333                  pci_resource_len(pdev, 3));
0334
0335     /* number of TX + RX buffers for one port - this is dual port card */
0336     i = ramsize / (2 * (sizeof(pkt_desc) + HDLC_MAX_MRU));
0337     card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
0338     card->rx_ring_buffers = i - card->tx_ring_buffers;
0339
0340     card->buff_offset = 2 * sizeof(pkt_desc) * (card->tx_ring_buffers +
0341                             card->rx_ring_buffers);
0342
0343     pr_info("%u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
0344         ramsize / 1024, ramphys,
0345         pdev->irq, card->tx_ring_buffers, card->rx_ring_buffers);
0346
0347     if (card->tx_ring_buffers < 1) {
0348         pr_err("RAM test failed\n");
0349         pci200_pci_remove_one(pdev);
0350         return -EFAULT;
0351     }
0352
0353     /* Enable interrupts on the PCI bridge */
0354     p = &card->plxbase->intr_ctrl_stat;
0355     writew(readw(p) | 0x0040, p);
0356
0357     /* Allocate IRQ */
0358     if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pci200syn", card)) {
0359         pr_warn("could not allocate IRQ%d\n", pdev->irq);
0360         pci200_pci_remove_one(pdev);
0361         return -EBUSY;
0362     }
0363     card->irq = pdev->irq;
0364
0365     sca_init(card, 0);
0366
0367     for (i = 0; i < 2; i++) {
0368         port_t *port = &card->ports[i];
0369         struct net_device *dev = port->netdev;
0370         hdlc_device *hdlc = dev_to_hdlc(dev);
0371
0372         port->chan = i;
0373
0374         spin_lock_init(&port->lock);
0375         dev->irq = card->irq;
0376         dev->mem_start = ramphys;
0377         dev->mem_end = ramphys + ramsize - 1;
0378         dev->tx_queue_len = 50;
0379         dev->netdev_ops = &pci200_ops;
0380         hdlc->attach = sca_attach;
0381         hdlc->xmit = sca_xmit;
0382         port->settings.clock_type = CLOCK_EXT;
0383         port->card = card;
0384         sca_init_port(port);
0385         if (register_hdlc_device(dev)) {
0386             pr_err("unable to register hdlc device\n");
0387             port->card = NULL;
0388             pci200_pci_remove_one(pdev);
0389             return -ENOBUFS;
0390         }
0391
0392         netdev_info(dev, "PCI200SYN channel %d\n", port->chan);
0393     }
0394
0395     sca_flush(card);
0396     return 0;
0397 }
0398
0399 static const struct pci_device_id pci200_pci_tbl[] = {
0400     { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, PCI_VENDOR_ID_PLX,
0401       PCI_DEVICE_ID_PLX_PCI200SYN, 0, 0, 0 },
0402     { 0, }
0403 };
0404
0405 static struct pci_driver pci200_pci_driver = {
0406     .name       = "PCI200SYN",
0407     .id_table   = pci200_pci_tbl,
0408     .probe      = pci200_pci_init_one,
0409     .remove     = pci200_pci_remove_one,
0410 };
0411
0412 static int __init pci200_init_module(void)
0413 {
0414     if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
0415         pr_err("Invalid PCI clock frequency\n");
0416         return -EINVAL;
0417     }
0418     return pci_register_driver(&pci200_pci_driver);
0419 }
0420
0421 static void __exit pci200_cleanup_module(void)
0422 {
0423     pci_unregister_driver(&pci200_pci_driver);
0424 }
0425
0426 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
0427 MODULE_DESCRIPTION("Goramo PCI200SYN serial port driver");
0428 MODULE_LICENSE("GPL v2");
0429 MODULE_DEVICE_TABLE(pci, pci200_pci_tbl);
0430 module_param(pci_clock_freq, int, 0444);
0431 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
0432 module_init(pci200_init_module);
0433 module_exit(pci200_cleanup_module);