net/wan/pc300too.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Cyclades PC300 synchronous serial card driver for Linux
0004  *
0005  * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
0006  *
0007  * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>.
0008  *
0009  * Sources of information:
0010  *    Hitachi HD64572 SCA-II User's Manual
0011  *    Original Cyclades PC300 Linux driver
0012  *
0013  * This driver currently supports only PC300/RSV (V.24/V.35) and
0014  * PC300/X21 cards.
0015  */
0016
0017 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0018
0019 #include <linux/module.h>
0020 #include <linux/kernel.h>
0021 #include <linux/slab.h>
0022 #include <linux/sched.h>
0023 #include <linux/types.h>
0024 #include <linux/fcntl.h>
0025 #include <linux/in.h>
0026 #include <linux/string.h>
0027 #include <linux/errno.h>
0028 #include <linux/init.h>
0029 #include <linux/ioport.h>
0030 #include <linux/moduleparam.h>
0031 #include <linux/netdevice.h>
0032 #include <linux/hdlc.h>
0033 #include <linux/pci.h>
0034 #include <linux/delay.h>
0035 #include <asm/io.h>
0036
0037 #include "hd64572.h"
0038
0039 #undef DEBUG_PKT
0040 #define DEBUG_RINGS
0041
0042 #define PC300_PLX_SIZE      0x80    /* PLX control window size (128 B) */
0043 #define PC300_SCA_SIZE      0x400   /* SCA window size (1 KB) */
0044 #define MAX_TX_BUFFERS      10
0045
0046 static int pci_clock_freq = 33000000;
0047 static int use_crystal_clock;
0048 static unsigned int CLOCK_BASE;
0049
0050 /* Masks to access the init_ctrl PLX register */
0051 #define PC300_CLKSEL_MASK    (0x00000004UL)
0052 #define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
0053 #define PC300_CTYPE_MASK     (0x00000800UL)
0054
0055 enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
0056
0057 /*      PLX PCI9050-1 local configuration and shared runtime registers.
0058  *      This structure can be used to access 9050 registers (memory mapped).
0059  */
0060 typedef struct {
0061     u32 loc_addr_range[4];  /* 00-0Ch : Local Address Ranges */
0062     u32 loc_rom_range;  /* 10h : Local ROM Range */
0063     u32 loc_addr_base[4];   /* 14-20h : Local Address Base Addrs */
0064     u32 loc_rom_base;   /* 24h : Local ROM Base */
0065     u32 loc_bus_descr[4];   /* 28-34h : Local Bus Descriptors */
0066     u32 rom_bus_descr;  /* 38h : ROM Bus Descriptor */
0067     u32 cs_base[4];     /* 3C-48h : Chip Select Base Addrs */
0068     u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
0069     u32 init_ctrl;      /* 50h : EEPROM ctrl, Init Ctrl, etc */
0070 } plx9050;
0071
0072 typedef struct port_s {
0073     struct napi_struct napi;
0074     struct net_device *netdev;
0075     struct card_s *card;
0076     spinlock_t lock;    /* TX lock */
0077     sync_serial_settings settings;
0078     int rxpart;     /* partial frame received, next frame invalid*/
0079     unsigned short encoding;
0080     unsigned short parity;
0081     unsigned int iface;
0082     u16 rxin;       /* rx ring buffer 'in' pointer */
0083     u16 txin;       /* tx ring buffer 'in' and 'last' pointers */
0084     u16 txlast;
0085     u8 rxs, txs, tmc;   /* SCA registers */
0086     u8 chan;        /* physical port # - 0 or 1 */
0087 } port_t;
0088
0089 typedef struct card_s {
0090     int type;       /* RSV, X21, etc. */
0091     int n_ports;        /* 1 or 2 ports */
0092     u8 __iomem *rambase;    /* buffer memory base (virtual) */
0093     u8 __iomem *scabase;    /* SCA memory base (virtual) */
0094     plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
0095     u32 init_ctrl_value;    /* Saved value - 9050 bug workaround */
0096     u16 rx_ring_buffers;    /* number of buffers in a ring */
0097     u16 tx_ring_buffers;
0098     u16 buff_offset;    /* offset of first buffer of first channel */
0099     u8 irq;         /* interrupt request level */
0100
0101     port_t ports[2];
0102 } card_t;
0103
0104 #define get_port(card, port)         ((port) < (card)->n_ports ? \
0105                      (&(card)->ports[port]) : (NULL))
0106
0107 #include "hd64572.c"
0108
0109 static void pc300_set_iface(port_t *port)
0110 {
0111     card_t *card = port->card;
0112     u32 __iomem *init_ctrl = &card->plxbase->init_ctrl;
0113     u16 msci = get_msci(port);
0114     u8 rxs = port->rxs & CLK_BRG_MASK;
0115     u8 txs = port->txs & CLK_BRG_MASK;
0116
0117     sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
0118         port->card);
0119     switch (port->settings.clock_type) {
0120     case CLOCK_INT:
0121         rxs |= CLK_BRG; /* BRG output */
0122         txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
0123         break;
0124
0125     case CLOCK_TXINT:
0126         rxs |= CLK_LINE; /* RXC input */
0127         txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
0128         break;
0129
0130     case CLOCK_TXFROMRX:
0131         rxs |= CLK_LINE; /* RXC input */
0132         txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
0133         break;
0134
0135     default:        /* EXTernal clock */
0136         rxs |= CLK_LINE; /* RXC input */
0137         txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
0138         break;
0139     }
0140
0141     port->rxs = rxs;
0142     port->txs = txs;
0143     sca_out(rxs, msci + RXS, card);
0144     sca_out(txs, msci + TXS, card);
0145     sca_set_port(port);
0146
0147     if (port->card->type == PC300_RSV) {
0148         if (port->iface == IF_IFACE_V35)
0149             writel(card->init_ctrl_value |
0150                    PC300_CHMEDIA_MASK(port->chan), init_ctrl);
0151         else
0152             writel(card->init_ctrl_value &
0153                    ~PC300_CHMEDIA_MASK(port->chan), init_ctrl);
0154     }
0155 }
0156
0157 static int pc300_open(struct net_device *dev)
0158 {
0159     port_t *port = dev_to_port(dev);
0160     int result = hdlc_open(dev);
0161
0162     if (result)
0163         return result;
0164
0165     sca_open(dev);
0166     pc300_set_iface(port);
0167     return 0;
0168 }
0169
0170 static int pc300_close(struct net_device *dev)
0171 {
0172     sca_close(dev);
0173     hdlc_close(dev);
0174     return 0;
0175 }
0176
0177 static int pc300_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
0178                 void __user *data, int cmd)
0179 {
0180 #ifdef DEBUG_RINGS
0181     if (cmd == SIOCDEVPRIVATE) {
0182         sca_dump_rings(dev);
0183         return 0;
0184     }
0185 #endif
0186     return -EOPNOTSUPP;
0187 }
0188
0189 static int pc300_ioctl(struct net_device *dev, struct if_settings *ifs)
0190 {
0191     const size_t size = sizeof(sync_serial_settings);
0192     sync_serial_settings new_line;
0193     sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
0194     int new_type;
0195     port_t *port = dev_to_port(dev);
0196
0197     if (ifs->type == IF_GET_IFACE) {
0198         ifs->type = port->iface;
0199         if (ifs->size < size) {
0200             ifs->size = size; /* data size wanted */
0201             return -ENOBUFS;
0202         }
0203         if (copy_to_user(line, &port->settings, size))
0204             return -EFAULT;
0205         return 0;
0206     }
0207
0208     if (port->card->type == PC300_X21 &&
0209         (ifs->type == IF_IFACE_SYNC_SERIAL ||
0210          ifs->type == IF_IFACE_X21))
0211         new_type = IF_IFACE_X21;
0212
0213     else if (port->card->type == PC300_RSV &&
0214          (ifs->type == IF_IFACE_SYNC_SERIAL ||
0215           ifs->type == IF_IFACE_V35))
0216         new_type = IF_IFACE_V35;
0217
0218     else if (port->card->type == PC300_RSV &&
0219          ifs->type == IF_IFACE_V24)
0220         new_type = IF_IFACE_V24;
0221
0222     else
0223         return hdlc_ioctl(dev, ifs);
0224
0225     if (!capable(CAP_NET_ADMIN))
0226         return -EPERM;
0227
0228     if (copy_from_user(&new_line, line, size))
0229         return -EFAULT;
0230
0231     if (new_line.clock_type != CLOCK_EXT &&
0232         new_line.clock_type != CLOCK_TXFROMRX &&
0233         new_line.clock_type != CLOCK_INT &&
0234         new_line.clock_type != CLOCK_TXINT)
0235         return -EINVAL; /* No such clock setting */
0236
0237     if (new_line.loopback != 0 && new_line.loopback != 1)
0238         return -EINVAL;
0239
0240     memcpy(&port->settings, &new_line, size); /* Update settings */
0241     port->iface = new_type;
0242     pc300_set_iface(port);
0243     return 0;
0244 }
0245
0246 static void pc300_pci_remove_one(struct pci_dev *pdev)
0247 {
0248     int i;
0249     card_t *card = pci_get_drvdata(pdev);
0250
0251     for (i = 0; i < 2; i++)
0252         if (card->ports[i].card)
0253             unregister_hdlc_device(card->ports[i].netdev);
0254
0255     if (card->irq)
0256         free_irq(card->irq, card);
0257
0258     if (card->rambase)
0259         iounmap(card->rambase);
0260     if (card->scabase)
0261         iounmap(card->scabase);
0262     if (card->plxbase)
0263         iounmap(card->plxbase);
0264
0265     pci_release_regions(pdev);
0266     pci_disable_device(pdev);
0267     if (card->ports[0].netdev)
0268         free_netdev(card->ports[0].netdev);
0269     if (card->ports[1].netdev)
0270         free_netdev(card->ports[1].netdev);
0271     kfree(card);
0272 }
0273
0274 static const struct net_device_ops pc300_ops = {
0275     .ndo_open       = pc300_open,
0276     .ndo_stop       = pc300_close,
0277     .ndo_start_xmit = hdlc_start_xmit,
0278     .ndo_siocwandev = pc300_ioctl,
0279     .ndo_siocdevprivate = pc300_siocdevprivate,
0280 };
0281
0282 static int pc300_pci_init_one(struct pci_dev *pdev,
0283                   const struct pci_device_id *ent)
0284 {
0285     card_t *card;
0286     u32 __iomem *p;
0287     int i;
0288     u32 ramsize;
0289     u32 ramphys;        /* buffer memory base */
0290     u32 scaphys;        /* SCA memory base */
0291     u32 plxphys;        /* PLX registers memory base */
0292
0293     i = pci_enable_device(pdev);
0294     if (i)
0295         return i;
0296
0297     i = pci_request_regions(pdev, "PC300");
0298     if (i) {
0299         pci_disable_device(pdev);
0300         return i;
0301     }
0302
0303     card = kzalloc(sizeof(card_t), GFP_KERNEL);
0304     if (!card) {
0305         pci_release_regions(pdev);
0306         pci_disable_device(pdev);
0307         return -ENOBUFS;
0308     }
0309     pci_set_drvdata(pdev, card);
0310
0311     if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
0312         pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
0313         pci_resource_len(pdev, 3) < 16384) {
0314         pr_err("invalid card EEPROM parameters\n");
0315         pc300_pci_remove_one(pdev);
0316         return -EFAULT;
0317     }
0318
0319     plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
0320     card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
0321
0322     scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
0323     card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
0324
0325     ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
0326     card->rambase = pci_ioremap_bar(pdev, 3);
0327
0328     if (!card->plxbase || !card->scabase || !card->rambase) {
0329         pr_err("ioremap() failed\n");
0330         pc300_pci_remove_one(pdev);
0331         return -ENOMEM;
0332     }
0333
0334     /* PLX PCI 9050 workaround for local configuration register read bug */
0335     pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
0336     card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
0337     pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
0338
0339     if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
0340         pdev->device == PCI_DEVICE_ID_PC300_TE_2)
0341         card->type = PC300_TE; /* not fully supported */
0342     else if (card->init_ctrl_value & PC300_CTYPE_MASK)
0343         card->type = PC300_X21;
0344     else
0345         card->type = PC300_RSV;
0346
0347     if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
0348         pdev->device == PCI_DEVICE_ID_PC300_TE_1)
0349         card->n_ports = 1;
0350     else
0351         card->n_ports = 2;
0352
0353     for (i = 0; i < card->n_ports; i++) {
0354         card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]);
0355         if (!card->ports[i].netdev) {
0356             pr_err("unable to allocate memory\n");
0357             pc300_pci_remove_one(pdev);
0358             return -ENOMEM;
0359         }
0360     }
0361
0362     /* Reset PLX */
0363     p = &card->plxbase->init_ctrl;
0364     writel(card->init_ctrl_value | 0x40000000, p);
0365     readl(p);       /* Flush the write - do not use sca_flush */
0366     udelay(1);
0367
0368     writel(card->init_ctrl_value, p);
0369     readl(p);       /* Flush the write - do not use sca_flush */
0370     udelay(1);
0371
0372     /* Reload Config. Registers from EEPROM */
0373     writel(card->init_ctrl_value | 0x20000000, p);
0374     readl(p);       /* Flush the write - do not use sca_flush */
0375     udelay(1);
0376
0377     writel(card->init_ctrl_value, p);
0378     readl(p);       /* Flush the write - do not use sca_flush */
0379     udelay(1);
0380
0381     ramsize = sca_detect_ram(card, card->rambase,
0382                  pci_resource_len(pdev, 3));
0383
0384     if (use_crystal_clock)
0385         card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
0386     else
0387         card->init_ctrl_value |= PC300_CLKSEL_MASK;
0388
0389     writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
0390     /* number of TX + RX buffers for one port */
0391     i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
0392     card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
0393     card->rx_ring_buffers = i - card->tx_ring_buffers;
0394
0395     card->buff_offset = card->n_ports * sizeof(pkt_desc) *
0396         (card->tx_ring_buffers + card->rx_ring_buffers);
0397
0398     pr_info("PC300/%s, %u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
0399         card->type == PC300_X21 ? "X21" :
0400         card->type == PC300_TE ? "TE" : "RSV",
0401         ramsize / 1024, ramphys, pdev->irq,
0402         card->tx_ring_buffers, card->rx_ring_buffers);
0403
0404     if (card->tx_ring_buffers < 1) {
0405         pr_err("RAM test failed\n");
0406         pc300_pci_remove_one(pdev);
0407         return -EFAULT;
0408     }
0409
0410     /* Enable interrupts on the PCI bridge, LINTi1 active low */
0411     writew(0x0041, &card->plxbase->intr_ctrl_stat);
0412
0413     /* Allocate IRQ */
0414     if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) {
0415         pr_warn("could not allocate IRQ%d\n", pdev->irq);
0416         pc300_pci_remove_one(pdev);
0417         return -EBUSY;
0418     }
0419     card->irq = pdev->irq;
0420
0421     sca_init(card, 0);
0422
0423     // COTE not set - allows better TX DMA settings
0424     // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
0425
0426     sca_out(0x10, BTCR, card);
0427
0428     for (i = 0; i < card->n_ports; i++) {
0429         port_t *port = &card->ports[i];
0430         struct net_device *dev = port->netdev;
0431         hdlc_device *hdlc = dev_to_hdlc(dev);
0432
0433         port->chan = i;
0434
0435         spin_lock_init(&port->lock);
0436         dev->irq = card->irq;
0437         dev->mem_start = ramphys;
0438         dev->mem_end = ramphys + ramsize - 1;
0439         dev->tx_queue_len = 50;
0440         dev->netdev_ops = &pc300_ops;
0441         hdlc->attach = sca_attach;
0442         hdlc->xmit = sca_xmit;
0443         port->settings.clock_type = CLOCK_EXT;
0444         port->card = card;
0445         if (card->type == PC300_X21)
0446             port->iface = IF_IFACE_X21;
0447         else
0448             port->iface = IF_IFACE_V35;
0449
0450         sca_init_port(port);
0451         if (register_hdlc_device(dev)) {
0452             pr_err("unable to register hdlc device\n");
0453             port->card = NULL;
0454             pc300_pci_remove_one(pdev);
0455             return -ENOBUFS;
0456         }
0457
0458         netdev_info(dev, "PC300 channel %d\n", port->chan);
0459     }
0460     return 0;
0461 }
0462
0463 static const struct pci_device_id pc300_pci_tbl[] = {
0464     { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
0465       PCI_ANY_ID, 0, 0, 0 },
0466     { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
0467       PCI_ANY_ID, 0, 0, 0 },
0468     { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
0469       PCI_ANY_ID, 0, 0, 0 },
0470     { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
0471       PCI_ANY_ID, 0, 0, 0 },
0472     { 0, }
0473 };
0474
0475 static struct pci_driver pc300_pci_driver = {
0476     .name =          "PC300",
0477     .id_table =      pc300_pci_tbl,
0478     .probe =         pc300_pci_init_one,
0479     .remove =        pc300_pci_remove_one,
0480 };
0481
0482 static int __init pc300_init_module(void)
0483 {
0484     if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
0485         pr_err("Invalid PCI clock frequency\n");
0486         return -EINVAL;
0487     }
0488     if (use_crystal_clock != 0 && use_crystal_clock != 1) {
0489         pr_err("Invalid 'use_crystal_clock' value\n");
0490         return -EINVAL;
0491     }
0492
0493     CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
0494
0495     return pci_register_driver(&pc300_pci_driver);
0496 }
0497
0498 static void __exit pc300_cleanup_module(void)
0499 {
0500     pci_unregister_driver(&pc300_pci_driver);
0501 }
0502
0503 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
0504 MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
0505 MODULE_LICENSE("GPL v2");
0506 MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
0507 module_param(pci_clock_freq, int, 0444);
0508 MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
0509 module_param(use_crystal_clock, int, 0444);
0510 MODULE_PARM_DESC(use_crystal_clock,
0511          "Use 24.576 MHz clock instead of PCI clock");
0512 module_init(pc300_init_module);
0513 module_exit(pc300_cleanup_module);