net/wan/n2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * SDL Inc. RISCom/N2 synchronous serial card driver for Linux
0004  *
0005  * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
0006  *
0007  * For information see <https://www.kernel.org/pub/linux/utils/net/hdlc/>
0008  *
0009  * Note: integrated CSU/DSU/DDS are not supported by this driver
0010  *
0011  * Sources of information:
0012  *    Hitachi HD64570 SCA User's Manual
0013  *    SDL Inc. PPP/HDLC/CISCO driver
0014  */
0015
0016 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0017
0018 #include <linux/module.h>
0019 #include <linux/kernel.h>
0020 #include <linux/capability.h>
0021 #include <linux/slab.h>
0022 #include <linux/types.h>
0023 #include <linux/fcntl.h>
0024 #include <linux/in.h>
0025 #include <linux/string.h>
0026 #include <linux/errno.h>
0027 #include <linux/init.h>
0028 #include <linux/ioport.h>
0029 #include <linux/moduleparam.h>
0030 #include <linux/netdevice.h>
0031 #include <linux/hdlc.h>
0032 #include <asm/io.h>
0033 #include "hd64570.h"
0034
0035 static const char *version = "SDL RISCom/N2 driver version: 1.15";
0036 static const char *devname = "RISCom/N2";
0037
0038 #undef DEBUG_PKT
0039 #define DEBUG_RINGS
0040
0041 #define USE_WINDOWSIZE 16384
0042 #define USE_BUS16BITS 1
0043 #define CLOCK_BASE 9830400  /* 9.8304 MHz */
0044 #define MAX_PAGES      16   /* 16 RAM pages at max */
0045 #define MAX_RAM_SIZE 0x80000    /* 512 KB */
0046 #if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE
0047 #undef MAX_RAM_SIZE
0048 #define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE)
0049 #endif
0050 #define N2_IOPORTS 0x10
0051 #define NEED_DETECT_RAM
0052 #define NEED_SCA_MSCI_INTR
0053 #define MAX_TX_BUFFERS 10
0054
0055 static char *hw;    /* pointer to hw=xxx command line string */
0056
0057 /* RISCom/N2 Board Registers */
0058
0059 /* PC Control Register */
0060 #define N2_PCR 0
0061 #define PCR_RUNSCA 1     /* Run 64570 */
0062 #define PCR_VPM    2     /* Enable VPM - needed if using RAM above 1 MB */
0063 #define PCR_ENWIN  4     /* Open window */
0064 #define PCR_BUS16  8     /* 16-bit bus */
0065
0066 /* Memory Base Address Register */
0067 #define N2_BAR 2
0068
0069 /* Page Scan Register  */
0070 #define N2_PSR 4
0071 #define WIN16K       0x00
0072 #define WIN32K       0x20
0073 #define WIN64K       0x40
0074 #define PSR_WINBITS  0x60
0075 #define PSR_DMAEN    0x80
0076 #define PSR_PAGEBITS 0x0F
0077
0078 /* Modem Control Reg */
0079 #define N2_MCR 6
0080 #define CLOCK_OUT_PORT1 0x80
0081 #define CLOCK_OUT_PORT0 0x40
0082 #define TX422_PORT1     0x20
0083 #define TX422_PORT0     0x10
0084 #define DSR_PORT1       0x08
0085 #define DSR_PORT0       0x04
0086 #define DTR_PORT1       0x02
0087 #define DTR_PORT0       0x01
0088
0089 typedef struct port_s {
0090     struct net_device *dev;
0091     struct card_s *card;
0092     spinlock_t lock;    /* TX lock */
0093     sync_serial_settings settings;
0094     int valid;      /* port enabled */
0095     int rxpart;     /* partial frame received, next frame invalid*/
0096     unsigned short encoding;
0097     unsigned short parity;
0098     u16 rxin;       /* rx ring buffer 'in' pointer */
0099     u16 txin;       /* tx ring buffer 'in' and 'last' pointers */
0100     u16 txlast;
0101     u8 rxs, txs, tmc;   /* SCA registers */
0102     u8 phy_node;        /* physical port # - 0 or 1 */
0103     u8 log_node;        /* logical port # */
0104 } port_t;
0105
0106 typedef struct card_s {
0107     u8 __iomem *winbase;        /* ISA window base address */
0108     u32 phy_winbase;    /* ISA physical base address */
0109     u32 ram_size;       /* number of bytes */
0110     u16 io;         /* IO Base address */
0111     u16 buff_offset;    /* offset of first buffer of first channel */
0112     u16 rx_ring_buffers;    /* number of buffers in a ring */
0113     u16 tx_ring_buffers;
0114     u8 irq;         /* IRQ (3-15) */
0115
0116     port_t ports[2];
0117     struct card_s *next_card;
0118 } card_t;
0119
0120 static card_t *first_card;
0121 static card_t **new_card = &first_card;
0122
0123 #define sca_reg(reg, card) (0x8000 | (card)->io | \
0124                 ((reg) & 0x0F) | (((reg) & 0xF0) << 6))
0125 #define sca_in(reg, card)       inb(sca_reg(reg, card))
0126 #define sca_out(value, reg, card)   outb(value, sca_reg(reg, card))
0127 #define sca_inw(reg, card)      inw(sca_reg(reg, card))
0128 #define sca_outw(value, reg, card)  outw(value, sca_reg(reg, card))
0129
0130 #define port_to_card(port)      ((port)->card)
0131 #define log_node(port)          ((port)->log_node)
0132 #define phy_node(port)          ((port)->phy_node)
0133 #define winsize(card)           (USE_WINDOWSIZE)
0134 #define winbase(card)               ((card)->winbase)
0135 #define get_port(card, port)        ((card)->ports[port].valid ? \
0136                      &(card)->ports[port] : NULL)
0137
0138 static __inline__ u8 sca_get_page(card_t *card)
0139 {
0140     return inb(card->io + N2_PSR) & PSR_PAGEBITS;
0141 }
0142
0143 static __inline__ void openwin(card_t *card, u8 page)
0144 {
0145     u8 psr = inb(card->io + N2_PSR);
0146
0147     outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR);
0148 }
0149
0150 #include "hd64570.c"
0151
0152 static void n2_set_iface(port_t *port)
0153 {
0154     card_t *card = port->card;
0155     int io = card->io;
0156     u8 mcr = inb(io + N2_MCR);
0157     u8 msci = get_msci(port);
0158     u8 rxs = port->rxs & CLK_BRG_MASK;
0159     u8 txs = port->txs & CLK_BRG_MASK;
0160
0161     switch (port->settings.clock_type) {
0162     case CLOCK_INT:
0163         mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
0164         rxs |= CLK_BRG_RX; /* BRG output */
0165         txs |= CLK_RXCLK_TX; /* RX clock */
0166         break;
0167
0168     case CLOCK_TXINT:
0169         mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
0170         rxs |= CLK_LINE_RX; /* RXC input */
0171         txs |= CLK_BRG_TX; /* BRG output */
0172         break;
0173
0174     case CLOCK_TXFROMRX:
0175         mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
0176         rxs |= CLK_LINE_RX; /* RXC input */
0177         txs |= CLK_RXCLK_TX; /* RX clock */
0178         break;
0179
0180     default:        /* Clock EXTernal */
0181         mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0;
0182         rxs |= CLK_LINE_RX; /* RXC input */
0183         txs |= CLK_LINE_TX; /* TXC input */
0184     }
0185
0186     outb(mcr, io + N2_MCR);
0187     port->rxs = rxs;
0188     port->txs = txs;
0189     sca_out(rxs, msci + RXS, card);
0190     sca_out(txs, msci + TXS, card);
0191     sca_set_port(port);
0192 }
0193
0194 static int n2_open(struct net_device *dev)
0195 {
0196     port_t *port = dev_to_port(dev);
0197     int io = port->card->io;
0198     u8 mcr = inb(io + N2_MCR) |
0199         (port->phy_node ? TX422_PORT1 : TX422_PORT0);
0200     int result;
0201
0202     result = hdlc_open(dev);
0203     if (result)
0204         return result;
0205
0206     mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */
0207     outb(mcr, io + N2_MCR);
0208
0209     outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */
0210     outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */
0211     sca_open(dev);
0212     n2_set_iface(port);
0213     return 0;
0214 }
0215
0216 static int n2_close(struct net_device *dev)
0217 {
0218     port_t *port = dev_to_port(dev);
0219     int io = port->card->io;
0220     u8 mcr = inb(io + N2_MCR) |
0221         (port->phy_node ? TX422_PORT1 : TX422_PORT0);
0222
0223     sca_close(dev);
0224     mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */
0225     outb(mcr, io + N2_MCR);
0226     hdlc_close(dev);
0227     return 0;
0228 }
0229
0230 static int n2_siocdevprivate(struct net_device *dev, struct ifreq *ifr,
0231                  void __user *data, int cmd)
0232 {
0233 #ifdef DEBUG_RINGS
0234     if (cmd == SIOCDEVPRIVATE) {
0235         sca_dump_rings(dev);
0236         return 0;
0237     }
0238 #endif
0239     return -EOPNOTSUPP;
0240 }
0241
0242 static int n2_ioctl(struct net_device *dev, struct if_settings *ifs)
0243 {
0244     const size_t size = sizeof(sync_serial_settings);
0245     sync_serial_settings new_line;
0246     sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
0247     port_t *port = dev_to_port(dev);
0248
0249     switch (ifs->type) {
0250     case IF_GET_IFACE:
0251         ifs->type = IF_IFACE_SYNC_SERIAL;
0252         if (ifs->size < size) {
0253             ifs->size = size; /* data size wanted */
0254             return -ENOBUFS;
0255         }
0256         if (copy_to_user(line, &port->settings, size))
0257             return -EFAULT;
0258         return 0;
0259
0260     case IF_IFACE_SYNC_SERIAL:
0261         if (!capable(CAP_NET_ADMIN))
0262             return -EPERM;
0263
0264         if (copy_from_user(&new_line, line, size))
0265             return -EFAULT;
0266
0267         if (new_line.clock_type != CLOCK_EXT &&
0268             new_line.clock_type != CLOCK_TXFROMRX &&
0269             new_line.clock_type != CLOCK_INT &&
0270             new_line.clock_type != CLOCK_TXINT)
0271             return -EINVAL; /* No such clock setting */
0272
0273         if (new_line.loopback != 0 && new_line.loopback != 1)
0274             return -EINVAL;
0275
0276         memcpy(&port->settings, &new_line, size); /* Update settings */
0277         n2_set_iface(port);
0278         return 0;
0279
0280     default:
0281         return hdlc_ioctl(dev, ifs);
0282     }
0283 }
0284
0285 static void n2_destroy_card(card_t *card)
0286 {
0287     int cnt;
0288
0289     for (cnt = 0; cnt < 2; cnt++)
0290         if (card->ports[cnt].card) {
0291             struct net_device *dev = port_to_dev(&card->ports[cnt]);
0292
0293             unregister_hdlc_device(dev);
0294         }
0295
0296     if (card->irq)
0297         free_irq(card->irq, card);
0298
0299     if (card->winbase) {
0300         iounmap(card->winbase);
0301         release_mem_region(card->phy_winbase, USE_WINDOWSIZE);
0302     }
0303
0304     if (card->io)
0305         release_region(card->io, N2_IOPORTS);
0306     if (card->ports[0].dev)
0307         free_netdev(card->ports[0].dev);
0308     if (card->ports[1].dev)
0309         free_netdev(card->ports[1].dev);
0310     kfree(card);
0311 }
0312
0313 static const struct net_device_ops n2_ops = {
0314     .ndo_open       = n2_open,
0315     .ndo_stop       = n2_close,
0316     .ndo_start_xmit = hdlc_start_xmit,
0317     .ndo_siocwandev = n2_ioctl,
0318     .ndo_siocdevprivate = n2_siocdevprivate,
0319 };
0320
0321 static int __init n2_run(unsigned long io, unsigned long irq,
0322              unsigned long winbase, long valid0, long valid1)
0323 {
0324     card_t *card;
0325     u8 cnt, pcr;
0326     int i;
0327
0328     if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) {
0329         pr_err("invalid I/O port value\n");
0330         return -ENODEV;
0331     }
0332
0333     if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ {
0334         pr_err("invalid IRQ value\n");
0335         return -ENODEV;
0336     }
0337
0338     if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) {
0339         pr_err("invalid RAM value\n");
0340         return -ENODEV;
0341     }
0342
0343     card = kzalloc(sizeof(card_t), GFP_KERNEL);
0344     if (!card)
0345         return -ENOBUFS;
0346
0347     card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
0348     card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
0349     if (!card->ports[0].dev || !card->ports[1].dev) {
0350         pr_err("unable to allocate memory\n");
0351         n2_destroy_card(card);
0352         return -ENOMEM;
0353     }
0354
0355     if (!request_region(io, N2_IOPORTS, devname)) {
0356         pr_err("I/O port region in use\n");
0357         n2_destroy_card(card);
0358         return -EBUSY;
0359     }
0360     card->io = io;
0361
0362     if (request_irq(irq, sca_intr, 0, devname, card)) {
0363         pr_err("could not allocate IRQ\n");
0364         n2_destroy_card(card);
0365         return -EBUSY;
0366     }
0367     card->irq = irq;
0368
0369     if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) {
0370         pr_err("could not request RAM window\n");
0371         n2_destroy_card(card);
0372         return -EBUSY;
0373     }
0374     card->phy_winbase = winbase;
0375     card->winbase = ioremap(winbase, USE_WINDOWSIZE);
0376     if (!card->winbase) {
0377         pr_err("ioremap() failed\n");
0378         n2_destroy_card(card);
0379         return -EFAULT;
0380     }
0381
0382     outb(0, io + N2_PCR);
0383     outb(winbase >> 12, io + N2_BAR);
0384
0385     switch (USE_WINDOWSIZE) {
0386     case 16384:
0387         outb(WIN16K, io + N2_PSR);
0388         break;
0389
0390     case 32768:
0391         outb(WIN32K, io + N2_PSR);
0392         break;
0393
0394     case 65536:
0395         outb(WIN64K, io + N2_PSR);
0396         break;
0397
0398     default:
0399         pr_err("invalid window size\n");
0400         n2_destroy_card(card);
0401         return -ENODEV;
0402     }
0403
0404     pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0);
0405     outb(pcr, io + N2_PCR);
0406
0407     card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE);
0408
0409     /* number of TX + RX buffers for one port */
0410     i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) +
0411                            HDLC_MAX_MRU));
0412
0413     card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
0414     card->rx_ring_buffers = i - card->tx_ring_buffers;
0415
0416     card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) *
0417         (card->tx_ring_buffers + card->rx_ring_buffers);
0418
0419     pr_info("RISCom/N2 %u KB RAM, IRQ%u, using %u TX + %u RX packets rings\n",
0420         card->ram_size / 1024, card->irq,
0421         card->tx_ring_buffers, card->rx_ring_buffers);
0422
0423     if (card->tx_ring_buffers < 1) {
0424         pr_err("RAM test failed\n");
0425         n2_destroy_card(card);
0426         return -EIO;
0427     }
0428
0429     pcr |= PCR_RUNSCA;      /* run SCA */
0430     outb(pcr, io + N2_PCR);
0431     outb(0, io + N2_MCR);
0432
0433     sca_init(card, 0);
0434     for (cnt = 0; cnt < 2; cnt++) {
0435         port_t *port = &card->ports[cnt];
0436         struct net_device *dev = port_to_dev(port);
0437         hdlc_device *hdlc = dev_to_hdlc(dev);
0438
0439         if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1))
0440             continue;
0441
0442         port->phy_node = cnt;
0443         port->valid = 1;
0444
0445         if ((cnt == 1) && valid0)
0446             port->log_node = 1;
0447
0448         spin_lock_init(&port->lock);
0449         dev->irq = irq;
0450         dev->mem_start = winbase;
0451         dev->mem_end = winbase + USE_WINDOWSIZE - 1;
0452         dev->tx_queue_len = 50;
0453         dev->netdev_ops = &n2_ops;
0454         hdlc->attach = sca_attach;
0455         hdlc->xmit = sca_xmit;
0456         port->settings.clock_type = CLOCK_EXT;
0457         port->card = card;
0458
0459         if (register_hdlc_device(dev)) {
0460             pr_warn("unable to register hdlc device\n");
0461             port->card = NULL;
0462             n2_destroy_card(card);
0463             return -ENOBUFS;
0464         }
0465         sca_init_port(port); /* Set up SCA memory */
0466
0467         netdev_info(dev, "RISCom/N2 node %d\n", port->phy_node);
0468     }
0469
0470     *new_card = card;
0471     new_card = &card->next_card;
0472
0473     return 0;
0474 }
0475
0476 static int __init n2_init(void)
0477 {
0478     if (!hw) {
0479 #ifdef MODULE
0480         pr_info("no card initialized\n");
0481 #endif
0482         return -EINVAL; /* no parameters specified, abort */
0483     }
0484
0485     pr_info("%s\n", version);
0486
0487     do {
0488         unsigned long io, irq, ram;
0489         long valid[2] = { 0, 0 }; /* Default = both ports disabled */
0490
0491         io = simple_strtoul(hw, &hw, 0);
0492
0493         if (*hw++ != ',')
0494             break;
0495         irq = simple_strtoul(hw, &hw, 0);
0496
0497         if (*hw++ != ',')
0498             break;
0499         ram = simple_strtoul(hw, &hw, 0);
0500
0501         if (*hw++ != ',')
0502             break;
0503         while (1) {
0504             if (*hw == '0' && !valid[0])
0505                 valid[0] = 1; /* Port 0 enabled */
0506             else if (*hw == '1' && !valid[1])
0507                 valid[1] = 1; /* Port 1 enabled */
0508             else
0509                 break;
0510             hw++;
0511         }
0512
0513         if (!valid[0] && !valid[1])
0514             break;  /* at least one port must be used */
0515
0516         if (*hw == ':' || *hw == '\x0')
0517             n2_run(io, irq, ram, valid[0], valid[1]);
0518
0519         if (*hw == '\x0')
0520             return first_card ? 0 : -EINVAL;
0521     } while (*hw++ == ':');
0522
0523     pr_err("invalid hardware parameters\n");
0524     return first_card ? 0 : -EINVAL;
0525 }
0526
0527 static void __exit n2_cleanup(void)
0528 {
0529     card_t *card = first_card;
0530
0531     while (card) {
0532         card_t *ptr = card;
0533
0534         card = card->next_card;
0535         n2_destroy_card(ptr);
0536     }
0537 }
0538
0539 module_init(n2_init);
0540 module_exit(n2_cleanup);
0541
0542 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
0543 MODULE_DESCRIPTION("RISCom/N2 serial port driver");
0544 MODULE_LICENSE("GPL v2");
0545 module_param(hw, charp, 0444);
0546 MODULE_PARM_DESC(hw, "io,irq,ram,ports:io,irq,...");