Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel IXP4xx HSS (synchronous serial port) driver for Linux
0004  *
0005  * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
0006  */
0007 
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009 
0010 #include <linux/module.h>
0011 #include <linux/bitops.h>
0012 #include <linux/cdev.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/dmapool.h>
0015 #include <linux/fs.h>
0016 #include <linux/hdlc.h>
0017 #include <linux/io.h>
0018 #include <linux/kernel.h>
0019 #include <linux/mfd/syscon.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/poll.h>
0022 #include <linux/regmap.h>
0023 #include <linux/slab.h>
0024 #include <linux/gpio/consumer.h>
0025 #include <linux/of.h>
0026 #include <linux/soc/ixp4xx/npe.h>
0027 #include <linux/soc/ixp4xx/qmgr.h>
0028 #include <linux/soc/ixp4xx/cpu.h>
0029 
0030 /* This is what all IXP4xx platforms we know uses, if more frequencies
0031  * are needed, we need to migrate to the clock framework.
0032  */
0033 #define IXP4XX_TIMER_FREQ   66666000
0034 
0035 #define DEBUG_DESC      0
0036 #define DEBUG_RX        0
0037 #define DEBUG_TX        0
0038 #define DEBUG_PKT_BYTES     0
0039 #define DEBUG_CLOSE     0
0040 
0041 #define DRV_NAME        "ixp4xx_hss"
0042 
0043 #define PKT_EXTRA_FLAGS     0 /* orig 1 */
0044 #define PKT_NUM_PIPES       1 /* 1, 2 or 4 */
0045 #define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
0046 
0047 #define RX_DESCS        16 /* also length of all RX queues */
0048 #define TX_DESCS        16 /* also length of all TX queues */
0049 
0050 #define POOL_ALLOC_SIZE     (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
0051 #define RX_SIZE         (HDLC_MAX_MRU + 4) /* NPE needs more space */
0052 #define MAX_CLOSE_WAIT      1000 /* microseconds */
0053 #define HSS_COUNT       2
0054 #define FRAME_SIZE      256 /* doesn't matter at this point */
0055 #define FRAME_OFFSET        0
0056 #define MAX_CHANNELS        (FRAME_SIZE / 8)
0057 
0058 #define NAPI_WEIGHT     16
0059 
0060 /* Queue IDs */
0061 #define HSS0_PKT_RX_QUEUE   13  /* orig size = 32 dwords */
0062 #define HSS0_PKT_TX0_QUEUE  14  /* orig size = 16 dwords */
0063 #define HSS0_PKT_TX1_QUEUE  15
0064 #define HSS0_PKT_TX2_QUEUE  16
0065 #define HSS0_PKT_TX3_QUEUE  17
0066 #define HSS0_PKT_RXFREE0_QUEUE  18  /* orig size = 16 dwords */
0067 #define HSS0_PKT_RXFREE1_QUEUE  19
0068 #define HSS0_PKT_RXFREE2_QUEUE  20
0069 #define HSS0_PKT_RXFREE3_QUEUE  21
0070 #define HSS0_PKT_TXDONE_QUEUE   22  /* orig size = 64 dwords */
0071 
0072 #define HSS1_PKT_RX_QUEUE   0
0073 #define HSS1_PKT_TX0_QUEUE  5
0074 #define HSS1_PKT_TX1_QUEUE  6
0075 #define HSS1_PKT_TX2_QUEUE  7
0076 #define HSS1_PKT_TX3_QUEUE  8
0077 #define HSS1_PKT_RXFREE0_QUEUE  1
0078 #define HSS1_PKT_RXFREE1_QUEUE  2
0079 #define HSS1_PKT_RXFREE2_QUEUE  3
0080 #define HSS1_PKT_RXFREE3_QUEUE  4
0081 #define HSS1_PKT_TXDONE_QUEUE   9
0082 
0083 #define NPE_PKT_MODE_HDLC       0
0084 #define NPE_PKT_MODE_RAW        1
0085 #define NPE_PKT_MODE_56KMODE        2
0086 #define NPE_PKT_MODE_56KENDIAN_MSB  4
0087 
0088 /* PKT_PIPE_HDLC_CFG_WRITE flags */
0089 #define PKT_HDLC_IDLE_ONES      0x1 /* default = flags */
0090 #define PKT_HDLC_CRC_32         0x2 /* default = CRC-16 */
0091 #define PKT_HDLC_MSB_ENDIAN     0x4 /* default = LE */
0092 
0093 /* hss_config, PCRs */
0094 /* Frame sync sampling, default = active low */
0095 #define PCR_FRM_SYNC_ACTIVE_HIGH    0x40000000
0096 #define PCR_FRM_SYNC_FALLINGEDGE    0x80000000
0097 #define PCR_FRM_SYNC_RISINGEDGE     0xC0000000
0098 
0099 /* Frame sync pin: input (default) or output generated off a given clk edge */
0100 #define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
0101 #define PCR_FRM_SYNC_OUTPUT_RISING  0x30000000
0102 
0103 /* Frame and data clock sampling on edge, default = falling */
0104 #define PCR_FCLK_EDGE_RISING        0x08000000
0105 #define PCR_DCLK_EDGE_RISING        0x04000000
0106 
0107 /* Clock direction, default = input */
0108 #define PCR_SYNC_CLK_DIR_OUTPUT     0x02000000
0109 
0110 /* Generate/Receive frame pulses, default = enabled */
0111 #define PCR_FRM_PULSE_DISABLED      0x01000000
0112 
0113  /* Data rate is full (default) or half the configured clk speed */
0114 #define PCR_HALF_CLK_RATE       0x00200000
0115 
0116 /* Invert data between NPE and HSS FIFOs? (default = no) */
0117 #define PCR_DATA_POLARITY_INVERT    0x00100000
0118 
0119 /* TX/RX endianness, default = LSB */
0120 #define PCR_MSB_ENDIAN          0x00080000
0121 
0122 /* Normal (default) / open drain mode (TX only) */
0123 #define PCR_TX_PINS_OPEN_DRAIN      0x00040000
0124 
0125 /* No framing bit transmitted and expected on RX? (default = framing bit) */
0126 #define PCR_SOF_NO_FBIT         0x00020000
0127 
0128 /* Drive data pins? */
0129 #define PCR_TX_DATA_ENABLE      0x00010000
0130 
0131 /* Voice 56k type: drive the data pins low (default), high, high Z */
0132 #define PCR_TX_V56K_HIGH        0x00002000
0133 #define PCR_TX_V56K_HIGH_IMP        0x00004000
0134 
0135 /* Unassigned type: drive the data pins low (default), high, high Z */
0136 #define PCR_TX_UNASS_HIGH       0x00000800
0137 #define PCR_TX_UNASS_HIGH_IMP       0x00001000
0138 
0139 /* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
0140 #define PCR_TX_FB_HIGH_IMP      0x00000400
0141 
0142 /* 56k data endiannes - which bit unused: high (default) or low */
0143 #define PCR_TX_56KE_BIT_0_UNUSED    0x00000200
0144 
0145 /* 56k data transmission type: 32/8 bit data (default) or 56K data */
0146 #define PCR_TX_56KS_56K_DATA        0x00000100
0147 
0148 /* hss_config, cCR */
0149 /* Number of packetized clients, default = 1 */
0150 #define CCR_NPE_HFIFO_2_HDLC        0x04000000
0151 #define CCR_NPE_HFIFO_3_OR_4HDLC    0x08000000
0152 
0153 /* default = no loopback */
0154 #define CCR_LOOPBACK            0x02000000
0155 
0156 /* HSS number, default = 0 (first) */
0157 #define CCR_SECOND_HSS          0x01000000
0158 
0159 /* hss_config, clkCR: main:10, num:10, denom:12 */
0160 #define CLK42X_SPEED_EXP    ((0x3FF << 22) | (2 << 12) |   15) /*65 KHz*/
0161 
0162 #define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) |   15)
0163 #define CLK42X_SPEED_1536KHZ    ((43 << 22) | (18 << 12) |   47)
0164 #define CLK42X_SPEED_1544KHZ    ((43 << 22) | (33 << 12) |  192)
0165 #define CLK42X_SPEED_2048KHZ    ((32 << 22) | (34 << 12) |   63)
0166 #define CLK42X_SPEED_4096KHZ    ((16 << 22) | (34 << 12) |  127)
0167 #define CLK42X_SPEED_8192KHZ    ((8 << 22) | (34 << 12) |  255)
0168 
0169 #define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) |  127)
0170 #define CLK46X_SPEED_1536KHZ    ((43 << 22) | (152 << 12) |  383)
0171 #define CLK46X_SPEED_1544KHZ    ((43 << 22) | (66 << 12) |  385)
0172 #define CLK46X_SPEED_2048KHZ    ((32 << 22) | (280 << 12) |  511)
0173 #define CLK46X_SPEED_4096KHZ    ((16 << 22) | (280 << 12) | 1023)
0174 #define CLK46X_SPEED_8192KHZ    ((8 << 22) | (280 << 12) | 2047)
0175 
0176 /* HSS_CONFIG_CLOCK_CR register consists of 3 parts:
0177  *     A (10 bits), B (10 bits) and C (12 bits).
0178  * IXP42x HSS clock generator operation (verified with an oscilloscope):
0179  * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
0180  * The clock sequence consists of (C - B) states of 0s and 1s, each state is
0181  * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
0182  * (A + 1) bits wide.
0183  *
0184  * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
0185  * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
0186  * minimum freq = 66.666 MHz / (A + 1)
0187  * maximum freq = 66.666 MHz / A
0188  *
0189  * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
0190  * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
0191  * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
0192  * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
0193  * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
0194  * The sequence consists of 4 complete clock periods, thus the average
0195  * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
0196  * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
0197  */
0198 
0199 /* hss_config, LUT entries */
0200 #define TDMMAP_UNASSIGNED   0
0201 #define TDMMAP_HDLC     1   /* HDLC - packetized */
0202 #define TDMMAP_VOICE56K     2   /* Voice56K - 7-bit channelized */
0203 #define TDMMAP_VOICE64K     3   /* Voice64K - 8-bit channelized */
0204 
0205 /* offsets into HSS config */
0206 #define HSS_CONFIG_TX_PCR   0x00 /* port configuration registers */
0207 #define HSS_CONFIG_RX_PCR   0x04
0208 #define HSS_CONFIG_CORE_CR  0x08 /* loopback control, HSS# */
0209 #define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
0210 #define HSS_CONFIG_TX_FCR   0x10 /* frame configuration registers */
0211 #define HSS_CONFIG_RX_FCR   0x14
0212 #define HSS_CONFIG_TX_LUT   0x18 /* channel look-up tables */
0213 #define HSS_CONFIG_RX_LUT   0x38
0214 
0215 /* NPE command codes */
0216 /* writes the ConfigWord value to the location specified by offset */
0217 #define PORT_CONFIG_WRITE       0x40
0218 
0219 /* triggers the NPE to load the contents of the configuration table */
0220 #define PORT_CONFIG_LOAD        0x41
0221 
0222 /* triggers the NPE to return an HssErrorReadResponse message */
0223 #define PORT_ERROR_READ         0x42
0224 
0225 /* triggers the NPE to reset internal status and enable the HssPacketized
0226  * operation for the flow specified by pPipe
0227  */
0228 #define PKT_PIPE_FLOW_ENABLE        0x50
0229 #define PKT_PIPE_FLOW_DISABLE       0x51
0230 #define PKT_NUM_PIPES_WRITE     0x52
0231 #define PKT_PIPE_FIFO_SIZEW_WRITE   0x53
0232 #define PKT_PIPE_HDLC_CFG_WRITE     0x54
0233 #define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
0234 #define PKT_PIPE_RX_SIZE_WRITE      0x56
0235 #define PKT_PIPE_MODE_WRITE     0x57
0236 
0237 /* HDLC packet status values - desc->status */
0238 #define ERR_SHUTDOWN        1 /* stop or shutdown occurrence */
0239 #define ERR_HDLC_ALIGN      2 /* HDLC alignment error */
0240 #define ERR_HDLC_FCS        3 /* HDLC Frame Check Sum error */
0241 #define ERR_RXFREE_Q_EMPTY  4 /* RX-free queue became empty while receiving
0242                    * this packet (if buf_len < pkt_len)
0243                    */
0244 #define ERR_HDLC_TOO_LONG   5 /* HDLC frame size too long */
0245 #define ERR_HDLC_ABORT      6 /* abort sequence received */
0246 #define ERR_DISCONNECTING   7 /* disconnect is in progress */
0247 
0248 #ifdef __ARMEB__
0249 typedef struct sk_buff buffer_t;
0250 #define free_buffer dev_kfree_skb
0251 #define free_buffer_irq dev_consume_skb_irq
0252 #else
0253 typedef void buffer_t;
0254 #define free_buffer kfree
0255 #define free_buffer_irq kfree
0256 #endif
0257 
0258 struct port {
0259     struct device *dev;
0260     struct npe *npe;
0261     unsigned int txreadyq;
0262     unsigned int rxtrigq;
0263     unsigned int rxfreeq;
0264     unsigned int rxq;
0265     unsigned int txq;
0266     unsigned int txdoneq;
0267     struct gpio_desc *cts;
0268     struct gpio_desc *rts;
0269     struct gpio_desc *dcd;
0270     struct gpio_desc *dtr;
0271     struct gpio_desc *clk_internal;
0272     struct net_device *netdev;
0273     struct napi_struct napi;
0274     buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
0275     struct desc *desc_tab;  /* coherent */
0276     dma_addr_t desc_tab_phys;
0277     unsigned int id;
0278     unsigned int clock_type, clock_rate, loopback;
0279     unsigned int initialized, carrier;
0280     u8 hdlc_cfg;
0281     u32 clock_reg;
0282 };
0283 
0284 /* NPE message structure */
0285 struct msg {
0286 #ifdef __ARMEB__
0287     u8 cmd, unused, hss_port, index;
0288     union {
0289         struct { u8 data8a, data8b, data8c, data8d; };
0290         struct { u16 data16a, data16b; };
0291         struct { u32 data32; };
0292     };
0293 #else
0294     u8 index, hss_port, unused, cmd;
0295     union {
0296         struct { u8 data8d, data8c, data8b, data8a; };
0297         struct { u16 data16b, data16a; };
0298         struct { u32 data32; };
0299     };
0300 #endif
0301 };
0302 
0303 /* HDLC packet descriptor */
0304 struct desc {
0305     u32 next;       /* pointer to next buffer, unused */
0306 
0307 #ifdef __ARMEB__
0308     u16 buf_len;        /* buffer length */
0309     u16 pkt_len;        /* packet length */
0310     u32 data;       /* pointer to data buffer in RAM */
0311     u8 status;
0312     u8 error_count;
0313     u16 __reserved;
0314 #else
0315     u16 pkt_len;        /* packet length */
0316     u16 buf_len;        /* buffer length */
0317     u32 data;       /* pointer to data buffer in RAM */
0318     u16 __reserved;
0319     u8 error_count;
0320     u8 status;
0321 #endif
0322     u32 __reserved1[4];
0323 };
0324 
0325 #define rx_desc_phys(port, n)   ((port)->desc_tab_phys +        \
0326                  (n) * sizeof(struct desc))
0327 #define rx_desc_ptr(port, n)    (&(port)->desc_tab[n])
0328 
0329 #define tx_desc_phys(port, n)   ((port)->desc_tab_phys +        \
0330                  ((n) + RX_DESCS) * sizeof(struct desc))
0331 #define tx_desc_ptr(port, n)    (&(port)->desc_tab[(n) + RX_DESCS])
0332 
0333 /*****************************************************************************
0334  * global variables
0335  ****************************************************************************/
0336 
0337 static int ports_open;
0338 static struct dma_pool *dma_pool;
0339 static DEFINE_SPINLOCK(npe_lock);
0340 
0341 /*****************************************************************************
0342  * utility functions
0343  ****************************************************************************/
0344 
0345 static inline struct port *dev_to_port(struct net_device *dev)
0346 {
0347     return dev_to_hdlc(dev)->priv;
0348 }
0349 
0350 #ifndef __ARMEB__
0351 static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
0352 {
0353     int i;
0354 
0355     for (i = 0; i < cnt; i++)
0356         dest[i] = swab32(src[i]);
0357 }
0358 #endif
0359 
0360 /*****************************************************************************
0361  * HSS access
0362  ****************************************************************************/
0363 
0364 static void hss_npe_send(struct port *port, struct msg *msg, const char *what)
0365 {
0366     u32 *val = (u32 *)msg;
0367 
0368     if (npe_send_message(port->npe, msg, what)) {
0369         pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
0370             port->id, val[0], val[1], npe_name(port->npe));
0371         BUG();
0372     }
0373 }
0374 
0375 static void hss_config_set_lut(struct port *port)
0376 {
0377     struct msg msg;
0378     int ch;
0379 
0380     memset(&msg, 0, sizeof(msg));
0381     msg.cmd = PORT_CONFIG_WRITE;
0382     msg.hss_port = port->id;
0383 
0384     for (ch = 0; ch < MAX_CHANNELS; ch++) {
0385         msg.data32 >>= 2;
0386         msg.data32 |= TDMMAP_HDLC << 30;
0387 
0388         if (ch % 16 == 15) {
0389             msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
0390             hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
0391 
0392             msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
0393             hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
0394         }
0395     }
0396 }
0397 
0398 static void hss_config(struct port *port)
0399 {
0400     struct msg msg;
0401 
0402     memset(&msg, 0, sizeof(msg));
0403     msg.cmd = PORT_CONFIG_WRITE;
0404     msg.hss_port = port->id;
0405     msg.index = HSS_CONFIG_TX_PCR;
0406     msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
0407         PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
0408     if (port->clock_type == CLOCK_INT)
0409         msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
0410     hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
0411 
0412     msg.index = HSS_CONFIG_RX_PCR;
0413     msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
0414     hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
0415 
0416     memset(&msg, 0, sizeof(msg));
0417     msg.cmd = PORT_CONFIG_WRITE;
0418     msg.hss_port = port->id;
0419     msg.index = HSS_CONFIG_CORE_CR;
0420     msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
0421         (port->id ? CCR_SECOND_HSS : 0);
0422     hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
0423 
0424     memset(&msg, 0, sizeof(msg));
0425     msg.cmd = PORT_CONFIG_WRITE;
0426     msg.hss_port = port->id;
0427     msg.index = HSS_CONFIG_CLOCK_CR;
0428     msg.data32 = port->clock_reg;
0429     hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
0430 
0431     memset(&msg, 0, sizeof(msg));
0432     msg.cmd = PORT_CONFIG_WRITE;
0433     msg.hss_port = port->id;
0434     msg.index = HSS_CONFIG_TX_FCR;
0435     msg.data16a = FRAME_OFFSET;
0436     msg.data16b = FRAME_SIZE - 1;
0437     hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
0438 
0439     memset(&msg, 0, sizeof(msg));
0440     msg.cmd = PORT_CONFIG_WRITE;
0441     msg.hss_port = port->id;
0442     msg.index = HSS_CONFIG_RX_FCR;
0443     msg.data16a = FRAME_OFFSET;
0444     msg.data16b = FRAME_SIZE - 1;
0445     hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
0446 
0447     hss_config_set_lut(port);
0448 
0449     memset(&msg, 0, sizeof(msg));
0450     msg.cmd = PORT_CONFIG_LOAD;
0451     msg.hss_port = port->id;
0452     hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
0453 
0454     if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
0455         /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
0456         msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
0457         pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
0458         BUG();
0459     }
0460 
0461     /* HDLC may stop working without this - check FIXME */
0462     npe_recv_message(port->npe, &msg, "FLUSH_IT");
0463 }
0464 
0465 static void hss_set_hdlc_cfg(struct port *port)
0466 {
0467     struct msg msg;
0468 
0469     memset(&msg, 0, sizeof(msg));
0470     msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
0471     msg.hss_port = port->id;
0472     msg.data8a = port->hdlc_cfg; /* rx_cfg */
0473     msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
0474     hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
0475 }
0476 
0477 static u32 hss_get_status(struct port *port)
0478 {
0479     struct msg msg;
0480 
0481     memset(&msg, 0, sizeof(msg));
0482     msg.cmd = PORT_ERROR_READ;
0483     msg.hss_port = port->id;
0484     hss_npe_send(port, &msg, "PORT_ERROR_READ");
0485     if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
0486         pr_crit("HSS-%i: unable to read HSS status\n", port->id);
0487         BUG();
0488     }
0489 
0490     return msg.data32;
0491 }
0492 
0493 static void hss_start_hdlc(struct port *port)
0494 {
0495     struct msg msg;
0496 
0497     memset(&msg, 0, sizeof(msg));
0498     msg.cmd = PKT_PIPE_FLOW_ENABLE;
0499     msg.hss_port = port->id;
0500     msg.data32 = 0;
0501     hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
0502 }
0503 
0504 static void hss_stop_hdlc(struct port *port)
0505 {
0506     struct msg msg;
0507 
0508     memset(&msg, 0, sizeof(msg));
0509     msg.cmd = PKT_PIPE_FLOW_DISABLE;
0510     msg.hss_port = port->id;
0511     hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
0512     hss_get_status(port); /* make sure it's halted */
0513 }
0514 
0515 static int hss_load_firmware(struct port *port)
0516 {
0517     struct msg msg;
0518     int err;
0519 
0520     if (port->initialized)
0521         return 0;
0522 
0523     if (!npe_running(port->npe)) {
0524         err = npe_load_firmware(port->npe, npe_name(port->npe),
0525                     port->dev);
0526         if (err)
0527             return err;
0528     }
0529 
0530     /* HDLC mode configuration */
0531     memset(&msg, 0, sizeof(msg));
0532     msg.cmd = PKT_NUM_PIPES_WRITE;
0533     msg.hss_port = port->id;
0534     msg.data8a = PKT_NUM_PIPES;
0535     hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
0536 
0537     msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
0538     msg.data8a = PKT_PIPE_FIFO_SIZEW;
0539     hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
0540 
0541     msg.cmd = PKT_PIPE_MODE_WRITE;
0542     msg.data8a = NPE_PKT_MODE_HDLC;
0543     /* msg.data8b = inv_mask */
0544     /* msg.data8c = or_mask */
0545     hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
0546 
0547     msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
0548     msg.data16a = HDLC_MAX_MRU; /* including CRC */
0549     hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
0550 
0551     msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
0552     msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
0553     hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
0554 
0555     port->initialized = 1;
0556     return 0;
0557 }
0558 
0559 /*****************************************************************************
0560  * packetized (HDLC) operation
0561  ****************************************************************************/
0562 
0563 static inline void debug_pkt(struct net_device *dev, const char *func,
0564                  u8 *data, int len)
0565 {
0566 #if DEBUG_PKT_BYTES
0567     int i;
0568 
0569     printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
0570     for (i = 0; i < len; i++) {
0571         if (i >= DEBUG_PKT_BYTES)
0572             break;
0573         printk("%s%02X", !(i % 4) ? " " : "", data[i]);
0574     }
0575     printk("\n");
0576 #endif
0577 }
0578 
0579 static inline void debug_desc(u32 phys, struct desc *desc)
0580 {
0581 #if DEBUG_DESC
0582     printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
0583            phys, desc->next, desc->buf_len, desc->pkt_len,
0584            desc->data, desc->status, desc->error_count);
0585 #endif
0586 }
0587 
0588 static inline int queue_get_desc(unsigned int queue, struct port *port,
0589                  int is_tx)
0590 {
0591     u32 phys, tab_phys, n_desc;
0592     struct desc *tab;
0593 
0594     phys = qmgr_get_entry(queue);
0595     if (!phys)
0596         return -1;
0597 
0598     BUG_ON(phys & 0x1F);
0599     tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
0600     tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
0601     n_desc = (phys - tab_phys) / sizeof(struct desc);
0602     BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
0603     debug_desc(phys, &tab[n_desc]);
0604     BUG_ON(tab[n_desc].next);
0605     return n_desc;
0606 }
0607 
0608 static inline void queue_put_desc(unsigned int queue, u32 phys,
0609                   struct desc *desc)
0610 {
0611     debug_desc(phys, desc);
0612     BUG_ON(phys & 0x1F);
0613     qmgr_put_entry(queue, phys);
0614     /* Don't check for queue overflow here, we've allocated sufficient
0615      * length and queues >= 32 don't support this check anyway.
0616      */
0617 }
0618 
0619 static inline void dma_unmap_tx(struct port *port, struct desc *desc)
0620 {
0621 #ifdef __ARMEB__
0622     dma_unmap_single(&port->netdev->dev, desc->data,
0623              desc->buf_len, DMA_TO_DEVICE);
0624 #else
0625     dma_unmap_single(&port->netdev->dev, desc->data & ~3,
0626              ALIGN((desc->data & 3) + desc->buf_len, 4),
0627              DMA_TO_DEVICE);
0628 #endif
0629 }
0630 
0631 static void hss_hdlc_set_carrier(void *pdev, int carrier)
0632 {
0633     struct net_device *netdev = pdev;
0634     struct port *port = dev_to_port(netdev);
0635     unsigned long flags;
0636 
0637     spin_lock_irqsave(&npe_lock, flags);
0638     port->carrier = carrier;
0639     if (!port->loopback) {
0640         if (carrier)
0641             netif_carrier_on(netdev);
0642         else
0643             netif_carrier_off(netdev);
0644     }
0645     spin_unlock_irqrestore(&npe_lock, flags);
0646 }
0647 
0648 static void hss_hdlc_rx_irq(void *pdev)
0649 {
0650     struct net_device *dev = pdev;
0651     struct port *port = dev_to_port(dev);
0652 
0653 #if DEBUG_RX
0654     printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
0655 #endif
0656     qmgr_disable_irq(port->rxq);
0657     napi_schedule(&port->napi);
0658 }
0659 
0660 static int hss_hdlc_poll(struct napi_struct *napi, int budget)
0661 {
0662     struct port *port = container_of(napi, struct port, napi);
0663     struct net_device *dev = port->netdev;
0664     unsigned int rxq = port->rxq;
0665     unsigned int rxfreeq = port->rxfreeq;
0666     int received = 0;
0667 
0668 #if DEBUG_RX
0669     printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
0670 #endif
0671 
0672     while (received < budget) {
0673         struct sk_buff *skb;
0674         struct desc *desc;
0675         int n;
0676 #ifdef __ARMEB__
0677         struct sk_buff *temp;
0678         u32 phys;
0679 #endif
0680 
0681         n = queue_get_desc(rxq, port, 0);
0682         if (n < 0) {
0683 #if DEBUG_RX
0684             printk(KERN_DEBUG "%s: hss_hdlc_poll"
0685                    " napi_complete\n", dev->name);
0686 #endif
0687             napi_complete(napi);
0688             qmgr_enable_irq(rxq);
0689             if (!qmgr_stat_empty(rxq) &&
0690                 napi_reschedule(napi)) {
0691 #if DEBUG_RX
0692                 printk(KERN_DEBUG "%s: hss_hdlc_poll"
0693                        " napi_reschedule succeeded\n",
0694                        dev->name);
0695 #endif
0696                 qmgr_disable_irq(rxq);
0697                 continue;
0698             }
0699 #if DEBUG_RX
0700             printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
0701                    dev->name);
0702 #endif
0703             return received; /* all work done */
0704         }
0705 
0706         desc = rx_desc_ptr(port, n);
0707 #if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
0708         if (desc->error_count)
0709             printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
0710                    " errors %u\n", dev->name, desc->status,
0711                    desc->error_count);
0712 #endif
0713         skb = NULL;
0714         switch (desc->status) {
0715         case 0:
0716 #ifdef __ARMEB__
0717             skb = netdev_alloc_skb(dev, RX_SIZE);
0718             if (skb) {
0719                 phys = dma_map_single(&dev->dev, skb->data,
0720                               RX_SIZE,
0721                               DMA_FROM_DEVICE);
0722                 if (dma_mapping_error(&dev->dev, phys)) {
0723                     dev_kfree_skb(skb);
0724                     skb = NULL;
0725                 }
0726             }
0727 #else
0728             skb = netdev_alloc_skb(dev, desc->pkt_len);
0729 #endif
0730             if (!skb)
0731                 dev->stats.rx_dropped++;
0732             break;
0733         case ERR_HDLC_ALIGN:
0734         case ERR_HDLC_ABORT:
0735             dev->stats.rx_frame_errors++;
0736             dev->stats.rx_errors++;
0737             break;
0738         case ERR_HDLC_FCS:
0739             dev->stats.rx_crc_errors++;
0740             dev->stats.rx_errors++;
0741             break;
0742         case ERR_HDLC_TOO_LONG:
0743             dev->stats.rx_length_errors++;
0744             dev->stats.rx_errors++;
0745             break;
0746         default:    /* FIXME - remove printk */
0747             netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
0748                    desc->status, desc->error_count);
0749             dev->stats.rx_errors++;
0750         }
0751 
0752         if (!skb) {
0753             /* put the desc back on RX-ready queue */
0754             desc->buf_len = RX_SIZE;
0755             desc->pkt_len = desc->status = 0;
0756             queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
0757             continue;
0758         }
0759 
0760         /* process received frame */
0761 #ifdef __ARMEB__
0762         temp = skb;
0763         skb = port->rx_buff_tab[n];
0764         dma_unmap_single(&dev->dev, desc->data,
0765                  RX_SIZE, DMA_FROM_DEVICE);
0766 #else
0767         dma_sync_single_for_cpu(&dev->dev, desc->data,
0768                     RX_SIZE, DMA_FROM_DEVICE);
0769         memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
0770                   ALIGN(desc->pkt_len, 4) / 4);
0771 #endif
0772         skb_put(skb, desc->pkt_len);
0773 
0774         debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
0775 
0776         skb->protocol = hdlc_type_trans(skb, dev);
0777         dev->stats.rx_packets++;
0778         dev->stats.rx_bytes += skb->len;
0779         netif_receive_skb(skb);
0780 
0781         /* put the new buffer on RX-free queue */
0782 #ifdef __ARMEB__
0783         port->rx_buff_tab[n] = temp;
0784         desc->data = phys;
0785 #endif
0786         desc->buf_len = RX_SIZE;
0787         desc->pkt_len = 0;
0788         queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
0789         received++;
0790     }
0791 #if DEBUG_RX
0792     printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
0793 #endif
0794     return received;    /* not all work done */
0795 }
0796 
0797 static void hss_hdlc_txdone_irq(void *pdev)
0798 {
0799     struct net_device *dev = pdev;
0800     struct port *port = dev_to_port(dev);
0801     int n_desc;
0802 
0803 #if DEBUG_TX
0804     printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
0805 #endif
0806     while ((n_desc = queue_get_desc(port->txdoneq,
0807                     port, 1)) >= 0) {
0808         struct desc *desc;
0809         int start;
0810 
0811         desc = tx_desc_ptr(port, n_desc);
0812 
0813         dev->stats.tx_packets++;
0814         dev->stats.tx_bytes += desc->pkt_len;
0815 
0816         dma_unmap_tx(port, desc);
0817 #if DEBUG_TX
0818         printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
0819                dev->name, port->tx_buff_tab[n_desc]);
0820 #endif
0821         free_buffer_irq(port->tx_buff_tab[n_desc]);
0822         port->tx_buff_tab[n_desc] = NULL;
0823 
0824         start = qmgr_stat_below_low_watermark(port->txreadyq);
0825         queue_put_desc(port->txreadyq,
0826                    tx_desc_phys(port, n_desc), desc);
0827         if (start) { /* TX-ready queue was empty */
0828 #if DEBUG_TX
0829             printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
0830                    " ready\n", dev->name);
0831 #endif
0832             netif_wake_queue(dev);
0833         }
0834     }
0835 }
0836 
0837 static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
0838 {
0839     struct port *port = dev_to_port(dev);
0840     unsigned int txreadyq = port->txreadyq;
0841     int len, offset, bytes, n;
0842     void *mem;
0843     u32 phys;
0844     struct desc *desc;
0845 
0846 #if DEBUG_TX
0847     printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
0848 #endif
0849 
0850     if (unlikely(skb->len > HDLC_MAX_MRU)) {
0851         dev_kfree_skb(skb);
0852         dev->stats.tx_errors++;
0853         return NETDEV_TX_OK;
0854     }
0855 
0856     debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
0857 
0858     len = skb->len;
0859 #ifdef __ARMEB__
0860     offset = 0; /* no need to keep alignment */
0861     bytes = len;
0862     mem = skb->data;
0863 #else
0864     offset = (int)skb->data & 3; /* keep 32-bit alignment */
0865     bytes = ALIGN(offset + len, 4);
0866     mem = kmalloc(bytes, GFP_ATOMIC);
0867     if (!mem) {
0868         dev_kfree_skb(skb);
0869         dev->stats.tx_dropped++;
0870         return NETDEV_TX_OK;
0871     }
0872     memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
0873     dev_kfree_skb(skb);
0874 #endif
0875 
0876     phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
0877     if (dma_mapping_error(&dev->dev, phys)) {
0878 #ifdef __ARMEB__
0879         dev_kfree_skb(skb);
0880 #else
0881         kfree(mem);
0882 #endif
0883         dev->stats.tx_dropped++;
0884         return NETDEV_TX_OK;
0885     }
0886 
0887     n = queue_get_desc(txreadyq, port, 1);
0888     BUG_ON(n < 0);
0889     desc = tx_desc_ptr(port, n);
0890 
0891 #ifdef __ARMEB__
0892     port->tx_buff_tab[n] = skb;
0893 #else
0894     port->tx_buff_tab[n] = mem;
0895 #endif
0896     desc->data = phys + offset;
0897     desc->buf_len = desc->pkt_len = len;
0898 
0899     wmb();
0900     queue_put_desc(port->txq, tx_desc_phys(port, n), desc);
0901 
0902     if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
0903 #if DEBUG_TX
0904         printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
0905 #endif
0906         netif_stop_queue(dev);
0907         /* we could miss TX ready interrupt */
0908         if (!qmgr_stat_below_low_watermark(txreadyq)) {
0909 #if DEBUG_TX
0910             printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
0911                    dev->name);
0912 #endif
0913             netif_wake_queue(dev);
0914         }
0915     }
0916 
0917 #if DEBUG_TX
0918     printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
0919 #endif
0920     return NETDEV_TX_OK;
0921 }
0922 
0923 static int request_hdlc_queues(struct port *port)
0924 {
0925     int err;
0926 
0927     err = qmgr_request_queue(port->rxfreeq, RX_DESCS, 0, 0,
0928                  "%s:RX-free", port->netdev->name);
0929     if (err)
0930         return err;
0931 
0932     err = qmgr_request_queue(port->rxq, RX_DESCS, 0, 0,
0933                  "%s:RX", port->netdev->name);
0934     if (err)
0935         goto rel_rxfree;
0936 
0937     err = qmgr_request_queue(port->txq, TX_DESCS, 0, 0,
0938                  "%s:TX", port->netdev->name);
0939     if (err)
0940         goto rel_rx;
0941 
0942     err = qmgr_request_queue(port->txreadyq, TX_DESCS, 0, 0,
0943                  "%s:TX-ready", port->netdev->name);
0944     if (err)
0945         goto rel_tx;
0946 
0947     err = qmgr_request_queue(port->txdoneq, TX_DESCS, 0, 0,
0948                  "%s:TX-done", port->netdev->name);
0949     if (err)
0950         goto rel_txready;
0951     return 0;
0952 
0953 rel_txready:
0954     qmgr_release_queue(port->txreadyq);
0955 rel_tx:
0956     qmgr_release_queue(port->txq);
0957 rel_rx:
0958     qmgr_release_queue(port->rxq);
0959 rel_rxfree:
0960     qmgr_release_queue(port->rxfreeq);
0961     printk(KERN_DEBUG "%s: unable to request hardware queues\n",
0962            port->netdev->name);
0963     return err;
0964 }
0965 
0966 static void release_hdlc_queues(struct port *port)
0967 {
0968     qmgr_release_queue(port->rxfreeq);
0969     qmgr_release_queue(port->rxq);
0970     qmgr_release_queue(port->txdoneq);
0971     qmgr_release_queue(port->txq);
0972     qmgr_release_queue(port->txreadyq);
0973 }
0974 
0975 static int init_hdlc_queues(struct port *port)
0976 {
0977     int i;
0978 
0979     if (!ports_open) {
0980         dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
0981                        POOL_ALLOC_SIZE, 32, 0);
0982         if (!dma_pool)
0983             return -ENOMEM;
0984     }
0985 
0986     port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL,
0987                     &port->desc_tab_phys);
0988     if (!port->desc_tab)
0989         return -ENOMEM;
0990     memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
0991     memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
0992 
0993     /* Setup RX buffers */
0994     for (i = 0; i < RX_DESCS; i++) {
0995         struct desc *desc = rx_desc_ptr(port, i);
0996         buffer_t *buff;
0997         void *data;
0998 #ifdef __ARMEB__
0999         buff = netdev_alloc_skb(port->netdev, RX_SIZE);
1000         if (!buff)
1001             return -ENOMEM;
1002         data = buff->data;
1003 #else
1004         buff = kmalloc(RX_SIZE, GFP_KERNEL);
1005         if (!buff)
1006             return -ENOMEM;
1007         data = buff;
1008 #endif
1009         desc->buf_len = RX_SIZE;
1010         desc->data = dma_map_single(&port->netdev->dev, data,
1011                         RX_SIZE, DMA_FROM_DEVICE);
1012         if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1013             free_buffer(buff);
1014             return -EIO;
1015         }
1016         port->rx_buff_tab[i] = buff;
1017     }
1018 
1019     return 0;
1020 }
1021 
1022 static void destroy_hdlc_queues(struct port *port)
1023 {
1024     int i;
1025 
1026     if (port->desc_tab) {
1027         for (i = 0; i < RX_DESCS; i++) {
1028             struct desc *desc = rx_desc_ptr(port, i);
1029             buffer_t *buff = port->rx_buff_tab[i];
1030 
1031             if (buff) {
1032                 dma_unmap_single(&port->netdev->dev,
1033                          desc->data, RX_SIZE,
1034                          DMA_FROM_DEVICE);
1035                 free_buffer(buff);
1036             }
1037         }
1038         for (i = 0; i < TX_DESCS; i++) {
1039             struct desc *desc = tx_desc_ptr(port, i);
1040             buffer_t *buff = port->tx_buff_tab[i];
1041 
1042             if (buff) {
1043                 dma_unmap_tx(port, desc);
1044                 free_buffer(buff);
1045             }
1046         }
1047         dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1048         port->desc_tab = NULL;
1049     }
1050 
1051     if (!ports_open && dma_pool) {
1052         dma_pool_destroy(dma_pool);
1053         dma_pool = NULL;
1054     }
1055 }
1056 
1057 static irqreturn_t hss_hdlc_dcd_irq(int irq, void *data)
1058 {
1059     struct net_device *dev = data;
1060     struct port *port = dev_to_port(dev);
1061     int val;
1062 
1063     val = gpiod_get_value(port->dcd);
1064     hss_hdlc_set_carrier(dev, val);
1065 
1066     return IRQ_HANDLED;
1067 }
1068 
1069 static int hss_hdlc_open(struct net_device *dev)
1070 {
1071     struct port *port = dev_to_port(dev);
1072     unsigned long flags;
1073     int i, err = 0;
1074     int val;
1075 
1076     err = hdlc_open(dev);
1077     if (err)
1078         return err;
1079 
1080     err = hss_load_firmware(port);
1081     if (err)
1082         goto err_hdlc_close;
1083 
1084     err = request_hdlc_queues(port);
1085     if (err)
1086         goto err_hdlc_close;
1087 
1088     err = init_hdlc_queues(port);
1089     if (err)
1090         goto err_destroy_queues;
1091 
1092     spin_lock_irqsave(&npe_lock, flags);
1093 
1094     /* Set the carrier, the GPIO is flagged active low so this will return
1095      * 1 if DCD is asserted.
1096      */
1097     val = gpiod_get_value(port->dcd);
1098     hss_hdlc_set_carrier(dev, val);
1099 
1100     /* Set up an IRQ for DCD */
1101     err = request_irq(gpiod_to_irq(port->dcd), hss_hdlc_dcd_irq, 0, "IXP4xx HSS", dev);
1102     if (err) {
1103         dev_err(&dev->dev, "ixp4xx_hss: failed to request DCD IRQ (%i)\n", err);
1104         goto err_unlock;
1105     }
1106 
1107     /* GPIOs are flagged active low so this asserts DTR and RTS */
1108     gpiod_set_value(port->dtr, 1);
1109     gpiod_set_value(port->rts, 1);
1110 
1111     spin_unlock_irqrestore(&npe_lock, flags);
1112 
1113     /* Populate queues with buffers, no failure after this point */
1114     for (i = 0; i < TX_DESCS; i++)
1115         queue_put_desc(port->txreadyq,
1116                    tx_desc_phys(port, i), tx_desc_ptr(port, i));
1117 
1118     for (i = 0; i < RX_DESCS; i++)
1119         queue_put_desc(port->rxfreeq,
1120                    rx_desc_phys(port, i), rx_desc_ptr(port, i));
1121 
1122     napi_enable(&port->napi);
1123     netif_start_queue(dev);
1124 
1125     qmgr_set_irq(port->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1126              hss_hdlc_rx_irq, dev);
1127 
1128     qmgr_set_irq(port->txdoneq, QUEUE_IRQ_SRC_NOT_EMPTY,
1129              hss_hdlc_txdone_irq, dev);
1130     qmgr_enable_irq(port->txdoneq);
1131 
1132     ports_open++;
1133 
1134     hss_set_hdlc_cfg(port);
1135     hss_config(port);
1136 
1137     hss_start_hdlc(port);
1138 
1139     /* we may already have RX data, enables IRQ */
1140     napi_schedule(&port->napi);
1141     return 0;
1142 
1143 err_unlock:
1144     spin_unlock_irqrestore(&npe_lock, flags);
1145 err_destroy_queues:
1146     destroy_hdlc_queues(port);
1147     release_hdlc_queues(port);
1148 err_hdlc_close:
1149     hdlc_close(dev);
1150     return err;
1151 }
1152 
1153 static int hss_hdlc_close(struct net_device *dev)
1154 {
1155     struct port *port = dev_to_port(dev);
1156     unsigned long flags;
1157     int i, buffs = RX_DESCS; /* allocated RX buffers */
1158 
1159     spin_lock_irqsave(&npe_lock, flags);
1160     ports_open--;
1161     qmgr_disable_irq(port->rxq);
1162     netif_stop_queue(dev);
1163     napi_disable(&port->napi);
1164 
1165     hss_stop_hdlc(port);
1166 
1167     while (queue_get_desc(port->rxfreeq, port, 0) >= 0)
1168         buffs--;
1169     while (queue_get_desc(port->rxq, port, 0) >= 0)
1170         buffs--;
1171 
1172     if (buffs)
1173         netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1174                 buffs);
1175 
1176     buffs = TX_DESCS;
1177     while (queue_get_desc(port->txq, port, 1) >= 0)
1178         buffs--; /* cancel TX */
1179 
1180     i = 0;
1181     do {
1182         while (queue_get_desc(port->txreadyq, port, 1) >= 0)
1183             buffs--;
1184         if (!buffs)
1185             break;
1186     } while (++i < MAX_CLOSE_WAIT);
1187 
1188     if (buffs)
1189         netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1190                 buffs);
1191 #if DEBUG_CLOSE
1192     if (!buffs)
1193         printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1194 #endif
1195     qmgr_disable_irq(port->txdoneq);
1196 
1197     free_irq(gpiod_to_irq(port->dcd), dev);
1198     /* GPIOs are flagged active low so this de-asserts DTR and RTS */
1199     gpiod_set_value(port->dtr, 0);
1200     gpiod_set_value(port->rts, 0);
1201     spin_unlock_irqrestore(&npe_lock, flags);
1202 
1203     destroy_hdlc_queues(port);
1204     release_hdlc_queues(port);
1205     hdlc_close(dev);
1206     return 0;
1207 }
1208 
1209 static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1210                unsigned short parity)
1211 {
1212     struct port *port = dev_to_port(dev);
1213 
1214     if (encoding != ENCODING_NRZ)
1215         return -EINVAL;
1216 
1217     switch (parity) {
1218     case PARITY_CRC16_PR1_CCITT:
1219         port->hdlc_cfg = 0;
1220         return 0;
1221 
1222     case PARITY_CRC32_PR1_CCITT:
1223         port->hdlc_cfg = PKT_HDLC_CRC_32;
1224         return 0;
1225 
1226     default:
1227         return -EINVAL;
1228     }
1229 }
1230 
1231 static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1232                u32 *best, u32 *best_diff, u32 *reg)
1233 {
1234     /* a is 10-bit, b is 10-bit, c is 12-bit */
1235     u64 new_rate;
1236     u32 new_diff;
1237 
1238     new_rate = timer_freq * (u64)(c + 1);
1239     do_div(new_rate, a * (c + 1) + b + 1);
1240     new_diff = abs((u32)new_rate - rate);
1241 
1242     if (new_diff < *best_diff) {
1243         *best = new_rate;
1244         *best_diff = new_diff;
1245         *reg = (a << 22) | (b << 12) | c;
1246     }
1247     return new_diff;
1248 }
1249 
1250 static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1251 {
1252     u32 a, b, diff = 0xFFFFFFFF;
1253 
1254     a = timer_freq / rate;
1255 
1256     if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1257         check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1258         return;
1259     }
1260     if (a == 0) { /* > 66.666 MHz */
1261         a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1262         rate = timer_freq;
1263     }
1264 
1265     if (rate * a == timer_freq) { /* don't divide by 0 later */
1266         check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1267         return;
1268     }
1269 
1270     for (b = 0; b < 0x400; b++) {
1271         u64 c = (b + 1) * (u64)rate;
1272 
1273         do_div(c, timer_freq - rate * a);
1274         c--;
1275         if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1276             if (b == 0 && /* also try a bit higher rate */
1277                 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1278                      &diff, reg))
1279                 return;
1280             check_clock(timer_freq, rate, a, b, 0xFFF, best,
1281                     &diff, reg);
1282             return;
1283         }
1284         if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1285             return;
1286         if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1287                  reg))
1288             return;
1289     }
1290 }
1291 
1292 static int hss_hdlc_set_clock(struct port *port, unsigned int clock_type)
1293 {
1294     switch (clock_type) {
1295     case CLOCK_DEFAULT:
1296     case CLOCK_EXT:
1297         gpiod_set_value(port->clk_internal, 0);
1298         return CLOCK_EXT;
1299     case CLOCK_INT:
1300         gpiod_set_value(port->clk_internal, 1);
1301         return CLOCK_INT;
1302     default:
1303         return -EINVAL;
1304     }
1305 }
1306 
1307 static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
1308 {
1309     const size_t size = sizeof(sync_serial_settings);
1310     sync_serial_settings new_line;
1311     sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1312     struct port *port = dev_to_port(dev);
1313     unsigned long flags;
1314     int clk;
1315 
1316     switch (ifs->type) {
1317     case IF_GET_IFACE:
1318         ifs->type = IF_IFACE_V35;
1319         if (ifs->size < size) {
1320             ifs->size = size; /* data size wanted */
1321             return -ENOBUFS;
1322         }
1323         memset(&new_line, 0, sizeof(new_line));
1324         new_line.clock_type = port->clock_type;
1325         new_line.clock_rate = port->clock_rate;
1326         new_line.loopback = port->loopback;
1327         if (copy_to_user(line, &new_line, size))
1328             return -EFAULT;
1329         return 0;
1330 
1331     case IF_IFACE_SYNC_SERIAL:
1332     case IF_IFACE_V35:
1333         if (!capable(CAP_NET_ADMIN))
1334             return -EPERM;
1335         if (copy_from_user(&new_line, line, size))
1336             return -EFAULT;
1337 
1338         clk = new_line.clock_type;
1339         hss_hdlc_set_clock(port, clk);
1340 
1341         if (clk != CLOCK_EXT && clk != CLOCK_INT)
1342             return -EINVAL; /* No such clock setting */
1343 
1344         if (new_line.loopback != 0 && new_line.loopback != 1)
1345             return -EINVAL;
1346 
1347         port->clock_type = clk; /* Update settings */
1348         if (clk == CLOCK_INT) {
1349             find_best_clock(IXP4XX_TIMER_FREQ,
1350                     new_line.clock_rate,
1351                     &port->clock_rate, &port->clock_reg);
1352         } else {
1353             port->clock_rate = 0;
1354             port->clock_reg = CLK42X_SPEED_2048KHZ;
1355         }
1356         port->loopback = new_line.loopback;
1357 
1358         spin_lock_irqsave(&npe_lock, flags);
1359 
1360         if (dev->flags & IFF_UP)
1361             hss_config(port);
1362 
1363         if (port->loopback || port->carrier)
1364             netif_carrier_on(port->netdev);
1365         else
1366             netif_carrier_off(port->netdev);
1367         spin_unlock_irqrestore(&npe_lock, flags);
1368 
1369         return 0;
1370 
1371     default:
1372         return hdlc_ioctl(dev, ifs);
1373     }
1374 }
1375 
1376 /*****************************************************************************
1377  * initialization
1378  ****************************************************************************/
1379 
1380 static const struct net_device_ops hss_hdlc_ops = {
1381     .ndo_open       = hss_hdlc_open,
1382     .ndo_stop       = hss_hdlc_close,
1383     .ndo_start_xmit = hdlc_start_xmit,
1384     .ndo_siocwandev = hss_hdlc_ioctl,
1385 };
1386 
1387 static int ixp4xx_hss_probe(struct platform_device *pdev)
1388 {
1389     struct of_phandle_args queue_spec;
1390     struct of_phandle_args npe_spec;
1391     struct device *dev = &pdev->dev;
1392     struct net_device *ndev;
1393     struct device_node *np;
1394     struct regmap *rmap;
1395     struct port *port;
1396     hdlc_device *hdlc;
1397     int err;
1398     u32 val;
1399 
1400     /*
1401      * Go into the syscon and check if we have the HSS and HDLC
1402      * features available, else this will not work.
1403      */
1404     rmap = syscon_regmap_lookup_by_compatible("syscon");
1405     if (IS_ERR(rmap))
1406         return dev_err_probe(dev, PTR_ERR(rmap),
1407                      "failed to look up syscon\n");
1408 
1409     val = cpu_ixp4xx_features(rmap);
1410 
1411     if ((val & (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1412         (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) {
1413         dev_err(dev, "HDLC and HSS feature unavailable in platform\n");
1414         return -ENODEV;
1415     }
1416 
1417     np = dev->of_node;
1418 
1419     port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1420     if (!port)
1421         return -ENOMEM;
1422 
1423     err = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
1424                            &npe_spec);
1425     if (err)
1426         return dev_err_probe(dev, err, "no NPE engine specified\n");
1427     /* NPE ID 0x00, 0x10, 0x20... */
1428     port->npe = npe_request(npe_spec.args[0] << 4);
1429     if (!port->npe) {
1430         dev_err(dev, "unable to obtain NPE instance\n");
1431         return -ENODEV;
1432     }
1433 
1434     /* Get the TX ready queue as resource from queue manager */
1435     err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-txready", 1, 0,
1436                            &queue_spec);
1437     if (err)
1438         return dev_err_probe(dev, err, "no txready queue phandle\n");
1439     port->txreadyq = queue_spec.args[0];
1440     /* Get the RX trig queue as resource from queue manager */
1441     err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-rxtrig", 1, 0,
1442                            &queue_spec);
1443     if (err)
1444         return dev_err_probe(dev, err, "no rxtrig queue phandle\n");
1445     port->rxtrigq = queue_spec.args[0];
1446     /* Get the RX queue as resource from queue manager */
1447     err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rx", 1, 0,
1448                            &queue_spec);
1449     if (err)
1450         return dev_err_probe(dev, err, "no RX queue phandle\n");
1451     port->rxq = queue_spec.args[0];
1452     /* Get the TX queue as resource from queue manager */
1453     err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-tx", 1, 0,
1454                            &queue_spec);
1455     if (err)
1456         return dev_err_probe(dev, err, "no RX queue phandle\n");
1457     port->txq = queue_spec.args[0];
1458     /* Get the RX free queue as resource from queue manager */
1459     err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rxfree", 1, 0,
1460                            &queue_spec);
1461     if (err)
1462         return dev_err_probe(dev, err, "no RX free queue phandle\n");
1463     port->rxfreeq = queue_spec.args[0];
1464     /* Get the TX done queue as resource from queue manager */
1465     err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-txdone", 1, 0,
1466                            &queue_spec);
1467     if (err)
1468         return dev_err_probe(dev, err, "no TX done queue phandle\n");
1469     port->txdoneq = queue_spec.args[0];
1470 
1471     /* Obtain all the line control GPIOs */
1472     port->cts = devm_gpiod_get(dev, "cts", GPIOD_OUT_LOW);
1473     if (IS_ERR(port->cts))
1474         return dev_err_probe(dev, PTR_ERR(port->cts), "unable to get CTS GPIO\n");
1475     port->rts = devm_gpiod_get(dev, "rts", GPIOD_OUT_LOW);
1476     if (IS_ERR(port->rts))
1477         return dev_err_probe(dev, PTR_ERR(port->rts), "unable to get RTS GPIO\n");
1478     port->dcd = devm_gpiod_get(dev, "dcd", GPIOD_IN);
1479     if (IS_ERR(port->dcd))
1480         return dev_err_probe(dev, PTR_ERR(port->dcd), "unable to get DCD GPIO\n");
1481     port->dtr = devm_gpiod_get(dev, "dtr", GPIOD_OUT_LOW);
1482     if (IS_ERR(port->dtr))
1483         return dev_err_probe(dev, PTR_ERR(port->dtr), "unable to get DTR GPIO\n");
1484     port->clk_internal = devm_gpiod_get(dev, "clk-internal", GPIOD_OUT_LOW);
1485     if (IS_ERR(port->clk_internal))
1486         return dev_err_probe(dev, PTR_ERR(port->clk_internal),
1487                      "unable to get CLK internal GPIO\n");
1488 
1489     ndev = alloc_hdlcdev(port);
1490     port->netdev = alloc_hdlcdev(port);
1491     if (!port->netdev) {
1492         err = -ENOMEM;
1493         goto err_plat;
1494     }
1495 
1496     SET_NETDEV_DEV(ndev, &pdev->dev);
1497     hdlc = dev_to_hdlc(ndev);
1498     hdlc->attach = hss_hdlc_attach;
1499     hdlc->xmit = hss_hdlc_xmit;
1500     ndev->netdev_ops = &hss_hdlc_ops;
1501     ndev->tx_queue_len = 100;
1502     port->clock_type = CLOCK_EXT;
1503     port->clock_rate = 0;
1504     port->clock_reg = CLK42X_SPEED_2048KHZ;
1505     port->id = pdev->id;
1506     port->dev = &pdev->dev;
1507     netif_napi_add_weight(ndev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1508 
1509     err = register_hdlc_device(ndev);
1510     if (err)
1511         goto err_free_netdev;
1512 
1513     platform_set_drvdata(pdev, port);
1514 
1515     netdev_info(ndev, "initialized\n");
1516     return 0;
1517 
1518 err_free_netdev:
1519     free_netdev(ndev);
1520 err_plat:
1521     npe_release(port->npe);
1522     return err;
1523 }
1524 
1525 static int ixp4xx_hss_remove(struct platform_device *pdev)
1526 {
1527     struct port *port = platform_get_drvdata(pdev);
1528 
1529     unregister_hdlc_device(port->netdev);
1530     free_netdev(port->netdev);
1531     npe_release(port->npe);
1532     return 0;
1533 }
1534 
1535 static struct platform_driver ixp4xx_hss_driver = {
1536     .driver.name    = DRV_NAME,
1537     .probe      = ixp4xx_hss_probe,
1538     .remove     = ixp4xx_hss_remove,
1539 };
1540 module_platform_driver(ixp4xx_hss_driver);
1541 
1542 MODULE_AUTHOR("Krzysztof Halasa");
1543 MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1544 MODULE_LICENSE("GPL v2");
1545 MODULE_ALIAS("platform:ixp4xx_hss");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!