net/wan/hd64570.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __HD64570_H
0003 #define __HD64570_H
0004
0005 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
0006    and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.
0007
0008    Source: HD64570 SCA User's Manual
0009 */
0010
0011
0012
0013 /* SCA Control Registers */
0014 #define LPR    0x00     /* Low Power */
0015
0016 /* Wait controller registers */
0017 #define PABR0  0x02     /* Physical Address Boundary 0 */
0018 #define PABR1  0x03     /* Physical Address Boundary 1 */
0019 #define WCRL   0x04     /* Wait Control L */
0020 #define WCRM   0x05     /* Wait Control M */
0021 #define WCRH   0x06     /* Wait Control H */
0022
0023 #define PCR    0x08     /* DMA Priority Control */
0024 #define DMER   0x09     /* DMA Master Enable */
0025
0026
0027 /* Interrupt registers */
0028 #define ISR0   0x10     /* Interrupt Status 0  */
0029 #define ISR1   0x11     /* Interrupt Status 1  */
0030 #define ISR2   0x12     /* Interrupt Status 2  */
0031
0032 #define IER0   0x14     /* Interrupt Enable 0  */
0033 #define IER1   0x15     /* Interrupt Enable 1  */
0034 #define IER2   0x16     /* Interrupt Enable 2  */
0035
0036 #define ITCR   0x18     /* Interrupt Control */
0037 #define IVR    0x1A     /* Interrupt Vector */
0038 #define IMVR   0x1C     /* Interrupt Modified Vector */
0039
0040
0041
0042 /* MSCI channel (port) 0 registers - offset 0x20
0043    MSCI channel (port) 1 registers - offset 0x40 */
0044
0045 #define MSCI0_OFFSET 0x20
0046 #define MSCI1_OFFSET 0x40
0047
0048 #define TRBL   0x00     /* TX/RX buffer L */
0049 #define TRBH   0x01     /* TX/RX buffer H */
0050 #define ST0    0x02     /* Status 0 */
0051 #define ST1    0x03     /* Status 1 */
0052 #define ST2    0x04     /* Status 2 */
0053 #define ST3    0x05     /* Status 3 */
0054 #define FST    0x06     /* Frame Status  */
0055 #define IE0    0x08     /* Interrupt Enable 0 */
0056 #define IE1    0x09     /* Interrupt Enable 1 */
0057 #define IE2    0x0A     /* Interrupt Enable 2 */
0058 #define FIE    0x0B     /* Frame Interrupt Enable  */
0059 #define CMD    0x0C     /* Command */
0060 #define MD0    0x0E     /* Mode 0 */
0061 #define MD1    0x0F     /* Mode 1 */
0062 #define MD2    0x10     /* Mode 2 */
0063 #define CTL    0x11     /* Control */
0064 #define SA0    0x12     /* Sync/Address 0 */
0065 #define SA1    0x13     /* Sync/Address 1 */
0066 #define IDL    0x14     /* Idle Pattern */
0067 #define TMC    0x15     /* Time Constant */
0068 #define RXS    0x16     /* RX Clock Source */
0069 #define TXS    0x17     /* TX Clock Source */
0070 #define TRC0   0x18     /* TX Ready Control 0 */
0071 #define TRC1   0x19     /* TX Ready Control 1 */
0072 #define RRC    0x1A     /* RX Ready Control */
0073 #define CST0   0x1C     /* Current Status 0 */
0074 #define CST1   0x1D     /* Current Status 1 */
0075
0076
0077 /* Timer channel 0 (port 0 RX) registers - offset 0x60
0078    Timer channel 1 (port 0 TX) registers - offset 0x68
0079    Timer channel 2 (port 1 RX) registers - offset 0x70
0080    Timer channel 3 (port 1 TX) registers - offset 0x78
0081 */
0082
0083 #define TIMER0RX_OFFSET 0x60
0084 #define TIMER0TX_OFFSET 0x68
0085 #define TIMER1RX_OFFSET 0x70
0086 #define TIMER1TX_OFFSET 0x78
0087
0088 #define TCNTL  0x00     /* Up-counter L */
0089 #define TCNTH  0x01     /* Up-counter H */
0090 #define TCONRL 0x02     /* Constant L */
0091 #define TCONRH 0x03     /* Constant H */
0092 #define TCSR   0x04     /* Control/Status */
0093 #define TEPR   0x05     /* Expand Prescale */
0094
0095
0096
0097 /* DMA channel 0 (port 0 RX) registers - offset 0x80
0098    DMA channel 1 (port 0 TX) registers - offset 0xA0
0099    DMA channel 2 (port 1 RX) registers - offset 0xC0
0100    DMA channel 3 (port 1 TX) registers - offset 0xE0
0101 */
0102
0103 #define DMAC0RX_OFFSET 0x80
0104 #define DMAC0TX_OFFSET 0xA0
0105 #define DMAC1RX_OFFSET 0xC0
0106 #define DMAC1TX_OFFSET 0xE0
0107
0108 #define BARL   0x00     /* Buffer Address L (chained block) */
0109 #define BARH   0x01     /* Buffer Address H (chained block) */
0110 #define BARB   0x02     /* Buffer Address B (chained block) */
0111
0112 #define DARL   0x00     /* RX Destination Addr L (single block) */
0113 #define DARH   0x01     /* RX Destination Addr H (single block) */
0114 #define DARB   0x02     /* RX Destination Addr B (single block) */
0115
0116 #define SARL   0x04     /* TX Source Address L (single block) */
0117 #define SARH   0x05     /* TX Source Address H (single block) */
0118 #define SARB   0x06     /* TX Source Address B (single block) */
0119
0120 #define CPB    0x06     /* Chain Pointer Base (chained block) */
0121
0122 #define CDAL   0x08     /* Current Descriptor Addr L (chained block) */
0123 #define CDAH   0x09     /* Current Descriptor Addr H (chained block) */
0124 #define EDAL   0x0A     /* Error Descriptor Addr L (chained block) */
0125 #define EDAH   0x0B     /* Error Descriptor Addr H (chained block) */
0126 #define BFLL   0x0C     /* RX Receive Buffer Length L (chained block)*/
0127 #define BFLH   0x0D     /* RX Receive Buffer Length H (chained block)*/
0128 #define BCRL   0x0E     /* Byte Count L */
0129 #define BCRH   0x0F     /* Byte Count H */
0130 #define DSR    0x10     /* DMA Status */
0131 #define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
0132 #define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
0133 #define DMR    0x11     /* DMA Mode */
0134 #define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
0135 #define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
0136 #define FCT    0x13     /* Frame End Interrupt Counter */
0137 #define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
0138 #define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
0139 #define DIR    0x14     /* DMA Interrupt Enable */
0140 #define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
0141 #define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
0142 #define DCR    0x15     /* DMA Command  */
0143 #define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
0144 #define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
0145
0146
0147
0148
0149 /* Descriptor Structure */
0150
0151 typedef struct {
0152     u16 cp;         /* Chain Pointer */
0153     u32 bp;         /* Buffer Pointer (24 bits) */
0154     u16 len;        /* Data Length */
0155     u8 stat;        /* Status */
0156     u8 unused;      /* pads to 2-byte boundary */
0157 }__packed pkt_desc;
0158
0159
0160 /* Packet Descriptor Status bits */
0161
0162 #define ST_TX_EOM     0x80  /* End of frame */
0163 #define ST_TX_EOT     0x01  /* End of transmission */
0164
0165 #define ST_RX_EOM     0x80  /* End of frame */
0166 #define ST_RX_SHORT   0x40  /* Short frame */
0167 #define ST_RX_ABORT   0x20  /* Abort */
0168 #define ST_RX_RESBIT  0x10  /* Residual bit */
0169 #define ST_RX_OVERRUN 0x08  /* Overrun */
0170 #define ST_RX_CRC     0x04  /* CRC */
0171
0172 #define ST_ERROR_MASK 0x7C
0173
0174 #define DIR_EOTE      0x80      /* Transfer completed */
0175 #define DIR_EOME      0x40      /* Frame Transfer Completed (chained-block) */
0176 #define DIR_BOFE      0x20      /* Buffer Overflow/Underflow (chained-block)*/
0177 #define DIR_COFE      0x10      /* Counter Overflow (chained-block) */
0178
0179
0180 #define DSR_EOT       0x80      /* Transfer completed */
0181 #define DSR_EOM       0x40      /* Frame Transfer Completed (chained-block) */
0182 #define DSR_BOF       0x20      /* Buffer Overflow/Underflow (chained-block)*/
0183 #define DSR_COF       0x10      /* Counter Overflow (chained-block) */
0184 #define DSR_DE        0x02  /* DMA Enable */
0185 #define DSR_DWE       0x01      /* DMA Write Disable */
0186
0187 /* DMA Master Enable Register (DMER) bits */
0188 #define DMER_DME      0x80  /* DMA Master Enable */
0189
0190
0191 #define CMD_RESET     0x21  /* Reset Channel */
0192 #define CMD_TX_ENABLE 0x02  /* Start transmitter */
0193 #define CMD_RX_ENABLE 0x12  /* Start receiver */
0194
0195 #define MD0_HDLC      0x80  /* Bit-sync HDLC mode */
0196 #define MD0_CRC_ENA   0x04  /* Enable CRC code calculation */
0197 #define MD0_CRC_CCITT 0x02  /* CCITT CRC instead of CRC-16 */
0198 #define MD0_CRC_PR1   0x01  /* Initial all-ones instead of all-zeros */
0199
0200 #define MD0_CRC_NONE  0x00
0201 #define MD0_CRC_16_0  0x04
0202 #define MD0_CRC_16    0x05
0203 #define MD0_CRC_ITU_0 0x06
0204 #define MD0_CRC_ITU   0x07
0205
0206 #define MD2_NRZ       0x00
0207 #define MD2_NRZI      0x20
0208 #define MD2_MANCHESTER 0x80
0209 #define MD2_FM_MARK   0xA0
0210 #define MD2_FM_SPACE  0xC0
0211 #define MD2_LOOPBACK  0x03      /* Local data Loopback */
0212
0213 #define CTL_NORTS     0x01
0214 #define CTL_IDLE      0x10  /* Transmit an idle pattern */
0215 #define CTL_UDRNC     0x20  /* Idle after CRC or FCS+flag transmission */
0216
0217 #define ST0_TXRDY     0x02  /* TX ready */
0218 #define ST0_RXRDY     0x01  /* RX ready */
0219
0220 #define ST1_UDRN      0x80  /* MSCI TX underrun */
0221 #define ST1_CDCD      0x04  /* DCD level changed */
0222
0223 #define ST3_CTS       0x08  /* modem input - /CTS */
0224 #define ST3_DCD       0x04  /* modem input - /DCD */
0225
0226 #define IE0_TXINT     0x80  /* TX INT MSCI interrupt enable */
0227 #define IE0_RXINTA    0x40  /* RX INT A MSCI interrupt enable */
0228 #define IE1_UDRN      0x80  /* TX underrun MSCI interrupt enable */
0229 #define IE1_CDCD      0x04  /* DCD level changed */
0230
0231 #define DCR_ABORT     0x01  /* Software abort command */
0232 #define DCR_CLEAR_EOF 0x02  /* Clear EOF interrupt */
0233
0234 /* TX and RX Clock Source - RXS and TXS */
0235 #define CLK_BRG_MASK  0x0F
0236 #define CLK_LINE_RX   0x00  /* TX/RX clock line input */
0237 #define CLK_LINE_TX   0x00  /* TX/RX line input */
0238 #define CLK_BRG_RX    0x40  /* internal baud rate generator */
0239 #define CLK_BRG_TX    0x40  /* internal baud rate generator */
0240 #define CLK_RXCLK_TX  0x60  /* TX clock from RX clock */
0241
0242 #endif