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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Hitachi SCA HD64570 driver for Linux
0004  *
0005  * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
0006  *
0007  * Source of information: Hitachi HD64570 SCA User's Manual
0008  *
0009  * We use the following SCA memory map:
0010  *
0011  * Packet buffer descriptor rings - starting from winbase or win0base:
0012  * rx_ring_buffers * sizeof(pkt_desc) = logical channel #0 RX ring
0013  * tx_ring_buffers * sizeof(pkt_desc) = logical channel #0 TX ring
0014  * rx_ring_buffers * sizeof(pkt_desc) = logical channel #1 RX ring (if used)
0015  * tx_ring_buffers * sizeof(pkt_desc) = logical channel #1 TX ring (if used)
0016  *
0017  * Packet data buffers - starting from winbase + buff_offset:
0018  * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers
0019  * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers
0020  * rx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 RX buffers (if used)
0021  * tx_ring_buffers * HDLC_MAX_MRU     = logical channel #0 TX buffers (if used)
0022  */
0023 
0024 #include <linux/bitops.h>
0025 #include <linux/errno.h>
0026 #include <linux/fcntl.h>
0027 #include <linux/hdlc.h>
0028 #include <linux/in.h>
0029 #include <linux/interrupt.h>
0030 #include <linux/ioport.h>
0031 #include <linux/jiffies.h>
0032 #include <linux/kernel.h>
0033 #include <linux/module.h>
0034 #include <linux/netdevice.h>
0035 #include <linux/skbuff.h>
0036 #include <linux/string.h>
0037 #include <linux/types.h>
0038 #include <asm/io.h>
0039 #include <linux/uaccess.h>
0040 #include "hd64570.h"
0041 
0042 #define get_msci(port)    (phy_node(port) ?   MSCI1_OFFSET :   MSCI0_OFFSET)
0043 #define get_dmac_rx(port) (phy_node(port) ? DMAC1RX_OFFSET : DMAC0RX_OFFSET)
0044 #define get_dmac_tx(port) (phy_node(port) ? DMAC1TX_OFFSET : DMAC0TX_OFFSET)
0045 
0046 #define SCA_INTR_MSCI(node)    (node ? 0x10 : 0x01)
0047 #define SCA_INTR_DMAC_RX(node) (node ? 0x20 : 0x02)
0048 #define SCA_INTR_DMAC_TX(node) (node ? 0x40 : 0x04)
0049 
0050 static inline struct net_device *port_to_dev(port_t *port)
0051 {
0052     return port->dev;
0053 }
0054 
0055 static inline int sca_intr_status(card_t *card)
0056 {
0057     u8 result = 0;
0058     u8 isr0 = sca_in(ISR0, card);
0059     u8 isr1 = sca_in(ISR1, card);
0060 
0061     if (isr1 & 0x03)
0062         result |= SCA_INTR_DMAC_RX(0);
0063     if (isr1 & 0x0C)
0064         result |= SCA_INTR_DMAC_TX(0);
0065     if (isr1 & 0x30)
0066         result |= SCA_INTR_DMAC_RX(1);
0067     if (isr1 & 0xC0)
0068         result |= SCA_INTR_DMAC_TX(1);
0069     if (isr0 & 0x0F)
0070         result |= SCA_INTR_MSCI(0);
0071     if (isr0 & 0xF0)
0072         result |= SCA_INTR_MSCI(1);
0073 
0074     if (!(result & SCA_INTR_DMAC_TX(0)))
0075         if (sca_in(DSR_TX(0), card) & DSR_EOM)
0076             result |= SCA_INTR_DMAC_TX(0);
0077     if (!(result & SCA_INTR_DMAC_TX(1)))
0078         if (sca_in(DSR_TX(1), card) & DSR_EOM)
0079             result |= SCA_INTR_DMAC_TX(1);
0080 
0081     return result;
0082 }
0083 
0084 static inline port_t *dev_to_port(struct net_device *dev)
0085 {
0086     return dev_to_hdlc(dev)->priv;
0087 }
0088 
0089 static inline u16 next_desc(port_t *port, u16 desc, int transmit)
0090 {
0091     return (desc + 1) % (transmit ? port_to_card(port)->tx_ring_buffers
0092                  : port_to_card(port)->rx_ring_buffers);
0093 }
0094 
0095 static inline u16 desc_abs_number(port_t *port, u16 desc, int transmit)
0096 {
0097     u16 rx_buffs = port_to_card(port)->rx_ring_buffers;
0098     u16 tx_buffs = port_to_card(port)->tx_ring_buffers;
0099 
0100     desc %= (transmit ? tx_buffs : rx_buffs); // called with "X + 1" etc.
0101     return log_node(port) * (rx_buffs + tx_buffs) +
0102         transmit * rx_buffs + desc;
0103 }
0104 
0105 static inline u16 desc_offset(port_t *port, u16 desc, int transmit)
0106 {
0107     /* Descriptor offset always fits in 16 bits */
0108     return desc_abs_number(port, desc, transmit) * sizeof(pkt_desc);
0109 }
0110 
0111 static inline pkt_desc __iomem *desc_address(port_t *port, u16 desc,
0112                          int transmit)
0113 {
0114 #ifdef PAGE0_ALWAYS_MAPPED
0115     return (pkt_desc __iomem *)(win0base(port_to_card(port))
0116                     + desc_offset(port, desc, transmit));
0117 #else
0118     return (pkt_desc __iomem *)(winbase(port_to_card(port))
0119                     + desc_offset(port, desc, transmit));
0120 #endif
0121 }
0122 
0123 static inline u32 buffer_offset(port_t *port, u16 desc, int transmit)
0124 {
0125     return port_to_card(port)->buff_offset +
0126         desc_abs_number(port, desc, transmit) * (u32)HDLC_MAX_MRU;
0127 }
0128 
0129 static inline void sca_set_carrier(port_t *port)
0130 {
0131     if (!(sca_in(get_msci(port) + ST3, port_to_card(port)) & ST3_DCD)) {
0132 #ifdef DEBUG_LINK
0133         printk(KERN_DEBUG "%s: sca_set_carrier on\n",
0134                port_to_dev(port)->name);
0135 #endif
0136         netif_carrier_on(port_to_dev(port));
0137     } else {
0138 #ifdef DEBUG_LINK
0139         printk(KERN_DEBUG "%s: sca_set_carrier off\n",
0140                port_to_dev(port)->name);
0141 #endif
0142         netif_carrier_off(port_to_dev(port));
0143     }
0144 }
0145 
0146 static void sca_init_port(port_t *port)
0147 {
0148     card_t *card = port_to_card(port);
0149     int transmit, i;
0150 
0151     port->rxin = 0;
0152     port->txin = 0;
0153     port->txlast = 0;
0154 
0155 #ifndef PAGE0_ALWAYS_MAPPED
0156     openwin(card, 0);
0157 #endif
0158 
0159     for (transmit = 0; transmit < 2; transmit++) {
0160         u16 dmac = transmit ? get_dmac_tx(port) : get_dmac_rx(port);
0161         u16 buffs = transmit ? card->tx_ring_buffers
0162             : card->rx_ring_buffers;
0163 
0164         for (i = 0; i < buffs; i++) {
0165             pkt_desc __iomem *desc = desc_address(port, i, transmit);
0166             u16 chain_off = desc_offset(port, i + 1, transmit);
0167             u32 buff_off = buffer_offset(port, i, transmit);
0168 
0169             writew(chain_off, &desc->cp);
0170             writel(buff_off, &desc->bp);
0171             writew(0, &desc->len);
0172             writeb(0, &desc->stat);
0173         }
0174 
0175         /* DMA disable - to halt state */
0176         sca_out(0, transmit ? DSR_TX(phy_node(port)) :
0177             DSR_RX(phy_node(port)), card);
0178         /* software ABORT - to initial state */
0179         sca_out(DCR_ABORT, transmit ? DCR_TX(phy_node(port)) :
0180             DCR_RX(phy_node(port)), card);
0181 
0182         /* current desc addr */
0183         sca_out(0, dmac + CPB, card); /* pointer base */
0184         sca_outw(desc_offset(port, 0, transmit), dmac + CDAL, card);
0185         if (!transmit)
0186             sca_outw(desc_offset(port, buffs - 1, transmit),
0187                  dmac + EDAL, card);
0188         else
0189             sca_outw(desc_offset(port, 0, transmit), dmac + EDAL,
0190                  card);
0191 
0192         /* clear frame end interrupt counter */
0193         sca_out(DCR_CLEAR_EOF, transmit ? DCR_TX(phy_node(port)) :
0194             DCR_RX(phy_node(port)), card);
0195 
0196         if (!transmit) { /* Receive */
0197             /* set buffer length */
0198             sca_outw(HDLC_MAX_MRU, dmac + BFLL, card);
0199             /* Chain mode, Multi-frame */
0200             sca_out(0x14, DMR_RX(phy_node(port)), card);
0201             sca_out(DIR_EOME | DIR_BOFE, DIR_RX(phy_node(port)),
0202                 card);
0203             /* DMA enable */
0204             sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
0205         } else {    /* Transmit */
0206             /* Chain mode, Multi-frame */
0207             sca_out(0x14, DMR_TX(phy_node(port)), card);
0208             /* enable underflow interrupts */
0209             sca_out(DIR_BOFE, DIR_TX(phy_node(port)), card);
0210         }
0211     }
0212     sca_set_carrier(port);
0213 }
0214 
0215 #ifdef NEED_SCA_MSCI_INTR
0216 /* MSCI interrupt service */
0217 static inline void sca_msci_intr(port_t *port)
0218 {
0219     u16 msci = get_msci(port);
0220     card_t *card = port_to_card(port);
0221     u8 stat = sca_in(msci + ST1, card); /* read MSCI ST1 status */
0222 
0223     /* Reset MSCI TX underrun and CDCD status bit */
0224     sca_out(stat & (ST1_UDRN | ST1_CDCD), msci + ST1, card);
0225 
0226     if (stat & ST1_UDRN) {
0227         /* TX Underrun error detected */
0228         port_to_dev(port)->stats.tx_errors++;
0229         port_to_dev(port)->stats.tx_fifo_errors++;
0230     }
0231 
0232     if (stat & ST1_CDCD)
0233         sca_set_carrier(port);
0234 }
0235 #endif
0236 
0237 static inline void sca_rx(card_t *card, port_t *port, pkt_desc __iomem *desc,
0238               u16 rxin)
0239 {
0240     struct net_device *dev = port_to_dev(port);
0241     struct sk_buff *skb;
0242     u16 len;
0243     u32 buff;
0244     u32 maxlen;
0245     u8 page;
0246 
0247     len = readw(&desc->len);
0248     skb = dev_alloc_skb(len);
0249     if (!skb) {
0250         dev->stats.rx_dropped++;
0251         return;
0252     }
0253 
0254     buff = buffer_offset(port, rxin, 0);
0255     page = buff / winsize(card);
0256     buff = buff % winsize(card);
0257     maxlen = winsize(card) - buff;
0258 
0259     openwin(card, page);
0260 
0261     if (len > maxlen) {
0262         memcpy_fromio(skb->data, winbase(card) + buff, maxlen);
0263         openwin(card, page + 1);
0264         memcpy_fromio(skb->data + maxlen, winbase(card), len - maxlen);
0265     } else {
0266         memcpy_fromio(skb->data, winbase(card) + buff, len);
0267     }
0268 
0269 #ifndef PAGE0_ALWAYS_MAPPED
0270     openwin(card, 0);   /* select pkt_desc table page back */
0271 #endif
0272     skb_put(skb, len);
0273 #ifdef DEBUG_PKT
0274     printk(KERN_DEBUG "%s RX(%i):", dev->name, skb->len);
0275     debug_frame(skb);
0276 #endif
0277     dev->stats.rx_packets++;
0278     dev->stats.rx_bytes += skb->len;
0279     skb->protocol = hdlc_type_trans(skb, dev);
0280     netif_rx(skb);
0281 }
0282 
0283 /* Receive DMA interrupt service */
0284 static inline void sca_rx_intr(port_t *port)
0285 {
0286     struct net_device *dev = port_to_dev(port);
0287     u16 dmac = get_dmac_rx(port);
0288     card_t *card = port_to_card(port);
0289     u8 stat = sca_in(DSR_RX(phy_node(port)), card); /* read DMA Status */
0290 
0291     /* Reset DSR status bits */
0292     sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
0293         DSR_RX(phy_node(port)), card);
0294 
0295     if (stat & DSR_BOF)
0296         /* Dropped one or more frames */
0297         dev->stats.rx_over_errors++;
0298 
0299     while (1) {
0300         u32 desc_off = desc_offset(port, port->rxin, 0);
0301         pkt_desc __iomem *desc;
0302         u32 cda = sca_inw(dmac + CDAL, card);
0303 
0304         if (cda >= desc_off && (cda < desc_off + sizeof(pkt_desc)))
0305             break;  /* No frame received */
0306 
0307         desc = desc_address(port, port->rxin, 0);
0308         stat = readb(&desc->stat);
0309         if (!(stat & ST_RX_EOM))
0310             port->rxpart = 1; /* partial frame received */
0311         else if ((stat & ST_ERROR_MASK) || port->rxpart) {
0312             dev->stats.rx_errors++;
0313             if (stat & ST_RX_OVERRUN)
0314                 dev->stats.rx_fifo_errors++;
0315             else if ((stat & (ST_RX_SHORT | ST_RX_ABORT |
0316                       ST_RX_RESBIT)) || port->rxpart)
0317                 dev->stats.rx_frame_errors++;
0318             else if (stat & ST_RX_CRC)
0319                 dev->stats.rx_crc_errors++;
0320             if (stat & ST_RX_EOM)
0321                 port->rxpart = 0; /* received last fragment */
0322         } else {
0323             sca_rx(card, port, desc, port->rxin);
0324         }
0325 
0326         /* Set new error descriptor address */
0327         sca_outw(desc_off, dmac + EDAL, card);
0328         port->rxin = next_desc(port, port->rxin, 0);
0329     }
0330 
0331     /* make sure RX DMA is enabled */
0332     sca_out(DSR_DE, DSR_RX(phy_node(port)), card);
0333 }
0334 
0335 /* Transmit DMA interrupt service */
0336 static inline void sca_tx_intr(port_t *port)
0337 {
0338     struct net_device *dev = port_to_dev(port);
0339     u16 dmac = get_dmac_tx(port);
0340     card_t *card = port_to_card(port);
0341     u8 stat;
0342 
0343     spin_lock(&port->lock);
0344 
0345     stat = sca_in(DSR_TX(phy_node(port)), card); /* read DMA Status */
0346 
0347     /* Reset DSR status bits */
0348     sca_out((stat & (DSR_EOT | DSR_EOM | DSR_BOF | DSR_COF)) | DSR_DWE,
0349         DSR_TX(phy_node(port)), card);
0350 
0351     while (1) {
0352         pkt_desc __iomem *desc;
0353 
0354         u32 desc_off = desc_offset(port, port->txlast, 1);
0355         u32 cda = sca_inw(dmac + CDAL, card);
0356 
0357         if (cda >= desc_off && (cda < desc_off + sizeof(pkt_desc)))
0358             break;  /* Transmitter is/will_be sending this frame */
0359 
0360         desc = desc_address(port, port->txlast, 1);
0361         dev->stats.tx_packets++;
0362         dev->stats.tx_bytes += readw(&desc->len);
0363         writeb(0, &desc->stat); /* Free descriptor */
0364         port->txlast = next_desc(port, port->txlast, 1);
0365     }
0366 
0367     netif_wake_queue(dev);
0368     spin_unlock(&port->lock);
0369 }
0370 
0371 static irqreturn_t sca_intr(int irq, void *dev_id)
0372 {
0373     card_t *card = dev_id;
0374     int i;
0375     u8 stat;
0376     int handled = 0;
0377     u8 page = sca_get_page(card);
0378 
0379     while ((stat = sca_intr_status(card)) != 0) {
0380         handled = 1;
0381         for (i = 0; i < 2; i++) {
0382             port_t *port = get_port(card, i);
0383 
0384             if (port) {
0385                 if (stat & SCA_INTR_MSCI(i))
0386                     sca_msci_intr(port);
0387 
0388                 if (stat & SCA_INTR_DMAC_RX(i))
0389                     sca_rx_intr(port);
0390 
0391                 if (stat & SCA_INTR_DMAC_TX(i))
0392                     sca_tx_intr(port);
0393             }
0394         }
0395     }
0396 
0397     openwin(card, page);        /* Restore original page */
0398     return IRQ_RETVAL(handled);
0399 }
0400 
0401 static void sca_set_port(port_t *port)
0402 {
0403     card_t *card = port_to_card(port);
0404     u16 msci = get_msci(port);
0405     u8 md2 = sca_in(msci + MD2, card);
0406     unsigned int tmc, br = 10, brv = 1024;
0407 
0408     if (port->settings.clock_rate > 0) {
0409         /* Try lower br for better accuracy*/
0410         do {
0411             br--;
0412             brv >>= 1; /* brv = 2^9 = 512 max in specs */
0413 
0414             /* Baud Rate = CLOCK_BASE / TMC / 2^BR */
0415             tmc = CLOCK_BASE / brv / port->settings.clock_rate;
0416         } while (br > 1 && tmc <= 128);
0417 
0418         if (tmc < 1) {
0419             tmc = 1;
0420             br = 0; /* For baud=CLOCK_BASE we use tmc=1 br=0 */
0421             brv = 1;
0422         } else if (tmc > 255) {
0423             tmc = 256; /* tmc=0 means 256 - low baud rates */
0424         }
0425 
0426         port->settings.clock_rate = CLOCK_BASE / brv / tmc;
0427     } else {
0428         br = 9; /* Minimum clock rate */
0429         tmc = 256;  /* 8bit = 0 */
0430         port->settings.clock_rate = CLOCK_BASE / (256 * 512);
0431     }
0432 
0433     port->rxs = (port->rxs & ~CLK_BRG_MASK) | br;
0434     port->txs = (port->txs & ~CLK_BRG_MASK) | br;
0435     port->tmc = tmc;
0436 
0437     /* baud divisor - time constant*/
0438     sca_out(port->tmc, msci + TMC, card);
0439 
0440     /* Set BRG bits */
0441     sca_out(port->rxs, msci + RXS, card);
0442     sca_out(port->txs, msci + TXS, card);
0443 
0444     if (port->settings.loopback)
0445         md2 |= MD2_LOOPBACK;
0446     else
0447         md2 &= ~MD2_LOOPBACK;
0448 
0449     sca_out(md2, msci + MD2, card);
0450 }
0451 
0452 static void sca_open(struct net_device *dev)
0453 {
0454     port_t *port = dev_to_port(dev);
0455     card_t *card = port_to_card(port);
0456     u16 msci = get_msci(port);
0457     u8 md0, md2;
0458 
0459     switch (port->encoding) {
0460     case ENCODING_NRZ:
0461         md2 = MD2_NRZ;
0462         break;
0463     case ENCODING_NRZI:
0464         md2 = MD2_NRZI;
0465         break;
0466     case ENCODING_FM_MARK:
0467         md2 = MD2_FM_MARK;
0468         break;
0469     case ENCODING_FM_SPACE:
0470         md2 = MD2_FM_SPACE;
0471         break;
0472     default:
0473         md2 = MD2_MANCHESTER;
0474     }
0475 
0476     if (port->settings.loopback)
0477         md2 |= MD2_LOOPBACK;
0478 
0479     switch (port->parity) {
0480     case PARITY_CRC16_PR0:
0481         md0 = MD0_HDLC | MD0_CRC_16_0;
0482         break;
0483     case PARITY_CRC16_PR1:
0484         md0 = MD0_HDLC | MD0_CRC_16;
0485         break;
0486     case PARITY_CRC16_PR0_CCITT:
0487         md0 = MD0_HDLC | MD0_CRC_ITU_0;
0488         break;
0489     case PARITY_CRC16_PR1_CCITT:
0490         md0 = MD0_HDLC | MD0_CRC_ITU;
0491         break;
0492     default:
0493         md0 = MD0_HDLC | MD0_CRC_NONE;
0494     }
0495 
0496     sca_out(CMD_RESET, msci + CMD, card);
0497     sca_out(md0, msci + MD0, card);
0498     sca_out(0x00, msci + MD1, card); /* no address field check */
0499     sca_out(md2, msci + MD2, card);
0500     sca_out(0x7E, msci + IDL, card); /* flag character 0x7E */
0501     sca_out(CTL_IDLE, msci + CTL, card);
0502 
0503     /* Allow at least 8 bytes before requesting RX DMA operation */
0504     /* TX with higher priority and possibly with shorter transfers */
0505     sca_out(0x07, msci + RRC, card); /* +1=RXRDY/DMA activation condition*/
0506     sca_out(0x10, msci + TRC0, card); /* = TXRDY/DMA activation condition*/
0507     sca_out(0x14, msci + TRC1, card); /* +1=TXRDY/DMA deactiv condition */
0508 
0509 /* We're using the following interrupts:
0510  * - TXINT (DMAC completed all transmisions, underrun or DCD change)
0511  * - all DMA interrupts
0512  */
0513     sca_set_carrier(port);
0514 
0515     /* MSCI TX INT and RX INT A IRQ enable */
0516     sca_out(IE0_TXINT | IE0_RXINTA, msci + IE0, card);
0517     sca_out(IE1_UDRN | IE1_CDCD, msci + IE1, card);
0518     sca_out(sca_in(IER0, card) | (phy_node(port) ? 0xC0 : 0x0C),
0519         IER0, card); /* TXINT and RXINT */
0520     /* enable DMA IRQ */
0521     sca_out(sca_in(IER1, card) | (phy_node(port) ? 0xF0 : 0x0F),
0522         IER1, card);
0523 
0524     sca_out(port->tmc, msci + TMC, card); /* Restore registers */
0525     sca_out(port->rxs, msci + RXS, card);
0526     sca_out(port->txs, msci + TXS, card);
0527     sca_out(CMD_TX_ENABLE, msci + CMD, card);
0528     sca_out(CMD_RX_ENABLE, msci + CMD, card);
0529 
0530     netif_start_queue(dev);
0531 }
0532 
0533 static void sca_close(struct net_device *dev)
0534 {
0535     port_t *port = dev_to_port(dev);
0536     card_t *card = port_to_card(port);
0537 
0538     /* reset channel */
0539     sca_out(CMD_RESET, get_msci(port) + CMD, port_to_card(port));
0540     /* disable MSCI interrupts */
0541     sca_out(sca_in(IER0, card) & (phy_node(port) ? 0x0F : 0xF0),
0542         IER0, card);
0543     /* disable DMA interrupts */
0544     sca_out(sca_in(IER1, card) & (phy_node(port) ? 0x0F : 0xF0),
0545         IER1, card);
0546 
0547     netif_stop_queue(dev);
0548 }
0549 
0550 static int sca_attach(struct net_device *dev, unsigned short encoding,
0551               unsigned short parity)
0552 {
0553     if (encoding != ENCODING_NRZ &&
0554         encoding != ENCODING_NRZI &&
0555         encoding != ENCODING_FM_MARK &&
0556         encoding != ENCODING_FM_SPACE &&
0557         encoding != ENCODING_MANCHESTER)
0558         return -EINVAL;
0559 
0560     if (parity != PARITY_NONE &&
0561         parity != PARITY_CRC16_PR0 &&
0562         parity != PARITY_CRC16_PR1 &&
0563         parity != PARITY_CRC16_PR0_CCITT &&
0564         parity != PARITY_CRC16_PR1_CCITT)
0565         return -EINVAL;
0566 
0567     dev_to_port(dev)->encoding = encoding;
0568     dev_to_port(dev)->parity = parity;
0569     return 0;
0570 }
0571 
0572 #ifdef DEBUG_RINGS
0573 static void sca_dump_rings(struct net_device *dev)
0574 {
0575     port_t *port = dev_to_port(dev);
0576     card_t *card = port_to_card(port);
0577     u16 cnt;
0578 #ifndef PAGE0_ALWAYS_MAPPED
0579     u8 page = sca_get_page(card);
0580 
0581     openwin(card, 0);
0582 #endif
0583 
0584     printk(KERN_DEBUG "RX ring: CDA=%u EDA=%u DSR=%02X in=%u %sactive",
0585            sca_inw(get_dmac_rx(port) + CDAL, card),
0586            sca_inw(get_dmac_rx(port) + EDAL, card),
0587            sca_in(DSR_RX(phy_node(port)), card), port->rxin,
0588            sca_in(DSR_RX(phy_node(port)), card) & DSR_DE ? "" : "in");
0589     for (cnt = 0; cnt < port_to_card(port)->rx_ring_buffers; cnt++)
0590         pr_cont(" %02X", readb(&(desc_address(port, cnt, 0)->stat)));
0591     pr_cont("\n");
0592 
0593     printk(KERN_DEBUG "TX ring: CDA=%u EDA=%u DSR=%02X in=%u "
0594            "last=%u %sactive",
0595            sca_inw(get_dmac_tx(port) + CDAL, card),
0596            sca_inw(get_dmac_tx(port) + EDAL, card),
0597            sca_in(DSR_TX(phy_node(port)), card), port->txin, port->txlast,
0598            sca_in(DSR_TX(phy_node(port)), card) & DSR_DE ? "" : "in");
0599 
0600     for (cnt = 0; cnt < port_to_card(port)->tx_ring_buffers; cnt++)
0601         pr_cont(" %02X", readb(&(desc_address(port, cnt, 1)->stat)));
0602     pr_cont("\n");
0603 
0604     printk(KERN_DEBUG "MSCI: MD: %02x %02x %02x, ST: %02x %02x %02x %02x,"
0605            " FST: %02x CST: %02x %02x\n",
0606            sca_in(get_msci(port) + MD0, card),
0607            sca_in(get_msci(port) + MD1, card),
0608            sca_in(get_msci(port) + MD2, card),
0609            sca_in(get_msci(port) + ST0, card),
0610            sca_in(get_msci(port) + ST1, card),
0611            sca_in(get_msci(port) + ST2, card),
0612            sca_in(get_msci(port) + ST3, card),
0613            sca_in(get_msci(port) + FST, card),
0614            sca_in(get_msci(port) + CST0, card),
0615            sca_in(get_msci(port) + CST1, card));
0616 
0617     printk(KERN_DEBUG "ISR: %02x %02x %02x\n", sca_in(ISR0, card),
0618            sca_in(ISR1, card), sca_in(ISR2, card));
0619 
0620 #ifndef PAGE0_ALWAYS_MAPPED
0621     openwin(card, page); /* Restore original page */
0622 #endif
0623 }
0624 #endif /* DEBUG_RINGS */
0625 
0626 static netdev_tx_t sca_xmit(struct sk_buff *skb, struct net_device *dev)
0627 {
0628     port_t *port = dev_to_port(dev);
0629     card_t *card = port_to_card(port);
0630     pkt_desc __iomem *desc;
0631     u32 buff, len;
0632     u8 page;
0633     u32 maxlen;
0634 
0635     spin_lock_irq(&port->lock);
0636 
0637     desc = desc_address(port, port->txin + 1, 1);
0638     BUG_ON(readb(&desc->stat)); /* previous xmit should stop queue */
0639 
0640 #ifdef DEBUG_PKT
0641     printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
0642     debug_frame(skb);
0643 #endif
0644 
0645     desc = desc_address(port, port->txin, 1);
0646     buff = buffer_offset(port, port->txin, 1);
0647     len = skb->len;
0648     page = buff / winsize(card);
0649     buff = buff % winsize(card);
0650     maxlen = winsize(card) - buff;
0651 
0652     openwin(card, page);
0653     if (len > maxlen) {
0654         memcpy_toio(winbase(card) + buff, skb->data, maxlen);
0655         openwin(card, page + 1);
0656         memcpy_toio(winbase(card), skb->data + maxlen, len - maxlen);
0657     } else {
0658         memcpy_toio(winbase(card) + buff, skb->data, len);
0659     }
0660 
0661 #ifndef PAGE0_ALWAYS_MAPPED
0662     openwin(card, 0);   /* select pkt_desc table page back */
0663 #endif
0664     writew(len, &desc->len);
0665     writeb(ST_TX_EOM, &desc->stat);
0666 
0667     port->txin = next_desc(port, port->txin, 1);
0668     sca_outw(desc_offset(port, port->txin, 1),
0669          get_dmac_tx(port) + EDAL, card);
0670 
0671     sca_out(DSR_DE, DSR_TX(phy_node(port)), card); /* Enable TX DMA */
0672 
0673     desc = desc_address(port, port->txin + 1, 1);
0674     if (readb(&desc->stat)) /* allow 1 packet gap */
0675         netif_stop_queue(dev);
0676 
0677     spin_unlock_irq(&port->lock);
0678 
0679     dev_kfree_skb(skb);
0680     return NETDEV_TX_OK;
0681 }
0682 
0683 #ifdef NEED_DETECT_RAM
0684 static u32 sca_detect_ram(card_t *card, u8 __iomem *rambase, u32 ramsize)
0685 {
0686     /* Round RAM size to 32 bits, fill from end to start */
0687     u32 i = ramsize &= ~3;
0688     u32 size = winsize(card);
0689 
0690     openwin(card, (i - 4) / size); /* select last window */
0691 
0692     do {
0693         i -= 4;
0694         if ((i + 4) % size == 0)
0695             openwin(card, i / size);
0696         writel(i ^ 0x12345678, rambase + i % size);
0697     } while (i > 0);
0698 
0699     for (i = 0; i < ramsize ; i += 4) {
0700         if (i % size == 0)
0701             openwin(card, i / size);
0702 
0703         if (readl(rambase + i % size) != (i ^ 0x12345678))
0704             break;
0705     }
0706 
0707     return i;
0708 }
0709 #endif /* NEED_DETECT_RAM */
0710 
0711 static void sca_init(card_t *card, int wait_states)
0712 {
0713     sca_out(wait_states, WCRL, card); /* Wait Control */
0714     sca_out(wait_states, WCRM, card);
0715     sca_out(wait_states, WCRH, card);
0716 
0717     sca_out(0, DMER, card); /* DMA Master disable */
0718     sca_out(0x03, PCR, card); /* DMA priority */
0719     sca_out(0, DSR_RX(0), card); /* DMA disable - to halt state */
0720     sca_out(0, DSR_TX(0), card);
0721     sca_out(0, DSR_RX(1), card);
0722     sca_out(0, DSR_TX(1), card);
0723     sca_out(DMER_DME, DMER, card); /* DMA Master enable */
0724 }
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