net/wan/fsl_ucc_hdlc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* Freescale QUICC Engine HDLC Device Driver
0003  *
0004  * Copyright 2014 Freescale Semiconductor Inc.
0005  */
0006
0007 #ifndef _UCC_HDLC_H_
0008 #define _UCC_HDLC_H_
0009
0010 #include <linux/kernel.h>
0011 #include <linux/list.h>
0012
0013 #include <soc/fsl/qe/immap_qe.h>
0014 #include <soc/fsl/qe/qe.h>
0015
0016 #include <soc/fsl/qe/ucc.h>
0017 #include <soc/fsl/qe/ucc_fast.h>
0018
0019 /* UCC HDLC event register */
0020 #define UCCE_HDLC_RX_EVENTS \
0021 (UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)
0022 #define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)
0023
0024 struct ucc_hdlc_param {
0025     __be16 riptr;
0026     __be16 tiptr;
0027     __be16 res0;
0028     __be16 mrblr;
0029     __be32 rstate;
0030     __be32 rbase;
0031     __be16 rbdstat;
0032     __be16 rbdlen;
0033     __be32 rdptr;
0034     __be32 tstate;
0035     __be32 tbase;
0036     __be16 tbdstat;
0037     __be16 tbdlen;
0038     __be32 tdptr;
0039     __be32 rbptr;
0040     __be32 tbptr;
0041     __be32 rcrc;
0042     __be32 res1;
0043     __be32 tcrc;
0044     __be32 res2;
0045     __be32 res3;
0046     __be32 c_mask;
0047     __be32 c_pres;
0048     __be16 disfc;
0049     __be16 crcec;
0050     __be16 abtsc;
0051     __be16 nmarc;
0052     __be32 max_cnt;
0053     __be16 mflr;
0054     __be16 rfthr;
0055     __be16 rfcnt;
0056     __be16 hmask;
0057     __be16 haddr1;
0058     __be16 haddr2;
0059     __be16 haddr3;
0060     __be16 haddr4;
0061     __be16 ts_tmp;
0062     __be16 tmp_mb;
0063 };
0064
0065 struct ucc_hdlc_private {
0066     struct ucc_tdm  *utdm;
0067     struct ucc_tdm_info *ut_info;
0068     struct ucc_fast_private *uccf;
0069     struct device *dev;
0070     struct net_device *ndev;
0071     struct napi_struct napi;
0072     struct ucc_fast __iomem *uf_regs;   /* UCC Fast registers */
0073     struct ucc_hdlc_param __iomem *ucc_pram;
0074     u16 tsa;
0075     bool hdlc_busy;
0076     bool loopback;
0077     bool hdlc_bus;
0078
0079     u8 *tx_buffer;
0080     u8 *rx_buffer;
0081     dma_addr_t dma_tx_addr;
0082     dma_addr_t dma_rx_addr;
0083
0084     struct qe_bd *tx_bd_base;
0085     struct qe_bd *rx_bd_base;
0086     dma_addr_t dma_tx_bd;
0087     dma_addr_t dma_rx_bd;
0088     struct qe_bd *curtx_bd;
0089     struct qe_bd *currx_bd;
0090     struct qe_bd *dirty_tx;
0091     u16 currx_bdnum;
0092
0093     struct sk_buff **tx_skbuff;
0094     struct sk_buff **rx_skbuff;
0095     u16 skb_curtx;
0096     u16 skb_currx;
0097     unsigned short skb_dirtytx;
0098
0099     unsigned short tx_ring_size;
0100     unsigned short rx_ring_size;
0101     s32 ucc_pram_offset;
0102
0103     unsigned short encoding;
0104     unsigned short parity;
0105     unsigned short hmask;
0106     u32 clocking;
0107     spinlock_t lock;    /* lock for Tx BD and Tx buffer */
0108 #ifdef CONFIG_PM
0109     struct ucc_hdlc_param *ucc_pram_bak;
0110     u32 gumr;
0111     u8 guemr;
0112     u32 cmxsi1cr_l, cmxsi1cr_h;
0113     u32 cmxsi1syr;
0114     u32 cmxucr[4];
0115 #endif
0116 };
0117
0118 #define TX_BD_RING_LEN  0x10
0119 #define RX_BD_RING_LEN  0x20
0120 #define RX_CLEAN_MAX    0x10
0121 #define NUM_OF_BUF  4
0122 #define MAX_RX_BUF_LENGTH   (48 * 0x20)
0123 #define MAX_FRAME_LENGTH    (MAX_RX_BUF_LENGTH + 8)
0124 #define ALIGNMENT_OF_UCC_HDLC_PRAM  64
0125 #define SI_BANK_SIZE    128
0126 #define MAX_HDLC_NUM    4
0127 #define HDLC_HEAD_LEN   2
0128 #define HDLC_CRC_SIZE   2
0129 #define TX_RING_MOD_MASK(size) (size - 1)
0130 #define RX_RING_MOD_MASK(size) (size - 1)
0131
0132 #define HDLC_HEAD_MASK      0x0000
0133 #define DEFAULT_HDLC_HEAD   0xff44
0134 #define DEFAULT_ADDR_MASK   0x00ff
0135 #define DEFAULT_HDLC_ADDR   0x00ff
0136
0137 #define BMR_GBL         0x20000000
0138 #define BMR_BIG_ENDIAN      0x10000000
0139 #define CRC_16BIT_MASK      0x0000F0B8
0140 #define CRC_16BIT_PRES      0x0000FFFF
0141 #define DEFAULT_RFTHR       1
0142
0143 #define DEFAULT_PPP_HEAD    0xff03
0144
0145 #endif