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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Freescale QUICC Engine HDLC Device Driver
0003  *
0004  * Copyright 2016 Freescale Semiconductor Inc.
0005  */
0006 
0007 #include <linux/delay.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/hdlc.h>
0010 #include <linux/init.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/io.h>
0013 #include <linux/irq.h>
0014 #include <linux/kernel.h>
0015 #include <linux/module.h>
0016 #include <linux/netdevice.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_irq.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/platform_device.h>
0021 #include <linux/sched.h>
0022 #include <linux/skbuff.h>
0023 #include <linux/slab.h>
0024 #include <linux/spinlock.h>
0025 #include <linux/stddef.h>
0026 #include <soc/fsl/qe/qe_tdm.h>
0027 #include <uapi/linux/if_arp.h>
0028 
0029 #include "fsl_ucc_hdlc.h"
0030 
0031 #define DRV_DESC "Freescale QE UCC HDLC Driver"
0032 #define DRV_NAME "ucc_hdlc"
0033 
0034 #define TDM_PPPOHT_SLIC_MAXIN
0035 #define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S)
0036 
0037 static struct ucc_tdm_info utdm_primary_info = {
0038     .uf_info = {
0039         .tsa = 0,
0040         .cdp = 0,
0041         .cds = 1,
0042         .ctsp = 1,
0043         .ctss = 1,
0044         .revd = 0,
0045         .urfs = 256,
0046         .utfs = 256,
0047         .urfet = 128,
0048         .urfset = 192,
0049         .utfet = 128,
0050         .utftt = 0x40,
0051         .ufpt = 256,
0052         .mode = UCC_FAST_PROTOCOL_MODE_HDLC,
0053         .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL,
0054         .tenc = UCC_FAST_TX_ENCODING_NRZ,
0055         .renc = UCC_FAST_RX_ENCODING_NRZ,
0056         .tcrc = UCC_FAST_16_BIT_CRC,
0057         .synl = UCC_FAST_SYNC_LEN_NOT_USED,
0058     },
0059 
0060     .si_info = {
0061 #ifdef TDM_PPPOHT_SLIC_MAXIN
0062         .simr_rfsd = 1,
0063         .simr_tfsd = 2,
0064 #else
0065         .simr_rfsd = 0,
0066         .simr_tfsd = 0,
0067 #endif
0068         .simr_crt = 0,
0069         .simr_sl = 0,
0070         .simr_ce = 1,
0071         .simr_fe = 1,
0072         .simr_gm = 0,
0073     },
0074 };
0075 
0076 static struct ucc_tdm_info utdm_info[UCC_MAX_NUM];
0077 
0078 static int uhdlc_init(struct ucc_hdlc_private *priv)
0079 {
0080     struct ucc_tdm_info *ut_info;
0081     struct ucc_fast_info *uf_info;
0082     u32 cecr_subblock;
0083     u16 bd_status;
0084     int ret, i;
0085     void *bd_buffer;
0086     dma_addr_t bd_dma_addr;
0087     s32 riptr;
0088     s32 tiptr;
0089     u32 gumr;
0090 
0091     ut_info = priv->ut_info;
0092     uf_info = &ut_info->uf_info;
0093 
0094     if (priv->tsa) {
0095         uf_info->tsa = 1;
0096         uf_info->ctsp = 1;
0097         uf_info->cds = 1;
0098         uf_info->ctss = 1;
0099     } else {
0100         uf_info->cds = 0;
0101         uf_info->ctsp = 0;
0102         uf_info->ctss = 0;
0103     }
0104 
0105     /* This sets HPM register in CMXUCR register which configures a
0106      * open drain connected HDLC bus
0107      */
0108     if (priv->hdlc_bus)
0109         uf_info->brkpt_support = 1;
0110 
0111     uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
0112                 UCC_HDLC_UCCE_TXB) << 16);
0113 
0114     ret = ucc_fast_init(uf_info, &priv->uccf);
0115     if (ret) {
0116         dev_err(priv->dev, "Failed to init uccf.");
0117         return ret;
0118     }
0119 
0120     priv->uf_regs = priv->uccf->uf_regs;
0121     ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
0122 
0123     /* Loopback mode */
0124     if (priv->loopback) {
0125         dev_info(priv->dev, "Loopback Mode\n");
0126         /* use the same clock when work in loopback */
0127         qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
0128 
0129         gumr = ioread32be(&priv->uf_regs->gumr);
0130         gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
0131              UCC_FAST_GUMR_TCI);
0132         gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
0133         iowrite32be(gumr, &priv->uf_regs->gumr);
0134     }
0135 
0136     /* Initialize SI */
0137     if (priv->tsa)
0138         ucc_tdm_init(priv->utdm, priv->ut_info);
0139 
0140     /* Write to QE CECR, UCCx channel to Stop Transmission */
0141     cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
0142     ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
0143                QE_CR_PROTOCOL_UNSPECIFIED, 0);
0144 
0145     /* Set UPSMR normal mode (need fixed)*/
0146     iowrite32be(0, &priv->uf_regs->upsmr);
0147 
0148     /* hdlc_bus mode */
0149     if (priv->hdlc_bus) {
0150         u32 upsmr;
0151 
0152         dev_info(priv->dev, "HDLC bus Mode\n");
0153         upsmr = ioread32be(&priv->uf_regs->upsmr);
0154 
0155         /* bus mode and retransmit enable, with collision window
0156          * set to 8 bytes
0157          */
0158         upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
0159                 UCC_HDLC_UPSMR_CW8;
0160         iowrite32be(upsmr, &priv->uf_regs->upsmr);
0161 
0162         /* explicitly disable CDS & CTSP */
0163         gumr = ioread32be(&priv->uf_regs->gumr);
0164         gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
0165         /* set automatic sync to explicitly ignore CD signal */
0166         gumr |= UCC_FAST_GUMR_SYNL_AUTO;
0167         iowrite32be(gumr, &priv->uf_regs->gumr);
0168     }
0169 
0170     priv->rx_ring_size = RX_BD_RING_LEN;
0171     priv->tx_ring_size = TX_BD_RING_LEN;
0172     /* Alloc Rx BD */
0173     priv->rx_bd_base = dma_alloc_coherent(priv->dev,
0174             RX_BD_RING_LEN * sizeof(struct qe_bd),
0175             &priv->dma_rx_bd, GFP_KERNEL);
0176 
0177     if (!priv->rx_bd_base) {
0178         dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
0179         ret = -ENOMEM;
0180         goto free_uccf;
0181     }
0182 
0183     /* Alloc Tx BD */
0184     priv->tx_bd_base = dma_alloc_coherent(priv->dev,
0185             TX_BD_RING_LEN * sizeof(struct qe_bd),
0186             &priv->dma_tx_bd, GFP_KERNEL);
0187 
0188     if (!priv->tx_bd_base) {
0189         dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
0190         ret = -ENOMEM;
0191         goto free_rx_bd;
0192     }
0193 
0194     /* Alloc parameter ram for ucc hdlc */
0195     priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
0196                 ALIGNMENT_OF_UCC_HDLC_PRAM);
0197 
0198     if (priv->ucc_pram_offset < 0) {
0199         dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
0200         ret = -ENOMEM;
0201         goto free_tx_bd;
0202     }
0203 
0204     priv->rx_skbuff = kcalloc(priv->rx_ring_size,
0205                   sizeof(*priv->rx_skbuff),
0206                   GFP_KERNEL);
0207     if (!priv->rx_skbuff) {
0208         ret = -ENOMEM;
0209         goto free_ucc_pram;
0210     }
0211 
0212     priv->tx_skbuff = kcalloc(priv->tx_ring_size,
0213                   sizeof(*priv->tx_skbuff),
0214                   GFP_KERNEL);
0215     if (!priv->tx_skbuff) {
0216         ret = -ENOMEM;
0217         goto free_rx_skbuff;
0218     }
0219 
0220     priv->skb_curtx = 0;
0221     priv->skb_dirtytx = 0;
0222     priv->curtx_bd = priv->tx_bd_base;
0223     priv->dirty_tx = priv->tx_bd_base;
0224     priv->currx_bd = priv->rx_bd_base;
0225     priv->currx_bdnum = 0;
0226 
0227     /* init parameter base */
0228     cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
0229     ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
0230                QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
0231 
0232     priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
0233                     qe_muram_addr(priv->ucc_pram_offset);
0234 
0235     /* Zero out parameter ram */
0236     memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
0237 
0238     /* Alloc riptr, tiptr */
0239     riptr = qe_muram_alloc(32, 32);
0240     if (riptr < 0) {
0241         dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
0242         ret = -ENOMEM;
0243         goto free_tx_skbuff;
0244     }
0245 
0246     tiptr = qe_muram_alloc(32, 32);
0247     if (tiptr < 0) {
0248         dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
0249         ret = -ENOMEM;
0250         goto free_riptr;
0251     }
0252     if (riptr != (u16)riptr || tiptr != (u16)tiptr) {
0253         dev_err(priv->dev, "MURAM allocation out of addressable range\n");
0254         ret = -ENOMEM;
0255         goto free_tiptr;
0256     }
0257 
0258     /* Set RIPTR, TIPTR */
0259     iowrite16be(riptr, &priv->ucc_pram->riptr);
0260     iowrite16be(tiptr, &priv->ucc_pram->tiptr);
0261 
0262     /* Set MRBLR */
0263     iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
0264 
0265     /* Set RBASE, TBASE */
0266     iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
0267     iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
0268 
0269     /* Set RSTATE, TSTATE */
0270     iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
0271     iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
0272 
0273     /* Set C_MASK, C_PRES for 16bit CRC */
0274     iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
0275     iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
0276 
0277     iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
0278     iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
0279     iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
0280     iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
0281     iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
0282     iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
0283     iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
0284     iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
0285 
0286     /* Get BD buffer */
0287     bd_buffer = dma_alloc_coherent(priv->dev,
0288                        (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
0289                        &bd_dma_addr, GFP_KERNEL);
0290 
0291     if (!bd_buffer) {
0292         dev_err(priv->dev, "Could not allocate buffer descriptors\n");
0293         ret = -ENOMEM;
0294         goto free_tiptr;
0295     }
0296 
0297     priv->rx_buffer = bd_buffer;
0298     priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
0299 
0300     priv->dma_rx_addr = bd_dma_addr;
0301     priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
0302 
0303     for (i = 0; i < RX_BD_RING_LEN; i++) {
0304         if (i < (RX_BD_RING_LEN - 1))
0305             bd_status = R_E_S | R_I_S;
0306         else
0307             bd_status = R_E_S | R_I_S | R_W_S;
0308 
0309         priv->rx_bd_base[i].status = cpu_to_be16(bd_status);
0310         priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH);
0311     }
0312 
0313     for (i = 0; i < TX_BD_RING_LEN; i++) {
0314         if (i < (TX_BD_RING_LEN - 1))
0315             bd_status =  T_I_S | T_TC_S;
0316         else
0317             bd_status =  T_I_S | T_TC_S | T_W_S;
0318 
0319         priv->tx_bd_base[i].status = cpu_to_be16(bd_status);
0320         priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH);
0321     }
0322     dma_wmb();
0323 
0324     return 0;
0325 
0326 free_tiptr:
0327     qe_muram_free(tiptr);
0328 free_riptr:
0329     qe_muram_free(riptr);
0330 free_tx_skbuff:
0331     kfree(priv->tx_skbuff);
0332 free_rx_skbuff:
0333     kfree(priv->rx_skbuff);
0334 free_ucc_pram:
0335     qe_muram_free(priv->ucc_pram_offset);
0336 free_tx_bd:
0337     dma_free_coherent(priv->dev,
0338               TX_BD_RING_LEN * sizeof(struct qe_bd),
0339               priv->tx_bd_base, priv->dma_tx_bd);
0340 free_rx_bd:
0341     dma_free_coherent(priv->dev,
0342               RX_BD_RING_LEN * sizeof(struct qe_bd),
0343               priv->rx_bd_base, priv->dma_rx_bd);
0344 free_uccf:
0345     ucc_fast_free(priv->uccf);
0346 
0347     return ret;
0348 }
0349 
0350 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
0351 {
0352     hdlc_device *hdlc = dev_to_hdlc(dev);
0353     struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
0354     struct qe_bd *bd;
0355     u16 bd_status;
0356     unsigned long flags;
0357     __be16 *proto_head;
0358 
0359     switch (dev->type) {
0360     case ARPHRD_RAWHDLC:
0361         if (skb_headroom(skb) < HDLC_HEAD_LEN) {
0362             dev->stats.tx_dropped++;
0363             dev_kfree_skb(skb);
0364             netdev_err(dev, "No enough space for hdlc head\n");
0365             return -ENOMEM;
0366         }
0367 
0368         skb_push(skb, HDLC_HEAD_LEN);
0369 
0370         proto_head = (__be16 *)skb->data;
0371         *proto_head = htons(DEFAULT_HDLC_HEAD);
0372 
0373         dev->stats.tx_bytes += skb->len;
0374         break;
0375 
0376     case ARPHRD_PPP:
0377         proto_head = (__be16 *)skb->data;
0378         if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
0379             dev->stats.tx_dropped++;
0380             dev_kfree_skb(skb);
0381             netdev_err(dev, "Wrong ppp header\n");
0382             return -ENOMEM;
0383         }
0384 
0385         dev->stats.tx_bytes += skb->len;
0386         break;
0387 
0388     case ARPHRD_ETHER:
0389         dev->stats.tx_bytes += skb->len;
0390         break;
0391 
0392     default:
0393         dev->stats.tx_dropped++;
0394         dev_kfree_skb(skb);
0395         return -ENOMEM;
0396     }
0397     netdev_sent_queue(dev, skb->len);
0398     spin_lock_irqsave(&priv->lock, flags);
0399 
0400     dma_rmb();
0401     /* Start from the next BD that should be filled */
0402     bd = priv->curtx_bd;
0403     bd_status = be16_to_cpu(bd->status);
0404     /* Save the skb pointer so we can free it later */
0405     priv->tx_skbuff[priv->skb_curtx] = skb;
0406 
0407     /* Update the current skb pointer (wrapping if this was the last) */
0408     priv->skb_curtx =
0409         (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
0410 
0411     /* copy skb data to tx buffer for sdma processing */
0412     memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
0413            skb->data, skb->len);
0414 
0415     /* set bd status and length */
0416     bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
0417 
0418     bd->length = cpu_to_be16(skb->len);
0419     bd->status = cpu_to_be16(bd_status);
0420 
0421     /* Move to next BD in the ring */
0422     if (!(bd_status & T_W_S))
0423         bd += 1;
0424     else
0425         bd = priv->tx_bd_base;
0426 
0427     if (bd == priv->dirty_tx) {
0428         if (!netif_queue_stopped(dev))
0429             netif_stop_queue(dev);
0430     }
0431 
0432     priv->curtx_bd = bd;
0433 
0434     spin_unlock_irqrestore(&priv->lock, flags);
0435 
0436     return NETDEV_TX_OK;
0437 }
0438 
0439 static int hdlc_tx_restart(struct ucc_hdlc_private *priv)
0440 {
0441     u32 cecr_subblock;
0442 
0443     cecr_subblock =
0444         ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num);
0445 
0446     qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
0447              QE_CR_PROTOCOL_UNSPECIFIED, 0);
0448     return 0;
0449 }
0450 
0451 static int hdlc_tx_done(struct ucc_hdlc_private *priv)
0452 {
0453     /* Start from the next BD that should be filled */
0454     struct net_device *dev = priv->ndev;
0455     unsigned int bytes_sent = 0;
0456     int howmany = 0;
0457     struct qe_bd *bd;       /* BD pointer */
0458     u16 bd_status;
0459     int tx_restart = 0;
0460 
0461     dma_rmb();
0462     bd = priv->dirty_tx;
0463     bd_status = be16_to_cpu(bd->status);
0464 
0465     /* Normal processing. */
0466     while ((bd_status & T_R_S) == 0) {
0467         struct sk_buff *skb;
0468 
0469         if (bd_status & T_UN_S) { /* Underrun */
0470             dev->stats.tx_fifo_errors++;
0471             tx_restart = 1;
0472         }
0473         if (bd_status & T_CT_S) { /* Carrier lost */
0474             dev->stats.tx_carrier_errors++;
0475             tx_restart = 1;
0476         }
0477 
0478         /* BD contains already transmitted buffer.   */
0479         /* Handle the transmitted buffer and release */
0480         /* the BD to be used with the current frame  */
0481 
0482         skb = priv->tx_skbuff[priv->skb_dirtytx];
0483         if (!skb)
0484             break;
0485         howmany++;
0486         bytes_sent += skb->len;
0487         dev->stats.tx_packets++;
0488         memset(priv->tx_buffer +
0489                (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
0490                0, skb->len);
0491         dev_consume_skb_irq(skb);
0492 
0493         priv->tx_skbuff[priv->skb_dirtytx] = NULL;
0494         priv->skb_dirtytx =
0495             (priv->skb_dirtytx +
0496              1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
0497 
0498         /* We freed a buffer, so now we can restart transmission */
0499         if (netif_queue_stopped(dev))
0500             netif_wake_queue(dev);
0501 
0502         /* Advance the confirmation BD pointer */
0503         if (!(bd_status & T_W_S))
0504             bd += 1;
0505         else
0506             bd = priv->tx_bd_base;
0507         bd_status = be16_to_cpu(bd->status);
0508     }
0509     priv->dirty_tx = bd;
0510 
0511     if (tx_restart)
0512         hdlc_tx_restart(priv);
0513 
0514     netdev_completed_queue(dev, howmany, bytes_sent);
0515     return 0;
0516 }
0517 
0518 static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
0519 {
0520     struct net_device *dev = priv->ndev;
0521     struct sk_buff *skb = NULL;
0522     hdlc_device *hdlc = dev_to_hdlc(dev);
0523     struct qe_bd *bd;
0524     u16 bd_status;
0525     u16 length, howmany = 0;
0526     u8 *bdbuffer;
0527 
0528     dma_rmb();
0529     bd = priv->currx_bd;
0530     bd_status = be16_to_cpu(bd->status);
0531 
0532     /* while there are received buffers and BD is full (~R_E) */
0533     while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) {
0534         if (bd_status & (RX_BD_ERRORS)) {
0535             dev->stats.rx_errors++;
0536 
0537             if (bd_status & R_CD_S)
0538                 dev->stats.collisions++;
0539             if (bd_status & R_OV_S)
0540                 dev->stats.rx_fifo_errors++;
0541             if (bd_status & R_CR_S)
0542                 dev->stats.rx_crc_errors++;
0543             if (bd_status & R_AB_S)
0544                 dev->stats.rx_over_errors++;
0545             if (bd_status & R_NO_S)
0546                 dev->stats.rx_frame_errors++;
0547             if (bd_status & R_LG_S)
0548                 dev->stats.rx_length_errors++;
0549 
0550             goto recycle;
0551         }
0552         bdbuffer = priv->rx_buffer +
0553             (priv->currx_bdnum * MAX_RX_BUF_LENGTH);
0554         length = be16_to_cpu(bd->length);
0555 
0556         switch (dev->type) {
0557         case ARPHRD_RAWHDLC:
0558             bdbuffer += HDLC_HEAD_LEN;
0559             length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE);
0560 
0561             skb = dev_alloc_skb(length);
0562             if (!skb) {
0563                 dev->stats.rx_dropped++;
0564                 return -ENOMEM;
0565             }
0566 
0567             skb_put(skb, length);
0568             skb->len = length;
0569             skb->dev = dev;
0570             memcpy(skb->data, bdbuffer, length);
0571             break;
0572 
0573         case ARPHRD_PPP:
0574         case ARPHRD_ETHER:
0575             length -= HDLC_CRC_SIZE;
0576 
0577             skb = dev_alloc_skb(length);
0578             if (!skb) {
0579                 dev->stats.rx_dropped++;
0580                 return -ENOMEM;
0581             }
0582 
0583             skb_put(skb, length);
0584             skb->len = length;
0585             skb->dev = dev;
0586             memcpy(skb->data, bdbuffer, length);
0587             break;
0588         }
0589 
0590         dev->stats.rx_packets++;
0591         dev->stats.rx_bytes += skb->len;
0592         howmany++;
0593         if (hdlc->proto)
0594             skb->protocol = hdlc_type_trans(skb, dev);
0595         netif_receive_skb(skb);
0596 
0597 recycle:
0598         bd->status = cpu_to_be16((bd_status & R_W_S) | R_E_S | R_I_S);
0599 
0600         /* update to point at the next bd */
0601         if (bd_status & R_W_S) {
0602             priv->currx_bdnum = 0;
0603             bd = priv->rx_bd_base;
0604         } else {
0605             if (priv->currx_bdnum < (RX_BD_RING_LEN - 1))
0606                 priv->currx_bdnum += 1;
0607             else
0608                 priv->currx_bdnum = RX_BD_RING_LEN - 1;
0609 
0610             bd += 1;
0611         }
0612 
0613         bd_status = be16_to_cpu(bd->status);
0614     }
0615     dma_rmb();
0616 
0617     priv->currx_bd = bd;
0618     return howmany;
0619 }
0620 
0621 static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
0622 {
0623     struct ucc_hdlc_private *priv = container_of(napi,
0624                              struct ucc_hdlc_private,
0625                              napi);
0626     int howmany;
0627 
0628     /* Tx event processing */
0629     spin_lock(&priv->lock);
0630     hdlc_tx_done(priv);
0631     spin_unlock(&priv->lock);
0632 
0633     howmany = 0;
0634     howmany += hdlc_rx_done(priv, budget - howmany);
0635 
0636     if (howmany < budget) {
0637         napi_complete_done(napi, howmany);
0638         qe_setbits_be32(priv->uccf->p_uccm,
0639                 (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
0640     }
0641 
0642     return howmany;
0643 }
0644 
0645 static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
0646 {
0647     struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id;
0648     struct net_device *dev = priv->ndev;
0649     struct ucc_fast_private *uccf;
0650     u32 ucce;
0651     u32 uccm;
0652 
0653     uccf = priv->uccf;
0654 
0655     ucce = ioread32be(uccf->p_ucce);
0656     uccm = ioread32be(uccf->p_uccm);
0657     ucce &= uccm;
0658     iowrite32be(ucce, uccf->p_ucce);
0659     if (!ucce)
0660         return IRQ_NONE;
0661 
0662     if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) {
0663         if (napi_schedule_prep(&priv->napi)) {
0664             uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)
0665                   << 16);
0666             iowrite32be(uccm, uccf->p_uccm);
0667             __napi_schedule(&priv->napi);
0668         }
0669     }
0670 
0671     /* Errors and other events */
0672     if (ucce >> 16 & UCC_HDLC_UCCE_BSY)
0673         dev->stats.rx_missed_errors++;
0674     if (ucce >> 16 & UCC_HDLC_UCCE_TXE)
0675         dev->stats.tx_errors++;
0676 
0677     return IRQ_HANDLED;
0678 }
0679 
0680 static int uhdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
0681 {
0682     const size_t size = sizeof(te1_settings);
0683     te1_settings line;
0684     struct ucc_hdlc_private *priv = netdev_priv(dev);
0685 
0686     switch (ifs->type) {
0687     case IF_GET_IFACE:
0688         ifs->type = IF_IFACE_E1;
0689         if (ifs->size < size) {
0690             ifs->size = size; /* data size wanted */
0691             return -ENOBUFS;
0692         }
0693         memset(&line, 0, sizeof(line));
0694         line.clock_type = priv->clocking;
0695 
0696         if (copy_to_user(ifs->ifs_ifsu.sync, &line, size))
0697             return -EFAULT;
0698         return 0;
0699 
0700     default:
0701         return hdlc_ioctl(dev, ifs);
0702     }
0703 }
0704 
0705 static int uhdlc_open(struct net_device *dev)
0706 {
0707     u32 cecr_subblock;
0708     hdlc_device *hdlc = dev_to_hdlc(dev);
0709     struct ucc_hdlc_private *priv = hdlc->priv;
0710     struct ucc_tdm *utdm = priv->utdm;
0711 
0712     if (priv->hdlc_busy != 1) {
0713         if (request_irq(priv->ut_info->uf_info.irq,
0714                 ucc_hdlc_irq_handler, 0, "hdlc", priv))
0715             return -ENODEV;
0716 
0717         cecr_subblock = ucc_fast_get_qe_cr_subblock(
0718                     priv->ut_info->uf_info.ucc_num);
0719 
0720         qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
0721                  QE_CR_PROTOCOL_UNSPECIFIED, 0);
0722 
0723         ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
0724 
0725         /* Enable the TDM port */
0726         if (priv->tsa)
0727             qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
0728 
0729         priv->hdlc_busy = 1;
0730         netif_device_attach(priv->ndev);
0731         napi_enable(&priv->napi);
0732         netdev_reset_queue(dev);
0733         netif_start_queue(dev);
0734         hdlc_open(dev);
0735     }
0736 
0737     return 0;
0738 }
0739 
0740 static void uhdlc_memclean(struct ucc_hdlc_private *priv)
0741 {
0742     qe_muram_free(ioread16be(&priv->ucc_pram->riptr));
0743     qe_muram_free(ioread16be(&priv->ucc_pram->tiptr));
0744 
0745     if (priv->rx_bd_base) {
0746         dma_free_coherent(priv->dev,
0747                   RX_BD_RING_LEN * sizeof(struct qe_bd),
0748                   priv->rx_bd_base, priv->dma_rx_bd);
0749 
0750         priv->rx_bd_base = NULL;
0751         priv->dma_rx_bd = 0;
0752     }
0753 
0754     if (priv->tx_bd_base) {
0755         dma_free_coherent(priv->dev,
0756                   TX_BD_RING_LEN * sizeof(struct qe_bd),
0757                   priv->tx_bd_base, priv->dma_tx_bd);
0758 
0759         priv->tx_bd_base = NULL;
0760         priv->dma_tx_bd = 0;
0761     }
0762 
0763     if (priv->ucc_pram) {
0764         qe_muram_free(priv->ucc_pram_offset);
0765         priv->ucc_pram = NULL;
0766         priv->ucc_pram_offset = 0;
0767      }
0768 
0769     kfree(priv->rx_skbuff);
0770     priv->rx_skbuff = NULL;
0771 
0772     kfree(priv->tx_skbuff);
0773     priv->tx_skbuff = NULL;
0774 
0775     if (priv->uf_regs) {
0776         iounmap(priv->uf_regs);
0777         priv->uf_regs = NULL;
0778     }
0779 
0780     if (priv->uccf) {
0781         ucc_fast_free(priv->uccf);
0782         priv->uccf = NULL;
0783     }
0784 
0785     if (priv->rx_buffer) {
0786         dma_free_coherent(priv->dev,
0787                   RX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
0788                   priv->rx_buffer, priv->dma_rx_addr);
0789         priv->rx_buffer = NULL;
0790         priv->dma_rx_addr = 0;
0791     }
0792 
0793     if (priv->tx_buffer) {
0794         dma_free_coherent(priv->dev,
0795                   TX_BD_RING_LEN * MAX_RX_BUF_LENGTH,
0796                   priv->tx_buffer, priv->dma_tx_addr);
0797         priv->tx_buffer = NULL;
0798         priv->dma_tx_addr = 0;
0799     }
0800 }
0801 
0802 static int uhdlc_close(struct net_device *dev)
0803 {
0804     struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
0805     struct ucc_tdm *utdm = priv->utdm;
0806     u32 cecr_subblock;
0807 
0808     napi_disable(&priv->napi);
0809     cecr_subblock = ucc_fast_get_qe_cr_subblock(
0810                 priv->ut_info->uf_info.ucc_num);
0811 
0812     qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
0813              (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
0814     qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock,
0815              (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
0816 
0817     if (priv->tsa)
0818         qe_clrbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
0819 
0820     ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
0821 
0822     free_irq(priv->ut_info->uf_info.irq, priv);
0823     netif_stop_queue(dev);
0824     netdev_reset_queue(dev);
0825     priv->hdlc_busy = 0;
0826 
0827     return 0;
0828 }
0829 
0830 static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding,
0831                unsigned short parity)
0832 {
0833     struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv;
0834 
0835     if (encoding != ENCODING_NRZ &&
0836         encoding != ENCODING_NRZI)
0837         return -EINVAL;
0838 
0839     if (parity != PARITY_NONE &&
0840         parity != PARITY_CRC32_PR1_CCITT &&
0841         parity != PARITY_CRC16_PR0_CCITT &&
0842         parity != PARITY_CRC16_PR1_CCITT)
0843         return -EINVAL;
0844 
0845     priv->encoding = encoding;
0846     priv->parity = parity;
0847 
0848     return 0;
0849 }
0850 
0851 #ifdef CONFIG_PM
0852 static void store_clk_config(struct ucc_hdlc_private *priv)
0853 {
0854     struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx;
0855 
0856     /* store si clk */
0857     priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h);
0858     priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l);
0859 
0860     /* store si sync */
0861     priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr);
0862 
0863     /* store ucc clk */
0864     memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32));
0865 }
0866 
0867 static void resume_clk_config(struct ucc_hdlc_private *priv)
0868 {
0869     struct qe_mux __iomem *qe_mux_reg = &qe_immr->qmx;
0870 
0871     memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32));
0872 
0873     iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);
0874     iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);
0875 
0876     iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);
0877 }
0878 
0879 static int uhdlc_suspend(struct device *dev)
0880 {
0881     struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
0882     struct ucc_fast __iomem *uf_regs;
0883 
0884     if (!priv)
0885         return -EINVAL;
0886 
0887     if (!netif_running(priv->ndev))
0888         return 0;
0889 
0890     netif_device_detach(priv->ndev);
0891     napi_disable(&priv->napi);
0892 
0893     uf_regs = priv->uf_regs;
0894 
0895     /* backup gumr guemr*/
0896     priv->gumr = ioread32be(&uf_regs->gumr);
0897     priv->guemr = ioread8(&uf_regs->guemr);
0898 
0899     priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak),
0900                     GFP_KERNEL);
0901     if (!priv->ucc_pram_bak)
0902         return -ENOMEM;
0903 
0904     /* backup HDLC parameter */
0905     memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram,
0906               sizeof(struct ucc_hdlc_param));
0907 
0908     /* store the clk configuration */
0909     store_clk_config(priv);
0910 
0911     /* save power */
0912     ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
0913 
0914     return 0;
0915 }
0916 
0917 static int uhdlc_resume(struct device *dev)
0918 {
0919     struct ucc_hdlc_private *priv = dev_get_drvdata(dev);
0920     struct ucc_tdm *utdm;
0921     struct ucc_tdm_info *ut_info;
0922     struct ucc_fast __iomem *uf_regs;
0923     struct ucc_fast_private *uccf;
0924     struct ucc_fast_info *uf_info;
0925     int i;
0926     u32 cecr_subblock;
0927     u16 bd_status;
0928 
0929     if (!priv)
0930         return -EINVAL;
0931 
0932     if (!netif_running(priv->ndev))
0933         return 0;
0934 
0935     utdm = priv->utdm;
0936     ut_info = priv->ut_info;
0937     uf_info = &ut_info->uf_info;
0938     uf_regs = priv->uf_regs;
0939     uccf = priv->uccf;
0940 
0941     /* restore gumr guemr */
0942     iowrite8(priv->guemr, &uf_regs->guemr);
0943     iowrite32be(priv->gumr, &uf_regs->gumr);
0944 
0945     /* Set Virtual Fifo registers */
0946     iowrite16be(uf_info->urfs, &uf_regs->urfs);
0947     iowrite16be(uf_info->urfet, &uf_regs->urfet);
0948     iowrite16be(uf_info->urfset, &uf_regs->urfset);
0949     iowrite16be(uf_info->utfs, &uf_regs->utfs);
0950     iowrite16be(uf_info->utfet, &uf_regs->utfet);
0951     iowrite16be(uf_info->utftt, &uf_regs->utftt);
0952     /* utfb, urfb are offsets from MURAM base */
0953     iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);
0954     iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);
0955 
0956     /* Rx Tx and sync clock routing */
0957     resume_clk_config(priv);
0958 
0959     iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
0960     iowrite32be(0xffffffff, &uf_regs->ucce);
0961 
0962     ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
0963 
0964     /* rebuild SIRAM */
0965     if (priv->tsa)
0966         ucc_tdm_init(priv->utdm, priv->ut_info);
0967 
0968     /* Write to QE CECR, UCCx channel to Stop Transmission */
0969     cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
0970     qe_issue_cmd(QE_STOP_TX, cecr_subblock,
0971              (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
0972 
0973     /* Set UPSMR normal mode */
0974     iowrite32be(0, &uf_regs->upsmr);
0975 
0976     /* init parameter base */
0977     cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
0978     qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
0979              QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
0980 
0981     priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
0982                 qe_muram_addr(priv->ucc_pram_offset);
0983 
0984     /* restore ucc parameter */
0985     memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak,
0986             sizeof(struct ucc_hdlc_param));
0987     kfree(priv->ucc_pram_bak);
0988 
0989     /* rebuild BD entry */
0990     for (i = 0; i < RX_BD_RING_LEN; i++) {
0991         if (i < (RX_BD_RING_LEN - 1))
0992             bd_status = R_E_S | R_I_S;
0993         else
0994             bd_status = R_E_S | R_I_S | R_W_S;
0995 
0996         priv->rx_bd_base[i].status = cpu_to_be16(bd_status);
0997         priv->rx_bd_base[i].buf = cpu_to_be32(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH);
0998     }
0999 
1000     for (i = 0; i < TX_BD_RING_LEN; i++) {
1001         if (i < (TX_BD_RING_LEN - 1))
1002             bd_status =  T_I_S | T_TC_S;
1003         else
1004             bd_status =  T_I_S | T_TC_S | T_W_S;
1005 
1006         priv->tx_bd_base[i].status = cpu_to_be16(bd_status);
1007         priv->tx_bd_base[i].buf = cpu_to_be32(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH);
1008     }
1009     dma_wmb();
1010 
1011     /* if hdlc is busy enable TX and RX */
1012     if (priv->hdlc_busy == 1) {
1013         cecr_subblock = ucc_fast_get_qe_cr_subblock(
1014                     priv->ut_info->uf_info.ucc_num);
1015 
1016         qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock,
1017                  (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0);
1018 
1019         ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
1020 
1021         /* Enable the TDM port */
1022         if (priv->tsa)
1023             qe_setbits_8(&utdm->si_regs->siglmr1_h, 0x1 << utdm->tdm_port);
1024     }
1025 
1026     napi_enable(&priv->napi);
1027     netif_device_attach(priv->ndev);
1028 
1029     return 0;
1030 }
1031 
1032 static const struct dev_pm_ops uhdlc_pm_ops = {
1033     .suspend = uhdlc_suspend,
1034     .resume = uhdlc_resume,
1035     .freeze = uhdlc_suspend,
1036     .thaw = uhdlc_resume,
1037 };
1038 
1039 #define HDLC_PM_OPS (&uhdlc_pm_ops)
1040 
1041 #else
1042 
1043 #define HDLC_PM_OPS NULL
1044 
1045 #endif
1046 static void uhdlc_tx_timeout(struct net_device *ndev, unsigned int txqueue)
1047 {
1048     netdev_err(ndev, "%s\n", __func__);
1049 }
1050 
1051 static const struct net_device_ops uhdlc_ops = {
1052     .ndo_open       = uhdlc_open,
1053     .ndo_stop       = uhdlc_close,
1054     .ndo_start_xmit = hdlc_start_xmit,
1055     .ndo_siocwandev = uhdlc_ioctl,
1056     .ndo_tx_timeout = uhdlc_tx_timeout,
1057 };
1058 
1059 static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr)
1060 {
1061     struct device_node *np;
1062     struct platform_device *pdev;
1063     struct resource *res;
1064     static int siram_init_flag;
1065     int ret = 0;
1066 
1067     np = of_find_compatible_node(NULL, NULL, name);
1068     if (!np)
1069         return -EINVAL;
1070 
1071     pdev = of_find_device_by_node(np);
1072     if (!pdev) {
1073         pr_err("%pOFn: failed to lookup pdev\n", np);
1074         of_node_put(np);
1075         return -EINVAL;
1076     }
1077 
1078     of_node_put(np);
1079     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1080     if (!res) {
1081         ret = -EINVAL;
1082         goto error_put_device;
1083     }
1084     *ptr = ioremap(res->start, resource_size(res));
1085     if (!*ptr) {
1086         ret = -ENOMEM;
1087         goto error_put_device;
1088     }
1089 
1090     /* We've remapped the addresses, and we don't need the device any
1091      * more, so we should release it.
1092      */
1093     put_device(&pdev->dev);
1094 
1095     if (init_flag && siram_init_flag == 0) {
1096         memset_io(*ptr, 0, resource_size(res));
1097         siram_init_flag = 1;
1098     }
1099     return  0;
1100 
1101 error_put_device:
1102     put_device(&pdev->dev);
1103 
1104     return ret;
1105 }
1106 
1107 static int ucc_hdlc_probe(struct platform_device *pdev)
1108 {
1109     struct device_node *np = pdev->dev.of_node;
1110     struct ucc_hdlc_private *uhdlc_priv = NULL;
1111     struct ucc_tdm_info *ut_info;
1112     struct ucc_tdm *utdm = NULL;
1113     struct resource res;
1114     struct net_device *dev;
1115     hdlc_device *hdlc;
1116     int ucc_num;
1117     const char *sprop;
1118     int ret;
1119     u32 val;
1120 
1121     ret = of_property_read_u32_index(np, "cell-index", 0, &val);
1122     if (ret) {
1123         dev_err(&pdev->dev, "Invalid ucc property\n");
1124         return -ENODEV;
1125     }
1126 
1127     ucc_num = val - 1;
1128     if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) {
1129         dev_err(&pdev->dev, ": Invalid UCC num\n");
1130         return -EINVAL;
1131     }
1132 
1133     memcpy(&utdm_info[ucc_num], &utdm_primary_info,
1134            sizeof(utdm_primary_info));
1135 
1136     ut_info = &utdm_info[ucc_num];
1137     ut_info->uf_info.ucc_num = ucc_num;
1138 
1139     sprop = of_get_property(np, "rx-clock-name", NULL);
1140     if (sprop) {
1141         ut_info->uf_info.rx_clock = qe_clock_source(sprop);
1142         if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) ||
1143             (ut_info->uf_info.rx_clock > QE_CLK24)) {
1144             dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1145             return -EINVAL;
1146         }
1147     } else {
1148         dev_err(&pdev->dev, "Invalid rx-clock-name property\n");
1149         return -EINVAL;
1150     }
1151 
1152     sprop = of_get_property(np, "tx-clock-name", NULL);
1153     if (sprop) {
1154         ut_info->uf_info.tx_clock = qe_clock_source(sprop);
1155         if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) ||
1156             (ut_info->uf_info.tx_clock > QE_CLK24)) {
1157             dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1158             return -EINVAL;
1159         }
1160     } else {
1161         dev_err(&pdev->dev, "Invalid tx-clock-name property\n");
1162         return -EINVAL;
1163     }
1164 
1165     ret = of_address_to_resource(np, 0, &res);
1166     if (ret)
1167         return -EINVAL;
1168 
1169     ut_info->uf_info.regs = res.start;
1170     ut_info->uf_info.irq = irq_of_parse_and_map(np, 0);
1171 
1172     uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL);
1173     if (!uhdlc_priv)
1174         return -ENOMEM;
1175 
1176     dev_set_drvdata(&pdev->dev, uhdlc_priv);
1177     uhdlc_priv->dev = &pdev->dev;
1178     uhdlc_priv->ut_info = ut_info;
1179 
1180     if (of_get_property(np, "fsl,tdm-interface", NULL))
1181         uhdlc_priv->tsa = 1;
1182 
1183     if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
1184         uhdlc_priv->loopback = 1;
1185 
1186     if (of_get_property(np, "fsl,hdlc-bus", NULL))
1187         uhdlc_priv->hdlc_bus = 1;
1188 
1189     if (uhdlc_priv->tsa == 1) {
1190         utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
1191         if (!utdm) {
1192             ret = -ENOMEM;
1193             dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n");
1194             goto free_uhdlc_priv;
1195         }
1196         uhdlc_priv->utdm = utdm;
1197         ret = ucc_of_parse_tdm(np, utdm, ut_info);
1198         if (ret)
1199             goto free_utdm;
1200 
1201         ret = hdlc_map_iomem("fsl,t1040-qe-si", 0,
1202                      (void __iomem **)&utdm->si_regs);
1203         if (ret)
1204             goto free_utdm;
1205         ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1,
1206                      (void __iomem **)&utdm->siram);
1207         if (ret)
1208             goto unmap_si_regs;
1209     }
1210 
1211     if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask))
1212         uhdlc_priv->hmask = DEFAULT_ADDR_MASK;
1213 
1214     ret = uhdlc_init(uhdlc_priv);
1215     if (ret) {
1216         dev_err(&pdev->dev, "Failed to init uhdlc\n");
1217         goto undo_uhdlc_init;
1218     }
1219 
1220     dev = alloc_hdlcdev(uhdlc_priv);
1221     if (!dev) {
1222         ret = -ENOMEM;
1223         pr_err("ucc_hdlc: unable to allocate memory\n");
1224         goto undo_uhdlc_init;
1225     }
1226 
1227     uhdlc_priv->ndev = dev;
1228     hdlc = dev_to_hdlc(dev);
1229     dev->tx_queue_len = 16;
1230     dev->netdev_ops = &uhdlc_ops;
1231     dev->watchdog_timeo = 2 * HZ;
1232     hdlc->attach = ucc_hdlc_attach;
1233     hdlc->xmit = ucc_hdlc_tx;
1234     netif_napi_add_weight(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32);
1235     if (register_hdlc_device(dev)) {
1236         ret = -ENOBUFS;
1237         pr_err("ucc_hdlc: unable to register hdlc device\n");
1238         goto free_dev;
1239     }
1240 
1241     return 0;
1242 
1243 free_dev:
1244     free_netdev(dev);
1245 undo_uhdlc_init:
1246     iounmap(utdm->siram);
1247 unmap_si_regs:
1248     iounmap(utdm->si_regs);
1249 free_utdm:
1250     if (uhdlc_priv->tsa)
1251         kfree(utdm);
1252 free_uhdlc_priv:
1253     kfree(uhdlc_priv);
1254     return ret;
1255 }
1256 
1257 static int ucc_hdlc_remove(struct platform_device *pdev)
1258 {
1259     struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev);
1260 
1261     uhdlc_memclean(priv);
1262 
1263     if (priv->utdm->si_regs) {
1264         iounmap(priv->utdm->si_regs);
1265         priv->utdm->si_regs = NULL;
1266     }
1267 
1268     if (priv->utdm->siram) {
1269         iounmap(priv->utdm->siram);
1270         priv->utdm->siram = NULL;
1271     }
1272     kfree(priv);
1273 
1274     dev_info(&pdev->dev, "UCC based hdlc module removed\n");
1275 
1276     return 0;
1277 }
1278 
1279 static const struct of_device_id fsl_ucc_hdlc_of_match[] = {
1280     {
1281     .compatible = "fsl,ucc-hdlc",
1282     },
1283     {},
1284 };
1285 
1286 MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match);
1287 
1288 static struct platform_driver ucc_hdlc_driver = {
1289     .probe  = ucc_hdlc_probe,
1290     .remove = ucc_hdlc_remove,
1291     .driver = {
1292         .name       = DRV_NAME,
1293         .pm     = HDLC_PM_OPS,
1294         .of_match_table = fsl_ucc_hdlc_of_match,
1295     },
1296 };
1297 
1298 module_platform_driver(ucc_hdlc_driver);
1299 MODULE_LICENSE("GPL");
1300 MODULE_DESCRIPTION(DRV_DESC);
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