net/vmxnet3/vmxnet3_defs.h

0001 /*
0002  * Linux driver for VMware's vmxnet3 ethernet NIC.
0003  *
0004  * Copyright (C) 2008-2022, VMware, Inc. All Rights Reserved.
0005  *
0006  * This program is free software; you can redistribute it and/or modify it
0007  * under the terms of the GNU General Public License as published by the
0008  * Free Software Foundation; version 2 of the License and no later version.
0009  *
0010  * This program is distributed in the hope that it will be useful, but
0011  * WITHOUT ANY WARRANTY; without even the implied warranty of
0012  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
0013  * NON INFRINGEMENT.  See the GNU General Public License for more
0014  * details.
0015  *
0016  * You should have received a copy of the GNU General Public License
0017  * along with this program; if not, write to the Free Software
0018  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
0019  *
0020  * The full GNU General Public License is included in this distribution in
0021  * the file called "COPYING".
0022  *
0023  * Maintained by: pv-drivers@vmware.com
0024  *
0025  */
0026
0027 #ifndef _VMXNET3_DEFS_H_
0028 #define _VMXNET3_DEFS_H_
0029
0030 #include "upt1_defs.h"
0031
0032 /* all registers are 32 bit wide */
0033 /* BAR 1 */
0034 enum {
0035     VMXNET3_REG_VRRS    = 0x0,  /* Vmxnet3 Revision Report Selection */
0036     VMXNET3_REG_UVRS    = 0x8,  /* UPT Version Report Selection */
0037     VMXNET3_REG_DSAL    = 0x10, /* Driver Shared Address Low */
0038     VMXNET3_REG_DSAH    = 0x18, /* Driver Shared Address High */
0039     VMXNET3_REG_CMD     = 0x20, /* Command */
0040     VMXNET3_REG_MACL    = 0x28, /* MAC Address Low */
0041     VMXNET3_REG_MACH    = 0x30, /* MAC Address High */
0042     VMXNET3_REG_ICR     = 0x38, /* Interrupt Cause Register */
0043     VMXNET3_REG_ECR     = 0x40, /* Event Cause Register */
0044     VMXNET3_REG_DCR         = 0x48, /* Device capability register,
0045                      * from 0x48 to 0x80
0046                      */
0047     VMXNET3_REG_PTCR        = 0x88, /* Passthru capbility register
0048                      * from 0x88 to 0xb0
0049                      */
0050 };
0051
0052 /* BAR 0 */
0053 enum {
0054     VMXNET3_REG_IMR     = 0x0,   /* Interrupt Mask Register */
0055     VMXNET3_REG_TXPROD  = 0x600, /* Tx Producer Index */
0056     VMXNET3_REG_RXPROD  = 0x800, /* Rx Producer Index for ring 1 */
0057     VMXNET3_REG_RXPROD2 = 0xA00  /* Rx Producer Index for ring 2 */
0058 };
0059
0060 /* For Large PT BAR, the following offset to DB register */
0061 enum {
0062     VMXNET3_REG_LB_TXPROD   = 0x1000, /* Tx Producer Index */
0063     VMXNET3_REG_LB_RXPROD   = 0x1400, /* Rx Producer Index for ring 1 */
0064     VMXNET3_REG_LB_RXPROD2  = 0x1800, /* Rx Producer Index for ring 2 */
0065 };
0066
0067 #define VMXNET3_PT_REG_SIZE         4096        /* BAR 0 */
0068 #define VMXNET3_LARGE_PT_REG_SIZE   8192        /* large PT pages */
0069 #define VMXNET3_VD_REG_SIZE         4096        /* BAR 1 */
0070 #define VMXNET3_LARGE_BAR0_REG_SIZE (4096 * 4096)   /* LARGE BAR 0 */
0071 #define VMXNET3_OOB_REG_SIZE        (4094 * 4096)   /* OOB pages */
0072
0073 #define VMXNET3_REG_ALIGN       8   /* All registers are 8-byte aligned. */
0074 #define VMXNET3_REG_ALIGN_MASK  0x7
0075
0076 /* I/O Mapped access to registers */
0077 #define VMXNET3_IO_TYPE_PT              0
0078 #define VMXNET3_IO_TYPE_VD              1
0079 #define VMXNET3_IO_ADDR(type, reg)      (((type) << 24) | ((reg) & 0xFFFFFF))
0080 #define VMXNET3_IO_TYPE(addr)           ((addr) >> 24)
0081 #define VMXNET3_IO_REG(addr)            ((addr) & 0xFFFFFF)
0082
0083 enum {
0084     VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
0085     VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
0086     VMXNET3_CMD_QUIESCE_DEV,
0087     VMXNET3_CMD_RESET_DEV,
0088     VMXNET3_CMD_UPDATE_RX_MODE,
0089     VMXNET3_CMD_UPDATE_MAC_FILTERS,
0090     VMXNET3_CMD_UPDATE_VLAN_FILTERS,
0091     VMXNET3_CMD_UPDATE_RSSIDT,
0092     VMXNET3_CMD_UPDATE_IML,
0093     VMXNET3_CMD_UPDATE_PMCFG,
0094     VMXNET3_CMD_UPDATE_FEATURE,
0095     VMXNET3_CMD_RESERVED1,
0096     VMXNET3_CMD_LOAD_PLUGIN,
0097     VMXNET3_CMD_RESERVED2,
0098     VMXNET3_CMD_RESERVED3,
0099     VMXNET3_CMD_SET_COALESCE,
0100     VMXNET3_CMD_REGISTER_MEMREGS,
0101     VMXNET3_CMD_SET_RSS_FIELDS,
0102     VMXNET3_CMD_RESERVED4,
0103     VMXNET3_CMD_RESERVED5,
0104     VMXNET3_CMD_SET_RING_BUFFER_SIZE,
0105
0106     VMXNET3_CMD_FIRST_GET = 0xF00D0000,
0107     VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
0108     VMXNET3_CMD_GET_STATS,
0109     VMXNET3_CMD_GET_LINK,
0110     VMXNET3_CMD_GET_PERM_MAC_LO,
0111     VMXNET3_CMD_GET_PERM_MAC_HI,
0112     VMXNET3_CMD_GET_DID_LO,
0113     VMXNET3_CMD_GET_DID_HI,
0114     VMXNET3_CMD_GET_DEV_EXTRA_INFO,
0115     VMXNET3_CMD_GET_CONF_INTR,
0116     VMXNET3_CMD_GET_RESERVED1,
0117     VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
0118     VMXNET3_CMD_GET_COALESCE,
0119     VMXNET3_CMD_GET_RSS_FIELDS,
0120     VMXNET3_CMD_GET_RESERVED2,
0121     VMXNET3_CMD_GET_RESERVED3,
0122     VMXNET3_CMD_GET_MAX_QUEUES_CONF,
0123     VMXNET3_CMD_GET_RESERVED4,
0124     VMXNET3_CMD_GET_MAX_CAPABILITIES,
0125     VMXNET3_CMD_GET_DCR0_REG,
0126 };
0127
0128 /*
0129  *  Little Endian layout of bitfields -
0130  *  Byte 0 :    7.....len.....0
0131  *  Byte 1 :    oco gen 13.len.8
0132  *  Byte 2 :    5.msscof.0 ext1  dtype
0133  *  Byte 3 :    13...msscof...6
0134  *
0135  *  Big Endian layout of bitfields -
0136  *  Byte 0:     13...msscof...6
0137  *  Byte 1 :    5.msscof.0 ext1  dtype
0138  *  Byte 2 :    oco gen 13.len.8
0139  *  Byte 3 :    7.....len.....0
0140  *
0141  *  Thus, le32_to_cpu on the dword will allow the big endian driver to read
0142  *  the bit fields correctly. And cpu_to_le32 will convert bitfields
0143  *  bit fields written by big endian driver to format required by device.
0144  */
0145
0146 struct Vmxnet3_TxDesc {
0147     __le64 addr;
0148
0149 #ifdef __BIG_ENDIAN_BITFIELD
0150     u32 msscof:14;  /* MSS, checksum offset, flags */
0151     u32 ext1:1;     /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */
0152     u32 dtype:1;    /* descriptor type */
0153     u32 oco:1;      /* Outer csum offload */
0154     u32 gen:1;      /* generation bit */
0155     u32 len:14;
0156 #else
0157     u32 len:14;
0158     u32 gen:1;      /* generation bit */
0159     u32 oco:1;      /* Outer csum offload */
0160     u32 dtype:1;    /* descriptor type */
0161     u32 ext1:1;     /* set to 1 to indicate inner csum/tso, vmxnet3 v7 */
0162     u32 msscof:14;  /* MSS, checksum offset, flags */
0163 #endif  /* __BIG_ENDIAN_BITFIELD */
0164
0165 #ifdef __BIG_ENDIAN_BITFIELD
0166     u32 tci:16;     /* Tag to Insert */
0167     u32 ti:1;       /* VLAN Tag Insertion */
0168     u32 ext2:1;
0169     u32 cq:1;       /* completion request */
0170     u32 eop:1;      /* End Of Packet */
0171     u32 om:2;       /* offload mode */
0172     u32 hlen:10;    /* header len */
0173 #else
0174     u32 hlen:10;    /* header len */
0175     u32 om:2;       /* offload mode */
0176     u32 eop:1;      /* End Of Packet */
0177     u32 cq:1;       /* completion request */
0178     u32 ext2:1;
0179     u32 ti:1;       /* VLAN Tag Insertion */
0180     u32 tci:16;     /* Tag to Insert */
0181 #endif  /* __BIG_ENDIAN_BITFIELD */
0182 };
0183
0184 /* TxDesc.OM values */
0185 #define VMXNET3_OM_NONE         0
0186 #define VMXNET3_OM_ENCAP        1
0187 #define VMXNET3_OM_CSUM         2
0188 #define VMXNET3_OM_TSO          3
0189
0190 /* fields in TxDesc we access w/o using bit fields */
0191 #define VMXNET3_TXD_EOP_SHIFT   12
0192 #define VMXNET3_TXD_CQ_SHIFT    13
0193 #define VMXNET3_TXD_GEN_SHIFT   14
0194 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
0195 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
0196
0197 #define VMXNET3_TXD_CQ      (1 << VMXNET3_TXD_CQ_SHIFT)
0198 #define VMXNET3_TXD_EOP     (1 << VMXNET3_TXD_EOP_SHIFT)
0199 #define VMXNET3_TXD_GEN     (1 << VMXNET3_TXD_GEN_SHIFT)
0200
0201 #define VMXNET3_HDR_COPY_SIZE   128
0202
0203
0204 struct Vmxnet3_TxDataDesc {
0205     u8      data[VMXNET3_HDR_COPY_SIZE];
0206 };
0207
0208 typedef u8 Vmxnet3_RxDataDesc;
0209
0210 #define VMXNET3_TCD_GEN_SHIFT   31
0211 #define VMXNET3_TCD_GEN_SIZE    1
0212 #define VMXNET3_TCD_TXIDX_SHIFT 0
0213 #define VMXNET3_TCD_TXIDX_SIZE  12
0214 #define VMXNET3_TCD_GEN_DWORD_SHIFT 3
0215
0216 struct Vmxnet3_TxCompDesc {
0217     u32     txdIdx:12;    /* Index of the EOP TxDesc */
0218     u32     ext1:20;
0219
0220     __le32      ext2;
0221     __le32      ext3;
0222
0223     u32     rsvd:24;
0224     u32     type:7;       /* completion type */
0225     u32     gen:1;        /* generation bit */
0226 };
0227
0228 struct Vmxnet3_RxDesc {
0229     __le64      addr;
0230
0231 #ifdef __BIG_ENDIAN_BITFIELD
0232     u32     gen:1;        /* Generation bit */
0233     u32     rsvd:15;
0234     u32     dtype:1;      /* Descriptor type */
0235     u32     btype:1;      /* Buffer Type */
0236     u32     len:14;
0237 #else
0238     u32     len:14;
0239     u32     btype:1;      /* Buffer Type */
0240     u32     dtype:1;      /* Descriptor type */
0241     u32     rsvd:15;
0242     u32     gen:1;        /* Generation bit */
0243 #endif
0244     u32     ext1;
0245 };
0246
0247 /* values of RXD.BTYPE */
0248 #define VMXNET3_RXD_BTYPE_HEAD   0    /* head only */
0249 #define VMXNET3_RXD_BTYPE_BODY   1    /* body only */
0250
0251 /* fields in RxDesc we access w/o using bit fields */
0252 #define VMXNET3_RXD_BTYPE_SHIFT  14
0253 #define VMXNET3_RXD_GEN_SHIFT    31
0254
0255 #define VMXNET3_RCD_HDR_INNER_SHIFT  13
0256
0257 struct Vmxnet3_RxCompDesc {
0258 #ifdef __BIG_ENDIAN_BITFIELD
0259     u32     ext2:1;
0260     u32     cnc:1;        /* Checksum Not Calculated */
0261     u32     rssType:4;    /* RSS hash type used */
0262     u32     rqID:10;      /* rx queue/ring ID */
0263     u32     sop:1;        /* Start of Packet */
0264     u32     eop:1;        /* End of Packet */
0265     u32     ext1:2;       /* bit 0: indicating v4/v6/.. is for inner header */
0266                       /* bit 1: indicating rssType is based on inner header */
0267     u32     rxdIdx:12;    /* Index of the RxDesc */
0268 #else
0269     u32     rxdIdx:12;    /* Index of the RxDesc */
0270     u32     ext1:2;       /* bit 0: indicating v4/v6/.. is for inner header */
0271                       /* bit 1: indicating rssType is based on inner header */
0272     u32     eop:1;        /* End of Packet */
0273     u32     sop:1;        /* Start of Packet */
0274     u32     rqID:10;      /* rx queue/ring ID */
0275     u32     rssType:4;    /* RSS hash type used */
0276     u32     cnc:1;        /* Checksum Not Calculated */
0277     u32     ext2:1;
0278 #endif  /* __BIG_ENDIAN_BITFIELD */
0279
0280     __le32      rssHash;      /* RSS hash value */
0281
0282 #ifdef __BIG_ENDIAN_BITFIELD
0283     u32     tci:16;       /* Tag stripped */
0284     u32     ts:1;         /* Tag is stripped */
0285     u32     err:1;        /* Error */
0286     u32     len:14;       /* data length */
0287 #else
0288     u32     len:14;       /* data length */
0289     u32     err:1;        /* Error */
0290     u32     ts:1;         /* Tag is stripped */
0291     u32     tci:16;       /* Tag stripped */
0292 #endif  /* __BIG_ENDIAN_BITFIELD */
0293
0294
0295 #ifdef __BIG_ENDIAN_BITFIELD
0296     u32     gen:1;        /* generation bit */
0297     u32     type:7;       /* completion type */
0298     u32     fcs:1;        /* Frame CRC correct */
0299     u32     frg:1;        /* IP Fragment */
0300     u32     v4:1;         /* IPv4 */
0301     u32     v6:1;         /* IPv6 */
0302     u32     ipc:1;        /* IP Checksum Correct */
0303     u32     tcp:1;        /* TCP packet */
0304     u32     udp:1;        /* UDP packet */
0305     u32     tuc:1;        /* TCP/UDP Checksum Correct */
0306     u32     csum:16;
0307 #else
0308     u32     csum:16;
0309     u32     tuc:1;        /* TCP/UDP Checksum Correct */
0310     u32     udp:1;        /* UDP packet */
0311     u32     tcp:1;        /* TCP packet */
0312     u32     ipc:1;        /* IP Checksum Correct */
0313     u32     v6:1;         /* IPv6 */
0314     u32     v4:1;         /* IPv4 */
0315     u32     frg:1;        /* IP Fragment */
0316     u32     fcs:1;        /* Frame CRC correct */
0317     u32     type:7;       /* completion type */
0318     u32     gen:1;        /* generation bit */
0319 #endif  /* __BIG_ENDIAN_BITFIELD */
0320 };
0321
0322 struct Vmxnet3_RxCompDescExt {
0323     __le32      dword1;
0324     u8      segCnt;       /* Number of aggregated packets */
0325     u8      dupAckCnt;    /* Number of duplicate Acks */
0326     __le16      tsDelta;      /* TCP timestamp difference */
0327     __le32      dword2;
0328 #ifdef __BIG_ENDIAN_BITFIELD
0329     u32     gen:1;        /* generation bit */
0330     u32     type:7;       /* completion type */
0331     u32     fcs:1;        /* Frame CRC correct */
0332     u32     frg:1;        /* IP Fragment */
0333     u32     v4:1;         /* IPv4 */
0334     u32     v6:1;         /* IPv6 */
0335     u32     ipc:1;        /* IP Checksum Correct */
0336     u32     tcp:1;        /* TCP packet */
0337     u32     udp:1;        /* UDP packet */
0338     u32     tuc:1;        /* TCP/UDP Checksum Correct */
0339     u32     mss:16;
0340 #else
0341     u32     mss:16;
0342     u32     tuc:1;        /* TCP/UDP Checksum Correct */
0343     u32     udp:1;        /* UDP packet */
0344     u32     tcp:1;        /* TCP packet */
0345     u32     ipc:1;        /* IP Checksum Correct */
0346     u32     v6:1;         /* IPv6 */
0347     u32     v4:1;         /* IPv4 */
0348     u32     frg:1;        /* IP Fragment */
0349     u32     fcs:1;        /* Frame CRC correct */
0350     u32     type:7;       /* completion type */
0351     u32     gen:1;        /* generation bit */
0352 #endif  /* __BIG_ENDIAN_BITFIELD */
0353 };
0354
0355
0356 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
0357 #define VMXNET3_RCD_TUC_SHIFT   16
0358 #define VMXNET3_RCD_IPC_SHIFT   19
0359
0360 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
0361 #define VMXNET3_RCD_TYPE_SHIFT  56
0362 #define VMXNET3_RCD_GEN_SHIFT   63
0363
0364 /* csum OK for TCP/UDP pkts over IP */
0365 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | \
0366                  1 << VMXNET3_RCD_IPC_SHIFT)
0367 #define VMXNET3_TXD_GEN_SIZE 1
0368 #define VMXNET3_TXD_EOP_SIZE 1
0369
0370 /* value of RxCompDesc.rssType */
0371 #define VMXNET3_RCD_RSS_TYPE_NONE     0
0372 #define VMXNET3_RCD_RSS_TYPE_IPV4     1
0373 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4  2
0374 #define VMXNET3_RCD_RSS_TYPE_IPV6     3
0375 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6  4
0376 #define VMXNET3_RCD_RSS_TYPE_UDPIPV4  5
0377 #define VMXNET3_RCD_RSS_TYPE_UDPIPV6  6
0378 #define VMXNET3_RCD_RSS_TYPE_ESPIPV4  7
0379 #define VMXNET3_RCD_RSS_TYPE_ESPIPV6  8
0380
0381
0382 /* a union for accessing all cmd/completion descriptors */
0383 union Vmxnet3_GenericDesc {
0384     __le64              qword[2];
0385     __le32              dword[4];
0386     __le16              word[8];
0387     struct Vmxnet3_TxDesc       txd;
0388     struct Vmxnet3_RxDesc       rxd;
0389     struct Vmxnet3_TxCompDesc   tcd;
0390     struct Vmxnet3_RxCompDesc   rcd;
0391     struct Vmxnet3_RxCompDescExt    rcdExt;
0392 };
0393
0394 #define VMXNET3_INIT_GEN       1
0395
0396 /* Max size of a single tx buffer */
0397 #define VMXNET3_MAX_TX_BUF_SIZE  (1 << 14)
0398
0399 /* # of tx desc needed for a tx buffer size */
0400 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / \
0401                   VMXNET3_MAX_TX_BUF_SIZE)
0402
0403 /* max # of tx descs for a non-tso pkt */
0404 #define VMXNET3_MAX_TXD_PER_PKT 16
0405 /* max # of tx descs for a tso pkt */
0406 #define VMXNET3_MAX_TSO_TXD_PER_PKT 24
0407
0408 /* Max size of a single rx buffer */
0409 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
0410 /* Minimum size of a type 0 buffer */
0411 #define VMXNET3_MIN_T0_BUF_SIZE  128
0412 #define VMXNET3_MAX_CSUM_OFFSET  1024
0413
0414 /* Ring base address alignment */
0415 #define VMXNET3_RING_BA_ALIGN   512
0416 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
0417
0418 /* Ring size must be a multiple of 32 */
0419 #define VMXNET3_RING_SIZE_ALIGN 32
0420 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
0421
0422 /* Tx Data Ring buffer size must be a multiple of 64 */
0423 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
0424 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
0425
0426 /* Rx Data Ring buffer size must be a multiple of 64 */
0427 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
0428 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
0429
0430 /* Max ring size */
0431 #define VMXNET3_TX_RING_MAX_SIZE   4096
0432 #define VMXNET3_TC_RING_MAX_SIZE   4096
0433 #define VMXNET3_RX_RING_MAX_SIZE   4096
0434 #define VMXNET3_RX_RING2_MAX_SIZE  4096
0435 #define VMXNET3_RC_RING_MAX_SIZE   8192
0436
0437 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128
0438 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
0439
0440 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
0441
0442 /* a list of reasons for queue stop */
0443
0444 enum {
0445  VMXNET3_ERR_NOEOP        = 0x80000000,  /* cannot find the EOP desc of a pkt */
0446  VMXNET3_ERR_TXD_REUSE    = 0x80000001,  /* reuse TxDesc before tx completion */
0447  VMXNET3_ERR_BIG_PKT      = 0x80000002,  /* too many TxDesc for a pkt */
0448  VMXNET3_ERR_DESC_NOT_SPT = 0x80000003,  /* descriptor type not supported */
0449  VMXNET3_ERR_SMALL_BUF    = 0x80000004,  /* type 0 buffer too small */
0450  VMXNET3_ERR_STRESS       = 0x80000005,  /* stress option firing in vmkernel */
0451  VMXNET3_ERR_SWITCH       = 0x80000006,  /* mode switch failure */
0452  VMXNET3_ERR_TXD_INVALID  = 0x80000007,  /* invalid TxDesc */
0453 };
0454
0455 /* completion descriptor types */
0456 #define VMXNET3_CDTYPE_TXCOMP      0    /* Tx Completion Descriptor */
0457 #define VMXNET3_CDTYPE_RXCOMP      3    /* Rx Completion Descriptor */
0458 #define VMXNET3_CDTYPE_RXCOMP_LRO  4    /* Rx Completion Descriptor for LRO */
0459
0460 enum {
0461     VMXNET3_GOS_BITS_UNK    = 0,   /* unknown */
0462     VMXNET3_GOS_BITS_32     = 1,
0463     VMXNET3_GOS_BITS_64     = 2,
0464 };
0465
0466 #define VMXNET3_GOS_TYPE_LINUX  1
0467
0468
0469 struct Vmxnet3_GOSInfo {
0470 #ifdef __BIG_ENDIAN_BITFIELD
0471     u32     gosMisc:10;    /* other info about gos */
0472     u32     gosVer:16;     /* gos version */
0473     u32     gosType:4;     /* which guest */
0474     u32     gosBits:2;    /* 32-bit or 64-bit? */
0475 #else
0476     u32     gosBits:2;     /* 32-bit or 64-bit? */
0477     u32     gosType:4;     /* which guest */
0478     u32     gosVer:16;     /* gos version */
0479     u32     gosMisc:10;    /* other info about gos */
0480 #endif  /* __BIG_ENDIAN_BITFIELD */
0481 };
0482
0483 struct Vmxnet3_DriverInfo {
0484     __le32              version;
0485     struct Vmxnet3_GOSInfo      gos;
0486     __le32              vmxnet3RevSpt;
0487     __le32              uptVerSpt;
0488 };
0489
0490
0491 #define VMXNET3_REV1_MAGIC  3133079265u
0492
0493 /*
0494  * QueueDescPA must be 128 bytes aligned. It points to an array of
0495  * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
0496  * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
0497  * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
0498  */
0499 #define VMXNET3_QUEUE_DESC_ALIGN  128
0500
0501
0502 struct Vmxnet3_MiscConf {
0503     struct Vmxnet3_DriverInfo driverInfo;
0504     __le64      uptFeatures;
0505     __le64      ddPA;         /* driver data PA */
0506     __le64      queueDescPA;  /* queue descriptor table PA */
0507     __le32      ddLen;        /* driver data len */
0508     __le32      queueDescLen; /* queue desc. table len in bytes */
0509     __le32      mtu;
0510     __le16      maxNumRxSG;
0511     u8      numTxQueues;
0512     u8      numRxQueues;
0513     __le32      reserved[4];
0514 };
0515
0516
0517 struct Vmxnet3_TxQueueConf {
0518     __le64      txRingBasePA;
0519     __le64      dataRingBasePA;
0520     __le64      compRingBasePA;
0521     __le64      ddPA;         /* driver data */
0522     __le64      reserved;
0523     __le32      txRingSize;   /* # of tx desc */
0524     __le32      dataRingSize; /* # of data desc */
0525     __le32      compRingSize; /* # of comp desc */
0526     __le32      ddLen;        /* size of driver data */
0527     u8      intrIdx;
0528     u8      _pad1[1];
0529     __le16      txDataRingDescSize;
0530     u8      _pad2[4];
0531 };
0532
0533
0534 struct Vmxnet3_RxQueueConf {
0535     __le64      rxRingBasePA[2];
0536     __le64      compRingBasePA;
0537     __le64      ddPA;            /* driver data */
0538     __le64      rxDataRingBasePA;
0539     __le32      rxRingSize[2];   /* # of rx desc */
0540     __le32      compRingSize;    /* # of rx comp desc */
0541     __le32      ddLen;           /* size of driver data */
0542     u8      intrIdx;
0543     u8      _pad1[1];
0544     __le16      rxDataRingDescSize;  /* size of rx data ring buffer */
0545     u8      _pad2[4];
0546 };
0547
0548
0549 enum vmxnet3_intr_mask_mode {
0550     VMXNET3_IMM_AUTO   = 0,
0551     VMXNET3_IMM_ACTIVE = 1,
0552     VMXNET3_IMM_LAZY   = 2
0553 };
0554
0555 enum vmxnet3_intr_type {
0556     VMXNET3_IT_AUTO = 0,
0557     VMXNET3_IT_INTX = 1,
0558     VMXNET3_IT_MSI  = 2,
0559     VMXNET3_IT_MSIX = 3
0560 };
0561
0562 #define VMXNET3_MAX_TX_QUEUES  8
0563 #define VMXNET3_MAX_RX_QUEUES  16
0564 /* addition 1 for events */
0565 #define VMXNET3_MAX_INTRS      25
0566
0567 /* Version 6 and later will use below macros */
0568 #define VMXNET3_EXT_MAX_TX_QUEUES  32
0569 #define VMXNET3_EXT_MAX_RX_QUEUES  32
0570 /* addition 1 for events */
0571 #define VMXNET3_EXT_MAX_INTRS      65
0572 #define VMXNET3_FIRST_SET_INTRS    64
0573
0574 /* value of intrCtrl */
0575 #define VMXNET3_IC_DISABLE_ALL  0x1   /* bit 0 */
0576
0577
0578 struct Vmxnet3_IntrConf {
0579     bool        autoMask;
0580     u8      numIntrs;      /* # of interrupts */
0581     u8      eventIntrIdx;
0582     u8      modLevels[VMXNET3_MAX_INTRS];   /* moderation level for
0583                              * each intr */
0584     __le32      intrCtrl;
0585     __le32      reserved[2];
0586 };
0587
0588 struct Vmxnet3_IntrConfExt {
0589     u8              autoMask;
0590     u8              numIntrs;      /* # of interrupts */
0591     u8              eventIntrIdx;
0592     u8              reserved;
0593     __le32          intrCtrl;
0594     __le32          reserved1;
0595     u8              modLevels[VMXNET3_EXT_MAX_INTRS]; /* moderation level for
0596                                * each intr
0597                                */
0598     u8              reserved2[3];
0599 };
0600
0601 /* one bit per VLAN ID, the size is in the units of u32 */
0602 #define VMXNET3_VFT_SIZE  (4096 / (sizeof(u32) * 8))
0603
0604
0605 struct Vmxnet3_QueueStatus {
0606     bool        stopped;
0607     u8      _pad[3];
0608     __le32      error;
0609 };
0610
0611
0612 struct Vmxnet3_TxQueueCtrl {
0613     __le32      txNumDeferred;
0614     __le32      txThreshold;
0615     __le64      reserved;
0616 };
0617
0618
0619 struct Vmxnet3_RxQueueCtrl {
0620     bool        updateRxProd;
0621     u8      _pad[7];
0622     __le64      reserved;
0623 };
0624
0625 enum {
0626     VMXNET3_RXM_UCAST     = 0x01,  /* unicast only */
0627     VMXNET3_RXM_MCAST     = 0x02,  /* multicast passing the filters */
0628     VMXNET3_RXM_BCAST     = 0x04,  /* broadcast only */
0629     VMXNET3_RXM_ALL_MULTI = 0x08,  /* all multicast */
0630     VMXNET3_RXM_PROMISC   = 0x10  /* promiscuous */
0631 };
0632
0633 struct Vmxnet3_RxFilterConf {
0634     __le32      rxMode;       /* VMXNET3_RXM_xxx */
0635     __le16      mfTableLen;   /* size of the multicast filter table */
0636     __le16      _pad1;
0637     __le64      mfTablePA;    /* PA of the multicast filters table */
0638     __le32      vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
0639 };
0640
0641
0642 #define VMXNET3_PM_MAX_FILTERS        6
0643 #define VMXNET3_PM_MAX_PATTERN_SIZE   128
0644 #define VMXNET3_PM_MAX_MASK_SIZE      (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
0645
0646 #define VMXNET3_PM_WAKEUP_MAGIC       cpu_to_le16(0x01)  /* wake up on magic pkts */
0647 #define VMXNET3_PM_WAKEUP_FILTER      cpu_to_le16(0x02)  /* wake up on pkts matching
0648                               * filters */
0649
0650
0651 struct Vmxnet3_PM_PktFilter {
0652     u8      maskSize;
0653     u8      patternSize;
0654     u8      mask[VMXNET3_PM_MAX_MASK_SIZE];
0655     u8      pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
0656     u8      pad[6];
0657 };
0658
0659
0660 struct Vmxnet3_PMConf {
0661     __le16      wakeUpEvents;  /* VMXNET3_PM_WAKEUP_xxx */
0662     u8      numFilters;
0663     u8      pad[5];
0664     struct Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
0665 };
0666
0667
0668 struct Vmxnet3_VariableLenConfDesc {
0669     __le32      confVer;
0670     __le32      confLen;
0671     __le64      confPA;
0672 };
0673
0674
0675 struct Vmxnet3_TxQueueDesc {
0676     struct Vmxnet3_TxQueueCtrl      ctrl;
0677     struct Vmxnet3_TxQueueConf      conf;
0678
0679     /* Driver read after a GET command */
0680     struct Vmxnet3_QueueStatus      status;
0681     struct UPT1_TxStats         stats;
0682     u8                  _pad[88]; /* 128 aligned */
0683 };
0684
0685
0686 struct Vmxnet3_RxQueueDesc {
0687     struct Vmxnet3_RxQueueCtrl      ctrl;
0688     struct Vmxnet3_RxQueueConf      conf;
0689     /* Driver read after a GET commad */
0690     struct Vmxnet3_QueueStatus      status;
0691     struct UPT1_RxStats         stats;
0692     u8                    __pad[88]; /* 128 aligned */
0693 };
0694
0695 struct Vmxnet3_SetPolling {
0696     u8                  enablePolling;
0697 };
0698
0699 #define VMXNET3_COAL_STATIC_MAX_DEPTH       128
0700 #define VMXNET3_COAL_RBC_MIN_RATE       100
0701 #define VMXNET3_COAL_RBC_MAX_RATE       100000
0702
0703 enum Vmxnet3_CoalesceMode {
0704     VMXNET3_COALESCE_DISABLED   = 0,
0705     VMXNET3_COALESCE_ADAPT      = 1,
0706     VMXNET3_COALESCE_STATIC     = 2,
0707     VMXNET3_COALESCE_RBC        = 3
0708 };
0709
0710 struct Vmxnet3_CoalesceRbc {
0711     u32                 rbc_rate;
0712 };
0713
0714 struct Vmxnet3_CoalesceStatic {
0715     u32                 tx_depth;
0716     u32                 tx_comp_depth;
0717     u32                 rx_depth;
0718 };
0719
0720 struct Vmxnet3_CoalesceScheme {
0721     enum Vmxnet3_CoalesceMode       coalMode;
0722     union {
0723         struct Vmxnet3_CoalesceRbc  coalRbc;
0724         struct Vmxnet3_CoalesceStatic   coalStatic;
0725     } coalPara;
0726 };
0727
0728 struct Vmxnet3_MemoryRegion {
0729     __le64                  startPA;
0730     __le32                  length;
0731     __le16                  txQueueBits;
0732     __le16                  rxQueueBits;
0733 };
0734
0735 #define MAX_MEMORY_REGION_PER_QUEUE 16
0736 #define MAX_MEMORY_REGION_PER_DEVICE 256
0737
0738 struct Vmxnet3_MemRegs {
0739     __le16                  numRegs;
0740     __le16                  pad[3];
0741     struct Vmxnet3_MemoryRegion     memRegs[1];
0742 };
0743
0744 enum Vmxnet3_RSSField {
0745     VMXNET3_RSS_FIELDS_TCPIP4 = 0x0001,
0746     VMXNET3_RSS_FIELDS_TCPIP6 = 0x0002,
0747     VMXNET3_RSS_FIELDS_UDPIP4 = 0x0004,
0748     VMXNET3_RSS_FIELDS_UDPIP6 = 0x0008,
0749     VMXNET3_RSS_FIELDS_ESPIP4 = 0x0010,
0750     VMXNET3_RSS_FIELDS_ESPIP6 = 0x0020,
0751 };
0752
0753 struct Vmxnet3_RingBufferSize {
0754     __le16             ring1BufSizeType0;
0755     __le16             ring1BufSizeType1;
0756     __le16             ring2BufSizeType1;
0757     __le16             pad;
0758 };
0759
0760 /* If the command data <= 16 bytes, use the shared memory directly.
0761  * otherwise, use variable length configuration descriptor.
0762  */
0763 union Vmxnet3_CmdInfo {
0764     struct Vmxnet3_VariableLenConfDesc  varConf;
0765     struct Vmxnet3_SetPolling       setPolling;
0766     enum   Vmxnet3_RSSField                 setRssFields;
0767     struct Vmxnet3_RingBufferSize           ringBufSize;
0768     __le64                  data[2];
0769 };
0770
0771 struct Vmxnet3_DSDevRead {
0772     /* read-only region for device, read by dev in response to a SET cmd */
0773     struct Vmxnet3_MiscConf         misc;
0774     struct Vmxnet3_IntrConf         intrConf;
0775     struct Vmxnet3_RxFilterConf     rxFilterConf;
0776     struct Vmxnet3_VariableLenConfDesc  rssConfDesc;
0777     struct Vmxnet3_VariableLenConfDesc  pmConfDesc;
0778     struct Vmxnet3_VariableLenConfDesc  pluginConfDesc;
0779 };
0780
0781 struct Vmxnet3_DSDevReadExt {
0782     /* read-only region for device, read by dev in response to a SET cmd */
0783     struct Vmxnet3_IntrConfExt              intrConfExt;
0784 };
0785
0786 /* All structures in DriverShared are padded to multiples of 8 bytes */
0787 struct Vmxnet3_DriverShared {
0788     __le32              magic;
0789     /* make devRead start at 64bit boundaries */
0790     __le32                          size; /* size of DriverShared */
0791     struct Vmxnet3_DSDevRead    devRead;
0792     __le32              ecr;
0793     __le32              reserved;
0794     union {
0795         __le32          reserved1[4];
0796         union Vmxnet3_CmdInfo   cmdInfo; /* only valid in the context of
0797                           * executing the relevant
0798                           * command
0799                           */
0800     } cu;
0801     struct Vmxnet3_DSDevReadExt     devReadExt;
0802 };
0803
0804
0805 #define VMXNET3_ECR_RQERR       (1 << 0)
0806 #define VMXNET3_ECR_TQERR       (1 << 1)
0807 #define VMXNET3_ECR_LINK        (1 << 2)
0808 #define VMXNET3_ECR_DIC         (1 << 3)
0809 #define VMXNET3_ECR_DEBUG       (1 << 4)
0810
0811 /* flip the gen bit of a ring */
0812 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
0813
0814 /* only use this if moving the idx won't affect the gen bit */
0815 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
0816     do {\
0817         (idx)++;\
0818         if (unlikely((idx) == (ring_size))) {\
0819             (idx) = 0;\
0820         } \
0821     } while (0)
0822
0823 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
0824     (vfTable[vid >> 5] |= (1 << (vid & 31)))
0825 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
0826     (vfTable[vid >> 5] &= ~(1 << (vid & 31)))
0827
0828 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
0829     ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
0830
0831 #define VMXNET3_MAX_MTU     9000
0832 #define VMXNET3_V6_MAX_MTU  9190
0833 #define VMXNET3_MIN_MTU     60
0834
0835 #define VMXNET3_LINK_UP         (10000 << 16 | 1)    /* 10 Gbps, up */
0836 #define VMXNET3_LINK_DOWN       0
0837
0838 #define VMXNET3_DCR_ERROR                          31   /* error when bit 31 of DCR is set */
0839 #define VMXNET3_CAP_UDP_RSS                        0    /* bit 0 of DCR 0 */
0840 #define VMXNET3_CAP_ESP_RSS_IPV4                   1    /* bit 1 of DCR 0 */
0841 #define VMXNET3_CAP_GENEVE_CHECKSUM_OFFLOAD        2    /* bit 2 of DCR 0 */
0842 #define VMXNET3_CAP_GENEVE_TSO                     3    /* bit 3 of DCR 0 */
0843 #define VMXNET3_CAP_VXLAN_CHECKSUM_OFFLOAD         4    /* bit 4 of DCR 0 */
0844 #define VMXNET3_CAP_VXLAN_TSO                      5    /* bit 5 of DCR 0 */
0845 #define VMXNET3_CAP_GENEVE_OUTER_CHECKSUM_OFFLOAD  6    /* bit 6 of DCR 0 */
0846 #define VMXNET3_CAP_VXLAN_OUTER_CHECKSUM_OFFLOAD   7    /* bit 7 of DCR 0 */
0847 #define VMXNET3_CAP_PKT_STEERING_IPV4              8    /* bit 8 of DCR 0 */
0848 #define VMXNET3_CAP_VERSION_4_MAX                  VMXNET3_CAP_PKT_STEERING_IPV4
0849 #define VMXNET3_CAP_ESP_RSS_IPV6                   9    /* bit 9 of DCR 0 */
0850 #define VMXNET3_CAP_VERSION_5_MAX                  VMXNET3_CAP_ESP_RSS_IPV6
0851 #define VMXNET3_CAP_ESP_OVER_UDP_RSS               10   /* bit 10 of DCR 0 */
0852 #define VMXNET3_CAP_INNER_RSS                      11   /* bit 11 of DCR 0 */
0853 #define VMXNET3_CAP_INNER_ESP_RSS                  12   /* bit 12 of DCR 0 */
0854 #define VMXNET3_CAP_CRC32_HASH_FUNC                13   /* bit 13 of DCR 0 */
0855 #define VMXNET3_CAP_VERSION_6_MAX                  VMXNET3_CAP_CRC32_HASH_FUNC
0856 #define VMXNET3_CAP_OAM_FILTER                     14   /* bit 14 of DCR 0 */
0857 #define VMXNET3_CAP_ESP_QS                         15   /* bit 15 of DCR 0 */
0858 #define VMXNET3_CAP_LARGE_BAR                      16   /* bit 16 of DCR 0 */
0859 #define VMXNET3_CAP_OOORX_COMP                     17   /* bit 17 of DCR 0 */
0860 #define VMXNET3_CAP_VERSION_7_MAX                  18
0861 /* when new capability is introduced, update VMXNET3_CAP_MAX */
0862 #define VMXNET3_CAP_MAX                            VMXNET3_CAP_VERSION_7_MAX
0863
0864 #endif /* _VMXNET3_DEFS_H_ */