net/usb/smsc95xx.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002  /***************************************************************************
0003  *
0004  * Copyright (C) 2007-2008 SMSC
0005  *
0006  *****************************************************************************/
0007
0008 #ifndef _SMSC95XX_H
0009 #define _SMSC95XX_H
0010
0011 /* Tx command words */
0012 #define TX_CMD_A_DATA_OFFSET_   (0x001F0000)    /* Data Start Offset */
0013 #define TX_CMD_A_FIRST_SEG_ (0x00002000)    /* First Segment */
0014 #define TX_CMD_A_LAST_SEG_  (0x00001000)    /* Last Segment */
0015 #define TX_CMD_A_BUF_SIZE_  (0x000007FF)    /* Buffer Size */
0016
0017 #define TX_CMD_B_CSUM_ENABLE    (0x00004000)    /* TX Checksum Enable */
0018 #define TX_CMD_B_ADD_CRC_DIS_   (0x00002000)    /* Add CRC Disable */
0019 #define TX_CMD_B_DIS_PADDING_   (0x00001000)    /* Disable Frame Padding */
0020 #define TX_CMD_B_FRAME_LENGTH_  (0x000007FF)    /* Frame Length (bytes) */
0021
0022 /* Rx status word */
0023 #define RX_STS_FF_      (0x40000000)    /* Filter Fail */
0024 #define RX_STS_FL_      (0x3FFF0000)    /* Frame Length */
0025 #define RX_STS_ES_      (0x00008000)    /* Error Summary */
0026 #define RX_STS_BF_      (0x00002000)    /* Broadcast Frame */
0027 #define RX_STS_LE_      (0x00001000)    /* Length Error */
0028 #define RX_STS_RF_      (0x00000800)    /* Runt Frame */
0029 #define RX_STS_MF_      (0x00000400)    /* Multicast Frame */
0030 #define RX_STS_TL_      (0x00000080)    /* Frame too long */
0031 #define RX_STS_CS_      (0x00000040)    /* Collision Seen */
0032 #define RX_STS_FT_      (0x00000020)    /* Frame Type */
0033 #define RX_STS_RW_      (0x00000010)    /* Receive Watchdog */
0034 #define RX_STS_ME_      (0x00000008)    /* MII Error */
0035 #define RX_STS_DB_      (0x00000004)    /* Dribbling */
0036 #define RX_STS_CRC_     (0x00000002)    /* CRC Error */
0037
0038 /* SCSRs - System Control and Status Registers */
0039 /* Device ID and Revision Register */
0040 #define ID_REV          (0x00)
0041 #define ID_REV_CHIP_ID_MASK_    (0xFFFF0000)
0042 #define ID_REV_CHIP_REV_MASK_   (0x0000FFFF)
0043 #define ID_REV_CHIP_ID_9500_    (0x9500)
0044 #define ID_REV_CHIP_ID_9500A_   (0x9E00)
0045 #define ID_REV_CHIP_ID_9512_    (0xEC00)
0046 #define ID_REV_CHIP_ID_9530_    (0x9530)
0047 #define ID_REV_CHIP_ID_89530_   (0x9E08)
0048 #define ID_REV_CHIP_ID_9730_    (0x9730)
0049
0050 /* Interrupt Status Register */
0051 #define INT_STS         (0x08)
0052 #define INT_STS_MAC_RTO_    (0x00040000)    /* MAC Reset Time Out */
0053 #define INT_STS_TX_STOP_    (0x00020000)    /* TX Stopped */
0054 #define INT_STS_RX_STOP_    (0x00010000)    /* RX Stopped */
0055 #define INT_STS_PHY_INT_    (0x00008000)    /* PHY Interrupt */
0056 #define INT_STS_TXE_        (0x00004000)    /* Transmitter Error */
0057 #define INT_STS_TDFU_       (0x00002000)    /* TX Data FIFO Underrun */
0058 #define INT_STS_TDFO_       (0x00001000)    /* TX Data FIFO Overrun */
0059 #define INT_STS_RXDF_       (0x00000800)    /* RX Dropped Frame */
0060 #define INT_STS_GPIOS_      (0x000007FF)    /* GPIOs Interrupts */
0061 #define INT_STS_CLEAR_ALL_  (0xFFFFFFFF)
0062
0063 /* Receive Configuration Register */
0064 #define RX_CFG          (0x0C)
0065 #define RX_FIFO_FLUSH_      (0x00000001)    /* Receive FIFO Flush */
0066
0067 /* Transmit Configuration Register */
0068 #define TX_CFG          (0x10)
0069 #define TX_CFG_ON_      (0x00000004)    /* Transmitter Enable */
0070 #define TX_CFG_STOP_        (0x00000002)    /* Stop Transmitter */
0071 #define TX_CFG_FIFO_FLUSH_  (0x00000001)    /* Transmit FIFO Flush */
0072
0073 /* Hardware Configuration Register */
0074 #define HW_CFG          (0x14)
0075 #define HW_CFG_BIR_     (0x00001000)    /* Bulk In Empty Response */
0076 #define HW_CFG_LEDB_        (0x00000800)    /* Activity LED 80ms Bypass */
0077 #define HW_CFG_RXDOFF_      (0x00000600)    /* RX Data Offset */
0078 #define HW_CFG_SBP_     (0x00000100)    /* Stall Bulk Out Pipe Dis. */
0079 #define HW_CFG_IME_     (0x00000080)    /* Internal MII Visi. Enable */
0080 #define HW_CFG_DRP_     (0x00000040)    /* Discard Errored RX Frame */
0081 #define HW_CFG_MEF_     (0x00000020)    /* Mult. ETH Frames/USB pkt */
0082 #define HW_CFG_ETC_     (0x00000010)    /* EEPROM Timeout Control */
0083 #define HW_CFG_LRST_        (0x00000008)    /* Soft Lite Reset */
0084 #define HW_CFG_PSEL_        (0x00000004)    /* External PHY Select */
0085 #define HW_CFG_BCE_     (0x00000002)    /* Burst Cap Enable */
0086 #define HW_CFG_SRST_        (0x00000001)    /* Soft Reset */
0087
0088 /* Receive FIFO Information Register */
0089 #define RX_FIFO_INF     (0x18)
0090 #define RX_FIFO_INF_USED_   (0x0000FFFF)    /* RX Data FIFO Used Space */
0091
0092 /* Transmit FIFO Information Register */
0093 #define TX_FIFO_INF     (0x1C)
0094 #define TX_FIFO_INF_FREE_   (0x0000FFFF)    /* TX Data FIFO Free Space */
0095
0096 /* Power Management Control Register */
0097 #define PM_CTRL         (0x20)
0098 #define PM_CTL_RES_CLR_WKP_STS  (0x00000200)    /* Resume Clears Wakeup STS */
0099 #define PM_CTL_RES_CLR_WKP_EN   (0x00000100)    /* Resume Clears Wkp Enables */
0100 #define PM_CTL_DEV_RDY_     (0x00000080)    /* Device Ready */
0101 #define PM_CTL_SUS_MODE_    (0x00000060)    /* Suspend Mode */
0102 #define PM_CTL_SUS_MODE_0   (0x00000000)
0103 #define PM_CTL_SUS_MODE_1   (0x00000020)
0104 #define PM_CTL_SUS_MODE_2   (0x00000040)
0105 #define PM_CTL_SUS_MODE_3   (0x00000060)
0106 #define PM_CTL_PHY_RST_     (0x00000010)    /* PHY Reset */
0107 #define PM_CTL_WOL_EN_      (0x00000008)    /* Wake On Lan Enable */
0108 #define PM_CTL_ED_EN_       (0x00000004)    /* Energy Detect Enable */
0109 #define PM_CTL_WUPS_        (0x00000003)    /* Wake Up Status */
0110 #define PM_CTL_WUPS_NO_     (0x00000000)    /* No Wake Up Event Detected */
0111 #define PM_CTL_WUPS_ED_     (0x00000001)    /* Energy Detect */
0112 #define PM_CTL_WUPS_WOL_    (0x00000002)    /* Wake On Lan */
0113 #define PM_CTL_WUPS_MULTI_  (0x00000003)    /* Multiple Events Occurred */
0114
0115 /* LED General Purpose IO Configuration Register */
0116 #define LED_GPIO_CFG        (0x24)
0117 #define LED_GPIO_CFG_SPD_LED    (0x01000000)    /* GPIOz as Speed LED */
0118 #define LED_GPIO_CFG_LNK_LED    (0x00100000)    /* GPIOy as Link LED */
0119 #define LED_GPIO_CFG_FDX_LED    (0x00010000)    /* GPIOx as Full Duplex LED */
0120
0121 /* General Purpose IO Configuration Register */
0122 #define GPIO_CFG        (0x28)
0123
0124 /* Automatic Flow Control Configuration Register */
0125 #define AFC_CFG         (0x2C)
0126 #define AFC_CFG_HI_     (0x00FF0000)    /* Auto Flow Ctrl High Level */
0127 #define AFC_CFG_LO_     (0x0000FF00)    /* Auto Flow Ctrl Low Level */
0128 #define AFC_CFG_BACK_DUR_   (0x000000F0)    /* Back Pressure Duration */
0129 #define AFC_CFG_FC_MULT_    (0x00000008)    /* Flow Ctrl on Mcast Frame */
0130 #define AFC_CFG_FC_BRD_     (0x00000004)    /* Flow Ctrl on Bcast Frame */
0131 #define AFC_CFG_FC_ADD_     (0x00000002)    /* Flow Ctrl on Addr. Decode */
0132 #define AFC_CFG_FC_ANY_     (0x00000001)    /* Flow Ctrl on Any Frame */
0133 /* Hi watermark = 15.5Kb (~10 mtu pkts) */
0134 /* low watermark = 3k (~2 mtu pkts) */
0135 /* backpressure duration = ~ 350us */
0136 /* Apply FC on any frame. */
0137 #define AFC_CFG_DEFAULT     (0x00F830A1)
0138
0139 /* EEPROM Command Register */
0140 #define E2P_CMD         (0x30)
0141 #define E2P_CMD_BUSY_       (0x80000000)    /* E2P Controller Busy */
0142 #define E2P_CMD_MASK_       (0x70000000)    /* Command Mask (see below) */
0143 #define E2P_CMD_READ_       (0x00000000)    /* Read Location */
0144 #define E2P_CMD_EWDS_       (0x10000000)    /* Erase/Write Disable */
0145 #define E2P_CMD_EWEN_       (0x20000000)    /* Erase/Write Enable */
0146 #define E2P_CMD_WRITE_      (0x30000000)    /* Write Location */
0147 #define E2P_CMD_WRAL_       (0x40000000)    /* Write All */
0148 #define E2P_CMD_ERASE_      (0x50000000)    /* Erase Location */
0149 #define E2P_CMD_ERAL_       (0x60000000)    /* Erase All */
0150 #define E2P_CMD_RELOAD_     (0x70000000)    /* Data Reload */
0151 #define E2P_CMD_TIMEOUT_    (0x00000400)    /* Set if no resp within 30ms */
0152 #define E2P_CMD_LOADED_     (0x00000200)    /* Valid EEPROM found */
0153 #define E2P_CMD_ADDR_       (0x000001FF)    /* Byte aligned address */
0154
0155 #define MAX_EEPROM_SIZE     (512)
0156
0157 /* EEPROM Data Register */
0158 #define E2P_DATA        (0x34)
0159 #define E2P_DATA_MASK_      (0x000000FF)    /* EEPROM Data Mask */
0160
0161 /* Burst Cap Register */
0162 #define BURST_CAP       (0x38)
0163 #define BURST_CAP_MASK_     (0x000000FF)    /* Max burst sent by the UTX */
0164
0165 /* Configuration Straps Status Register */
0166 #define STRAP_STATUS            (0x3C)
0167 #define STRAP_STATUS_PWR_SEL_       (0x00000020) /* Device self-powered */
0168 #define STRAP_STATUS_AMDIX_EN_      (0x00000010) /* Auto-MDIX Enabled */
0169 #define STRAP_STATUS_PORT_SWAP_     (0x00000008) /* USBD+/USBD- Swapped */
0170 #define STRAP_STATUS_EEP_SIZE_      (0x00000004) /* EEPROM Size */
0171 #define STRAP_STATUS_RMT_WKP_       (0x00000002) /* Remote Wkp supported */
0172 #define STRAP_STATUS_EEP_DISABLE_   (0x00000001) /* EEPROM Disabled */
0173
0174 /* Data Port Select Register */
0175 #define DP_SEL          (0x40)
0176
0177 /* Data Port Command Register */
0178 #define DP_CMD          (0x44)
0179
0180 /* Data Port Address Register */
0181 #define DP_ADDR         (0x48)
0182
0183 /* Data Port Data 0 Register */
0184 #define DP_DATA0        (0x4C)
0185
0186 /* Data Port Data 1 Register */
0187 #define DP_DATA1        (0x50)
0188
0189 /* General Purpose IO Wake Enable and Polarity Register */
0190 #define GPIO_WAKE       (0x64)
0191
0192 /* Interrupt Endpoint Control Register */
0193 #define INT_EP_CTL      (0x68)
0194 #define INT_EP_CTL_INTEP_   (0x80000000)    /* Always TX Interrupt PKT */
0195 #define INT_EP_CTL_MAC_RTO_ (0x00080000)    /* MAC Reset Time Out */
0196 #define INT_EP_CTL_RX_FIFO_ (0x00040000)    /* RX FIFO Has Frame */
0197 #define INT_EP_CTL_TX_STOP_ (0x00020000)    /* TX Stopped */
0198 #define INT_EP_CTL_RX_STOP_ (0x00010000)    /* RX Stopped */
0199 #define INT_EP_CTL_PHY_INT_ (0x00008000)    /* PHY Interrupt */
0200 #define INT_EP_CTL_TXE_     (0x00004000)    /* TX Error */
0201 #define INT_EP_CTL_TDFU_    (0x00002000)    /* TX Data FIFO Underrun */
0202 #define INT_EP_CTL_TDFO_    (0x00001000)    /* TX Data FIFO Overrun */
0203 #define INT_EP_CTL_RXDF_    (0x00000800)    /* RX Dropped Frame */
0204 #define INT_EP_CTL_GPIOS_   (0x000007FF)    /* GPIOs Interrupt Enable */
0205
0206 /* Bulk In Delay Register (units of 16.667ns, until ~1092µs) */
0207 #define BULK_IN_DLY     (0x6C)
0208
0209 /* MAC CSRs - MAC Control and Status Registers */
0210 /* MAC Control Register */
0211 #define MAC_CR          (0x100)
0212 #define MAC_CR_RXALL_       (0x80000000)    /* Receive All Mode */
0213 #define MAC_CR_RCVOWN_      (0x00800000)    /* Disable Receive Own */
0214 #define MAC_CR_LOOPBK_      (0x00200000)    /* Loopback Operation Mode */
0215 #define MAC_CR_FDPX_        (0x00100000)    /* Full Duplex Mode */
0216 #define MAC_CR_MCPAS_       (0x00080000)    /* Pass All Multicast */
0217 #define MAC_CR_PRMS_        (0x00040000)    /* Promiscuous Mode */
0218 #define MAC_CR_INVFILT_     (0x00020000)    /* Inverse Filtering */
0219 #define MAC_CR_PASSBAD_     (0x00010000)    /* Pass Bad Frames */
0220 #define MAC_CR_HFILT_       (0x00008000)    /* Hash Only Filtering Mode */
0221 #define MAC_CR_HPFILT_      (0x00002000)    /* Hash/Perfect Filt. Mode */
0222 #define MAC_CR_LCOLL_       (0x00001000)    /* Late Collision Control */
0223 #define MAC_CR_BCAST_       (0x00000800)    /* Disable Broadcast Frames */
0224 #define MAC_CR_DISRTY_      (0x00000400)    /* Disable Retry */
0225 #define MAC_CR_PADSTR_      (0x00000100)    /* Automatic Pad Stripping */
0226 #define MAC_CR_BOLMT_MASK   (0x000000C0)    /* BackOff Limit */
0227 #define MAC_CR_DFCHK_       (0x00000020)    /* Deferral Check */
0228 #define MAC_CR_TXEN_        (0x00000008)    /* Transmitter Enable */
0229 #define MAC_CR_RXEN_        (0x00000004)    /* Receiver Enable */
0230
0231 /* MAC Address High Register */
0232 #define ADDRH           (0x104)
0233
0234 /* MAC Address Low Register */
0235 #define ADDRL           (0x108)
0236
0237 /* Multicast Hash Table High Register */
0238 #define HASHH           (0x10C)
0239
0240 /* Multicast Hash Table Low Register */
0241 #define HASHL           (0x110)
0242
0243 /* MII Access Register */
0244 #define MII_ADDR        (0x114)
0245 #define MII_WRITE_      (0x02)
0246 #define MII_BUSY_       (0x01)
0247 #define MII_READ_       (0x00) /* ~of MII Write bit */
0248
0249 /* MII Data Register */
0250 #define MII_DATA        (0x118)
0251
0252 /* Flow Control Register */
0253 #define FLOW            (0x11C)
0254 #define FLOW_FCPT_      (0xFFFF0000)    /* Pause Time */
0255 #define FLOW_FCPASS_        (0x00000004)    /* Pass Control Frames */
0256 #define FLOW_FCEN_      (0x00000002)    /* Flow Control Enable */
0257 #define FLOW_FCBSY_     (0x00000001)    /* Flow Control Busy */
0258
0259 /* VLAN1 Tag Register */
0260 #define VLAN1           (0x120)
0261
0262 /* VLAN2 Tag Register */
0263 #define VLAN2           (0x124)
0264
0265 /* Wake Up Frame Filter Register */
0266 #define WUFF            (0x128)
0267 #define LAN9500_WUFF_NUM    (4)
0268 #define LAN9500A_WUFF_NUM   (8)
0269
0270 /* Wake Up Control and Status Register */
0271 #define WUCSR           (0x12C)
0272 #define WUCSR_WFF_PTR_RST_  (0x80000000)    /* WFrame Filter Pointer Rst */
0273 #define WUCSR_GUE_      (0x00000200)    /* Global Unicast Enable */
0274 #define WUCSR_WUFR_     (0x00000040)    /* Wakeup Frame Received */
0275 #define WUCSR_MPR_      (0x00000020)    /* Magic Packet Received */
0276 #define WUCSR_WAKE_EN_      (0x00000004)    /* Wakeup Frame Enable */
0277 #define WUCSR_MPEN_     (0x00000002)    /* Magic Packet Enable */
0278
0279 /* Checksum Offload Engine Control Register */
0280 #define COE_CR          (0x130)
0281 #define Tx_COE_EN_      (0x00010000)    /* TX Csum Offload Enable */
0282 #define Rx_COE_MODE_        (0x00000002)    /* RX Csum Offload Mode */
0283 #define Rx_COE_EN_      (0x00000001)    /* RX Csum Offload Enable */
0284
0285 /* Vendor-specific PHY Definitions (via MII access) */
0286 /* EDPD NLP / crossover time configuration (LAN9500A only) */
0287 #define PHY_EDPD_CONFIG         (16)
0288 #define PHY_EDPD_CONFIG_TX_NLP_EN_  ((u16)0x8000)
0289 #define PHY_EDPD_CONFIG_TX_NLP_1000_    ((u16)0x0000)
0290 #define PHY_EDPD_CONFIG_TX_NLP_768_ ((u16)0x2000)
0291 #define PHY_EDPD_CONFIG_TX_NLP_512_ ((u16)0x4000)
0292 #define PHY_EDPD_CONFIG_TX_NLP_256_ ((u16)0x6000)
0293 #define PHY_EDPD_CONFIG_RX_1_NLP_   ((u16)0x1000)
0294 #define PHY_EDPD_CONFIG_RX_NLP_64_  ((u16)0x0000)
0295 #define PHY_EDPD_CONFIG_RX_NLP_256_ ((u16)0x0400)
0296 #define PHY_EDPD_CONFIG_RX_NLP_512_ ((u16)0x0800)
0297 #define PHY_EDPD_CONFIG_RX_NLP_1000_    ((u16)0x0C00)
0298 #define PHY_EDPD_CONFIG_EXT_CROSSOVER_  ((u16)0x0001)
0299 #define PHY_EDPD_CONFIG_DEFAULT     (PHY_EDPD_CONFIG_TX_NLP_EN_ | \
0300                      PHY_EDPD_CONFIG_TX_NLP_768_ | \
0301                      PHY_EDPD_CONFIG_RX_1_NLP_)
0302
0303 /* Mode Control/Status Register */
0304 #define PHY_MODE_CTRL_STS       (17)
0305 #define MODE_CTRL_STS_EDPWRDOWN_    ((u16)0x2000)
0306 #define MODE_CTRL_STS_ENERGYON_     ((u16)0x0002)
0307
0308 /* Control/Status Indication Register */
0309 #define SPECIAL_CTRL_STS        (27)
0310 #define SPECIAL_CTRL_STS_OVRRD_AMDIX_   ((u16)0x8000)
0311 #define SPECIAL_CTRL_STS_AMDIX_ENABLE_  ((u16)0x4000)
0312 #define SPECIAL_CTRL_STS_AMDIX_STATE_   ((u16)0x2000)
0313
0314 /* Interrupt Source Register */
0315 #define PHY_INT_SRC         (29)
0316 #define PHY_INT_SRC_ENERGY_ON_      ((u16)0x0080)
0317 #define PHY_INT_SRC_ANEG_COMP_      ((u16)0x0040)
0318 #define PHY_INT_SRC_REMOTE_FAULT_   ((u16)0x0020)
0319 #define PHY_INT_SRC_LINK_DOWN_      ((u16)0x0010)
0320
0321 /* Interrupt Mask Register */
0322 #define PHY_INT_MASK            (30)
0323 #define PHY_INT_MASK_ENERGY_ON_     ((u16)0x0080)
0324 #define PHY_INT_MASK_ANEG_COMP_     ((u16)0x0040)
0325 #define PHY_INT_MASK_REMOTE_FAULT_  ((u16)0x0020)
0326 #define PHY_INT_MASK_LINK_DOWN_     ((u16)0x0010)
0327 #define PHY_INT_MASK_DEFAULT_       (PHY_INT_MASK_ANEG_COMP_ | \
0328                      PHY_INT_MASK_LINK_DOWN_)
0329 /* PHY Special Control/Status Register */
0330 #define PHY_SPECIAL         (31)
0331 #define PHY_SPECIAL_SPD_        ((u16)0x001C)
0332 #define PHY_SPECIAL_SPD_10HALF_     ((u16)0x0004)
0333 #define PHY_SPECIAL_SPD_10FULL_     ((u16)0x0014)
0334 #define PHY_SPECIAL_SPD_100HALF_    ((u16)0x0008)
0335 #define PHY_SPECIAL_SPD_100FULL_    ((u16)0x0018)
0336
0337 /* USB Vendor Requests */
0338 #define USB_VENDOR_REQUEST_WRITE_REGISTER   0xA0
0339 #define USB_VENDOR_REQUEST_READ_REGISTER    0xA1
0340 #define USB_VENDOR_REQUEST_GET_STATS        0xA2
0341
0342 /* Interrupt Endpoint status word bitfields */
0343 #define INT_ENP_MAC_RTO_        ((u32)BIT(18))  /* MAC Reset Time Out */
0344 #define INT_ENP_TX_STOP_        ((u32)BIT(17))  /* TX Stopped */
0345 #define INT_ENP_RX_STOP_        ((u32)BIT(16))  /* RX Stopped */
0346 #define INT_ENP_PHY_INT_        ((u32)BIT(15))  /* PHY Interrupt */
0347 #define INT_ENP_TXE_            ((u32)BIT(14))  /* TX Error */
0348 #define INT_ENP_TDFU_           ((u32)BIT(13))  /* TX FIFO Underrun */
0349 #define INT_ENP_TDFO_           ((u32)BIT(12))  /* TX FIFO Overrun */
0350 #define INT_ENP_RXDF_           ((u32)BIT(11))  /* RX Dropped Frame */
0351
0352 #endif /* _SMSC95XX_H */