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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * ASIX AX8817X based USB 2.0 Ethernet Devices
0004  * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
0005  * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
0006  * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
0007  * Copyright (c) 2002-2003 TiVo Inc.
0008  */
0009 
0010 #ifndef _ASIX_H
0011 #define _ASIX_H
0012 
0013 // #define  DEBUG           // error path messages, extra info
0014 // #define  VERBOSE         // more; success messages
0015 
0016 #include <linux/module.h>
0017 #include <linux/kmod.h>
0018 #include <linux/netdevice.h>
0019 #include <linux/etherdevice.h>
0020 #include <linux/ethtool.h>
0021 #include <linux/workqueue.h>
0022 #include <linux/mii.h>
0023 #include <linux/usb.h>
0024 #include <linux/crc32.h>
0025 #include <linux/usb/usbnet.h>
0026 #include <linux/slab.h>
0027 #include <linux/if_vlan.h>
0028 #include <linux/phy.h>
0029 #include <net/selftests.h>
0030 
0031 #define DRIVER_VERSION "22-Dec-2011"
0032 #define DRIVER_NAME "asix"
0033 
0034 /* ASIX AX8817X based USB 2.0 Ethernet Devices */
0035 
0036 #define AX_CMD_SET_SW_MII       0x06
0037 #define AX_CMD_READ_MII_REG     0x07
0038 #define AX_CMD_WRITE_MII_REG        0x08
0039 #define AX_CMD_STATMNGSTS_REG       0x09
0040 #define AX_CMD_SET_HW_MII       0x0a
0041 #define AX_CMD_READ_EEPROM      0x0b
0042 #define AX_CMD_WRITE_EEPROM     0x0c
0043 #define AX_CMD_WRITE_ENABLE     0x0d
0044 #define AX_CMD_WRITE_DISABLE        0x0e
0045 #define AX_CMD_READ_RX_CTL      0x0f
0046 #define AX_CMD_WRITE_RX_CTL     0x10
0047 #define AX_CMD_READ_IPG012      0x11
0048 #define AX_CMD_WRITE_IPG0       0x12
0049 #define AX_CMD_WRITE_IPG1       0x13
0050 #define AX_CMD_READ_NODE_ID     0x13
0051 #define AX_CMD_WRITE_NODE_ID        0x14
0052 #define AX_CMD_WRITE_IPG2       0x14
0053 #define AX_CMD_WRITE_MULTI_FILTER   0x16
0054 #define AX88172_CMD_READ_NODE_ID    0x17
0055 #define AX_CMD_READ_PHY_ID      0x19
0056 #define AX_CMD_READ_MEDIUM_STATUS   0x1a
0057 #define AX_CMD_WRITE_MEDIUM_MODE    0x1b
0058 #define AX_CMD_READ_MONITOR_MODE    0x1c
0059 #define AX_CMD_WRITE_MONITOR_MODE   0x1d
0060 #define AX_CMD_READ_GPIOS       0x1e
0061 #define AX_CMD_WRITE_GPIOS      0x1f
0062 #define AX_CMD_SW_RESET         0x20
0063 #define AX_CMD_SW_PHY_STATUS        0x21
0064 #define AX_CMD_SW_PHY_SELECT        0x22
0065 #define AX_QCTCTRL          0x2A
0066 
0067 #define AX_CHIPCODE_MASK        0x70
0068 #define AX_AX88772_CHIPCODE     0x00
0069 #define AX_AX88772A_CHIPCODE        0x10
0070 #define AX_AX88772B_CHIPCODE        0x20
0071 #define AX_HOST_EN          0x01
0072 
0073 #define AX_PHYSEL_PSEL          0x01
0074 #define AX_PHYSEL_SSMII         0
0075 #define AX_PHYSEL_SSEN          0x10
0076 
0077 #define AX_PHY_SELECT_MASK      (BIT(3) | BIT(2))
0078 #define AX_PHY_SELECT_INTERNAL      0
0079 #define AX_PHY_SELECT_EXTERNAL      BIT(2)
0080 
0081 #define AX_MONITOR_MODE         0x01
0082 #define AX_MONITOR_LINK         0x02
0083 #define AX_MONITOR_MAGIC        0x04
0084 #define AX_MONITOR_HSFS         0x10
0085 
0086 /* AX88172 Medium Status Register values */
0087 #define AX88172_MEDIUM_FD       0x02
0088 #define AX88172_MEDIUM_TX       0x04
0089 #define AX88172_MEDIUM_FC       0x10
0090 #define AX88172_MEDIUM_DEFAULT \
0091         ( AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC )
0092 
0093 #define AX_MCAST_FILTER_SIZE        8
0094 #define AX_MAX_MCAST            64
0095 
0096 #define AX_SWRESET_CLEAR        0x00
0097 #define AX_SWRESET_RR           0x01
0098 #define AX_SWRESET_RT           0x02
0099 #define AX_SWRESET_PRTE         0x04
0100 #define AX_SWRESET_PRL          0x08
0101 #define AX_SWRESET_BZ           0x10
0102 #define AX_SWRESET_IPRL         0x20
0103 #define AX_SWRESET_IPPD         0x40
0104 
0105 #define AX88772_IPG0_DEFAULT        0x15
0106 #define AX88772_IPG1_DEFAULT        0x0c
0107 #define AX88772_IPG2_DEFAULT        0x12
0108 
0109 /* AX88772 & AX88178 Medium Mode Register */
0110 #define AX_MEDIUM_PF        0x0080
0111 #define AX_MEDIUM_JFE       0x0040
0112 #define AX_MEDIUM_TFC       0x0020
0113 #define AX_MEDIUM_RFC       0x0010
0114 #define AX_MEDIUM_ENCK      0x0008
0115 #define AX_MEDIUM_AC        0x0004
0116 #define AX_MEDIUM_FD        0x0002
0117 #define AX_MEDIUM_GM        0x0001
0118 #define AX_MEDIUM_SM        0x1000
0119 #define AX_MEDIUM_SBP       0x0800
0120 #define AX_MEDIUM_PS        0x0200
0121 #define AX_MEDIUM_RE        0x0100
0122 
0123 #define AX88178_MEDIUM_DEFAULT  \
0124     (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \
0125      AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \
0126      AX_MEDIUM_RE)
0127 
0128 #define AX88772_MEDIUM_DEFAULT  \
0129     (AX_MEDIUM_FD | AX_MEDIUM_PS | \
0130      AX_MEDIUM_AC | AX_MEDIUM_RE)
0131 
0132 /* AX88772 & AX88178 RX_CTL values */
0133 #define AX_RX_CTL_SO        0x0080
0134 #define AX_RX_CTL_AP        0x0020
0135 #define AX_RX_CTL_AM        0x0010
0136 #define AX_RX_CTL_AB        0x0008
0137 #define AX_RX_CTL_SEP       0x0004
0138 #define AX_RX_CTL_AMALL     0x0002
0139 #define AX_RX_CTL_PRO       0x0001
0140 #define AX_RX_CTL_MFB_2048  0x0000
0141 #define AX_RX_CTL_MFB_4096  0x0100
0142 #define AX_RX_CTL_MFB_8192  0x0200
0143 #define AX_RX_CTL_MFB_16384 0x0300
0144 
0145 #define AX_DEFAULT_RX_CTL   (AX_RX_CTL_SO | AX_RX_CTL_AB)
0146 
0147 /* GPIO 0 .. 2 toggles */
0148 #define AX_GPIO_GPO0EN      0x01    /* GPIO0 Output enable */
0149 #define AX_GPIO_GPO_0       0x02    /* GPIO0 Output value */
0150 #define AX_GPIO_GPO1EN      0x04    /* GPIO1 Output enable */
0151 #define AX_GPIO_GPO_1       0x08    /* GPIO1 Output value */
0152 #define AX_GPIO_GPO2EN      0x10    /* GPIO2 Output enable */
0153 #define AX_GPIO_GPO_2       0x20    /* GPIO2 Output value */
0154 #define AX_GPIO_RESERVED    0x40    /* Reserved */
0155 #define AX_GPIO_RSE     0x80    /* Reload serial EEPROM */
0156 
0157 #define AX_EEPROM_MAGIC     0xdeadbeef
0158 #define AX_EEPROM_LEN       0x200
0159 
0160 #define AX_EMBD_PHY_ADDR    0x10
0161 
0162 /* This structure cannot exceed sizeof(unsigned long [5]) AKA 20 bytes */
0163 struct asix_data {
0164     u8 multi_filter[AX_MCAST_FILTER_SIZE];
0165     u8 mac_addr[ETH_ALEN];
0166     u8 phymode;
0167     u8 ledmode;
0168     u8 res;
0169 };
0170 
0171 struct asix_rx_fixup_info {
0172     struct sk_buff *ax_skb;
0173     u32 header;
0174     u16 remaining;
0175     bool split_head;
0176 };
0177 
0178 struct asix_common_private {
0179     void (*resume)(struct usbnet *dev);
0180     void (*suspend)(struct usbnet *dev);
0181     int (*reset)(struct usbnet *dev, int in_pm);
0182     u16 presvd_phy_advertise;
0183     u16 presvd_phy_bmcr;
0184     struct asix_rx_fixup_info rx_fixup_info;
0185     struct mii_bus *mdio;
0186     struct phy_device *phydev;
0187     struct phy_device *phydev_int;
0188     u16 phy_addr;
0189     bool embd_phy;
0190     u8 chipcode;
0191 };
0192 
0193 extern const struct driver_info ax88172a_info;
0194 
0195 /* ASIX specific flags */
0196 #define FLAG_EEPROM_MAC     (1UL << 0)  /* init device MAC from eeprom */
0197 
0198 int __must_check asix_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
0199                    u16 size, void *data, int in_pm);
0200 
0201 int asix_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
0202            u16 size, void *data, int in_pm);
0203 
0204 void asix_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
0205               u16 index, u16 size, void *data);
0206 
0207 int asix_rx_fixup_internal(struct usbnet *dev, struct sk_buff *skb,
0208                struct asix_rx_fixup_info *rx);
0209 int asix_rx_fixup_common(struct usbnet *dev, struct sk_buff *skb);
0210 void asix_rx_fixup_common_free(struct asix_common_private *dp);
0211 
0212 struct sk_buff *asix_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
0213                   gfp_t flags);
0214 
0215 int asix_read_phy_addr(struct usbnet *dev, bool internal);
0216 
0217 int asix_sw_reset(struct usbnet *dev, u8 flags, int in_pm);
0218 
0219 u16 asix_read_rx_ctl(struct usbnet *dev, int in_pm);
0220 int asix_write_rx_ctl(struct usbnet *dev, u16 mode, int in_pm);
0221 
0222 u16 asix_read_medium_status(struct usbnet *dev, int in_pm);
0223 int asix_write_medium_mode(struct usbnet *dev, u16 mode, int in_pm);
0224 void asix_adjust_link(struct net_device *netdev);
0225 
0226 int asix_write_gpio(struct usbnet *dev, u16 value, int sleep, int in_pm);
0227 
0228 void asix_set_multicast(struct net_device *net);
0229 
0230 int asix_mdio_read(struct net_device *netdev, int phy_id, int loc);
0231 void asix_mdio_write(struct net_device *netdev, int phy_id, int loc, int val);
0232 
0233 int asix_mdio_bus_read(struct mii_bus *bus, int phy_id, int regnum);
0234 int asix_mdio_bus_write(struct mii_bus *bus, int phy_id, int regnum, u16 val);
0235 
0236 int asix_mdio_read_nopm(struct net_device *netdev, int phy_id, int loc);
0237 void asix_mdio_write_nopm(struct net_device *netdev, int phy_id, int loc,
0238               int val);
0239 
0240 void asix_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
0241 int asix_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo);
0242 
0243 int asix_get_eeprom_len(struct net_device *net);
0244 int asix_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
0245             u8 *data);
0246 int asix_set_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
0247             u8 *data);
0248 
0249 void asix_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info);
0250 
0251 int asix_set_mac_address(struct net_device *net, void *p);
0252 
0253 #endif /* _ASIX_H */
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