net/phy/vitesse.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for Vitesse PHYs
0004  *
0005  * Author: Kriston Carson
0006  */
0007
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/mii.h>
0011 #include <linux/ethtool.h>
0012 #include <linux/phy.h>
0013
0014 /* Vitesse Extended Page Magic Register(s) */
0015 #define MII_VSC82X4_EXT_PAGE_16E    0x10
0016 #define MII_VSC82X4_EXT_PAGE_17E    0x11
0017 #define MII_VSC82X4_EXT_PAGE_18E    0x12
0018
0019 /* Vitesse Extended Control Register 1 */
0020 #define MII_VSC8244_EXT_CON1           0x17
0021 #define MII_VSC8244_EXTCON1_INIT       0x0000
0022 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK    0x0c00
0023 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK    0x0300
0024 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
0025 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
0026
0027 /* Vitesse Interrupt Mask Register */
0028 #define MII_VSC8244_IMASK       0x19
0029 #define MII_VSC8244_IMASK_IEN       0x8000
0030 #define MII_VSC8244_IMASK_SPEED     0x4000
0031 #define MII_VSC8244_IMASK_LINK      0x2000
0032 #define MII_VSC8244_IMASK_DUPLEX    0x1000
0033 #define MII_VSC8244_IMASK_MASK      0xf000
0034
0035 #define MII_VSC8221_IMASK_MASK      0xa000
0036
0037 /* Vitesse Interrupt Status Register */
0038 #define MII_VSC8244_ISTAT       0x1a
0039 #define MII_VSC8244_ISTAT_STATUS    0x8000
0040 #define MII_VSC8244_ISTAT_SPEED     0x4000
0041 #define MII_VSC8244_ISTAT_LINK      0x2000
0042 #define MII_VSC8244_ISTAT_DUPLEX    0x1000
0043 #define MII_VSC8244_ISTAT_MASK      (MII_VSC8244_ISTAT_SPEED | \
0044                      MII_VSC8244_ISTAT_LINK | \
0045                      MII_VSC8244_ISTAT_DUPLEX)
0046
0047 #define MII_VSC8221_ISTAT_MASK      MII_VSC8244_ISTAT_LINK
0048
0049 /* Vitesse Auxiliary Control/Status Register */
0050 #define MII_VSC8244_AUX_CONSTAT     0x1c
0051 #define MII_VSC8244_AUXCONSTAT_INIT 0x0000
0052 #define MII_VSC8244_AUXCONSTAT_DUPLEX   0x0020
0053 #define MII_VSC8244_AUXCONSTAT_SPEED    0x0018
0054 #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
0055 #define MII_VSC8244_AUXCONSTAT_100  0x0008
0056
0057 #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
0058 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
0059
0060 /* Vitesse Extended Page Access Register */
0061 #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
0062
0063 /* Vitesse VSC8601 Extended PHY Control Register 1 */
0064 #define MII_VSC8601_EPHY_CTL        0x17
0065 #define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
0066
0067 #define PHY_ID_VSC8234          0x000fc620
0068 #define PHY_ID_VSC8244          0x000fc6c0
0069 #define PHY_ID_VSC8572          0x000704d0
0070 #define PHY_ID_VSC8601          0x00070420
0071 #define PHY_ID_VSC7385          0x00070450
0072 #define PHY_ID_VSC7388          0x00070480
0073 #define PHY_ID_VSC7395          0x00070550
0074 #define PHY_ID_VSC7398          0x00070580
0075 #define PHY_ID_VSC8662          0x00070660
0076 #define PHY_ID_VSC8221          0x000fc550
0077 #define PHY_ID_VSC8211          0x000fc4b0
0078
0079 MODULE_DESCRIPTION("Vitesse PHY driver");
0080 MODULE_AUTHOR("Kriston Carson");
0081 MODULE_LICENSE("GPL");
0082
0083 static int vsc824x_add_skew(struct phy_device *phydev)
0084 {
0085     int err;
0086     int extcon;
0087
0088     extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
0089
0090     if (extcon < 0)
0091         return extcon;
0092
0093     extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
0094             MII_VSC8244_EXTCON1_RX_SKEW_MASK);
0095
0096     extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
0097             MII_VSC8244_EXTCON1_RX_SKEW);
0098
0099     err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
0100
0101     return err;
0102 }
0103
0104 static int vsc824x_config_init(struct phy_device *phydev)
0105 {
0106     int err;
0107
0108     err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
0109             MII_VSC8244_AUXCONSTAT_INIT);
0110     if (err < 0)
0111         return err;
0112
0113     if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
0114         err = vsc824x_add_skew(phydev);
0115
0116     return err;
0117 }
0118
0119 #define VSC73XX_EXT_PAGE_ACCESS 0x1f
0120
0121 static int vsc73xx_read_page(struct phy_device *phydev)
0122 {
0123     return __phy_read(phydev, VSC73XX_EXT_PAGE_ACCESS);
0124 }
0125
0126 static int vsc73xx_write_page(struct phy_device *phydev, int page)
0127 {
0128     return __phy_write(phydev, VSC73XX_EXT_PAGE_ACCESS, page);
0129 }
0130
0131 static void vsc73xx_config_init(struct phy_device *phydev)
0132 {
0133     /* Receiver init */
0134     phy_write(phydev, 0x1f, 0x2a30);
0135     phy_modify(phydev, 0x0c, 0x0300, 0x0200);
0136     phy_write(phydev, 0x1f, 0x0000);
0137
0138     /* Config LEDs 0x61 */
0139     phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061);
0140 }
0141
0142 static int vsc738x_config_init(struct phy_device *phydev)
0143 {
0144     u16 rev;
0145     /* This magic sequence appear in the application note
0146      * "VSC7385/7388 PHY Configuration".
0147      *
0148      * Maybe one day we will get to know what it all means.
0149      */
0150     phy_write(phydev, 0x1f, 0x2a30);
0151     phy_modify(phydev, 0x08, 0x0200, 0x0200);
0152     phy_write(phydev, 0x1f, 0x52b5);
0153     phy_write(phydev, 0x10, 0xb68a);
0154     phy_modify(phydev, 0x12, 0xff07, 0x0003);
0155     phy_modify(phydev, 0x11, 0x00ff, 0x00a2);
0156     phy_write(phydev, 0x10, 0x968a);
0157     phy_write(phydev, 0x1f, 0x2a30);
0158     phy_modify(phydev, 0x08, 0x0200, 0x0000);
0159     phy_write(phydev, 0x1f, 0x0000);
0160
0161     /* Read revision */
0162     rev = phy_read(phydev, MII_PHYSID2);
0163     rev &= 0x0f;
0164
0165     /* Special quirk for revision 0 */
0166     if (rev == 0) {
0167         phy_write(phydev, 0x1f, 0x2a30);
0168         phy_modify(phydev, 0x08, 0x0200, 0x0200);
0169         phy_write(phydev, 0x1f, 0x52b5);
0170         phy_write(phydev, 0x12, 0x0000);
0171         phy_write(phydev, 0x11, 0x0689);
0172         phy_write(phydev, 0x10, 0x8f92);
0173         phy_write(phydev, 0x1f, 0x52b5);
0174         phy_write(phydev, 0x12, 0x0000);
0175         phy_write(phydev, 0x11, 0x0e35);
0176         phy_write(phydev, 0x10, 0x9786);
0177         phy_write(phydev, 0x1f, 0x2a30);
0178         phy_modify(phydev, 0x08, 0x0200, 0x0000);
0179         phy_write(phydev, 0x17, 0xff80);
0180         phy_write(phydev, 0x17, 0x0000);
0181     }
0182
0183     phy_write(phydev, 0x1f, 0x0000);
0184     phy_write(phydev, 0x12, 0x0048);
0185
0186     if (rev == 0) {
0187         phy_write(phydev, 0x1f, 0x2a30);
0188         phy_write(phydev, 0x14, 0x6600);
0189         phy_write(phydev, 0x1f, 0x0000);
0190         phy_write(phydev, 0x18, 0xa24e);
0191     } else {
0192         phy_write(phydev, 0x1f, 0x2a30);
0193         phy_modify(phydev, 0x16, 0x0fc0, 0x0240);
0194         phy_modify(phydev, 0x14, 0x6000, 0x4000);
0195         /* bits 14-15 in extended register 0x14 controls DACG amplitude
0196          * 6 = -8%, 2 is hardware default
0197          */
0198         phy_write(phydev, 0x1f, 0x0001);
0199         phy_modify(phydev, 0x14, 0xe000, 0x6000);
0200         phy_write(phydev, 0x1f, 0x0000);
0201     }
0202
0203     vsc73xx_config_init(phydev);
0204
0205     return 0;
0206 }
0207
0208 static int vsc739x_config_init(struct phy_device *phydev)
0209 {
0210     /* This magic sequence appears in the VSC7395 SparX-G5e application
0211      * note "VSC7395/VSC7398 PHY Configuration"
0212      *
0213      * Maybe one day we will get to know what it all means.
0214      */
0215     phy_write(phydev, 0x1f, 0x2a30);
0216     phy_modify(phydev, 0x08, 0x0200, 0x0200);
0217     phy_write(phydev, 0x1f, 0x52b5);
0218     phy_write(phydev, 0x10, 0xb68a);
0219     phy_modify(phydev, 0x12, 0xff07, 0x0003);
0220     phy_modify(phydev, 0x11, 0x00ff, 0x00a2);
0221     phy_write(phydev, 0x10, 0x968a);
0222     phy_write(phydev, 0x1f, 0x2a30);
0223     phy_modify(phydev, 0x08, 0x0200, 0x0000);
0224     phy_write(phydev, 0x1f, 0x0000);
0225
0226     phy_write(phydev, 0x1f, 0x0000);
0227     phy_write(phydev, 0x12, 0x0048);
0228     phy_write(phydev, 0x1f, 0x2a30);
0229     phy_modify(phydev, 0x16, 0x0fc0, 0x0240);
0230     phy_modify(phydev, 0x14, 0x6000, 0x4000);
0231     phy_write(phydev, 0x1f, 0x0001);
0232     phy_modify(phydev, 0x14, 0xe000, 0x6000);
0233     phy_write(phydev, 0x1f, 0x0000);
0234
0235     vsc73xx_config_init(phydev);
0236
0237     return 0;
0238 }
0239
0240 static int vsc73xx_config_aneg(struct phy_device *phydev)
0241 {
0242     /* The VSC73xx switches does not like to be instructed to
0243      * do autonegotiation in any way, it prefers that you just go
0244      * with the power-on/reset defaults. Writing some registers will
0245      * just make autonegotiation permanently fail.
0246      */
0247     return 0;
0248 }
0249
0250 /* This adds a skew for both TX and RX clocks, so the skew should only be
0251  * applied to "rgmii-id" interfaces. It may not work as expected
0252  * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces.
0253  */
0254 static int vsc8601_add_skew(struct phy_device *phydev)
0255 {
0256     int ret;
0257
0258     ret = phy_read(phydev, MII_VSC8601_EPHY_CTL);
0259     if (ret < 0)
0260         return ret;
0261
0262     ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
0263     return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);
0264 }
0265
0266 static int vsc8601_config_init(struct phy_device *phydev)
0267 {
0268     int ret = 0;
0269
0270     if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
0271         ret = vsc8601_add_skew(phydev);
0272
0273     if (ret < 0)
0274         return ret;
0275
0276     return 0;
0277 }
0278
0279 static int vsc82xx_config_intr(struct phy_device *phydev)
0280 {
0281     int err;
0282
0283     if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
0284         /* Don't bother to ACK the interrupts since the 824x cannot
0285          * clear the interrupts if they are disabled.
0286          */
0287         err = phy_write(phydev, MII_VSC8244_IMASK,
0288             (phydev->drv->phy_id == PHY_ID_VSC8234 ||
0289              phydev->drv->phy_id == PHY_ID_VSC8244 ||
0290              phydev->drv->phy_id == PHY_ID_VSC8572 ||
0291              phydev->drv->phy_id == PHY_ID_VSC8601) ?
0292                 MII_VSC8244_IMASK_MASK :
0293                 MII_VSC8221_IMASK_MASK);
0294     else {
0295         /* The Vitesse PHY cannot clear the interrupt
0296          * once it has disabled them, so we clear them first
0297          */
0298         err = phy_read(phydev, MII_VSC8244_ISTAT);
0299
0300         if (err < 0)
0301             return err;
0302
0303         err = phy_write(phydev, MII_VSC8244_IMASK, 0);
0304     }
0305
0306     return err;
0307 }
0308
0309 static irqreturn_t vsc82xx_handle_interrupt(struct phy_device *phydev)
0310 {
0311     int irq_status, irq_mask;
0312
0313     if (phydev->drv->phy_id == PHY_ID_VSC8244 ||
0314         phydev->drv->phy_id == PHY_ID_VSC8572 ||
0315         phydev->drv->phy_id == PHY_ID_VSC8601)
0316         irq_mask = MII_VSC8244_ISTAT_MASK;
0317     else
0318         irq_mask = MII_VSC8221_ISTAT_MASK;
0319
0320     irq_status = phy_read(phydev, MII_VSC8244_ISTAT);
0321     if (irq_status < 0) {
0322         phy_error(phydev);
0323         return IRQ_NONE;
0324     }
0325
0326     if (!(irq_status & irq_mask))
0327         return IRQ_NONE;
0328
0329     phy_trigger_machine(phydev);
0330
0331     return IRQ_HANDLED;
0332 }
0333
0334 static int vsc8221_config_init(struct phy_device *phydev)
0335 {
0336     int err;
0337
0338     err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
0339             MII_VSC8221_AUXCONSTAT_INIT);
0340     return err;
0341
0342     /* Perhaps we should set EXT_CON1 based on the interface?
0343      * Options are 802.3Z SerDes or SGMII
0344      */
0345 }
0346
0347 /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
0348  * @phydev: target phy_device struct
0349  *
0350  * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
0351  * special values in the VSC8234/VSC8244 extended reserved registers
0352  */
0353 static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
0354 {
0355     int ret;
0356
0357     if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
0358         return 0;
0359
0360     /* map extended registers set 0x10 - 0x1e */
0361     ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
0362     if (ret >= 0)
0363         ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
0364     if (ret >= 0)
0365         ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
0366     if (ret >= 0)
0367         ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
0368     /* map standard registers set 0x10 - 0x1e */
0369     if (ret >= 0)
0370         ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
0371     else
0372         phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
0373
0374     return ret;
0375 }
0376
0377 /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
0378  * @phydev: target phy_device struct
0379  *
0380  * Description: If auto-negotiation is enabled, we configure the
0381  *   advertising, and then restart auto-negotiation.  If it is not
0382  *   enabled, then we write the BMCR and also start the auto
0383  *   MDI/MDI-X feature
0384  */
0385 static int vsc82x4_config_aneg(struct phy_device *phydev)
0386 {
0387     int ret;
0388
0389     /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
0390      * writing special values in the VSC8234 extended reserved registers
0391      */
0392     if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
0393         ret = genphy_setup_forced(phydev);
0394
0395         if (ret < 0) /* error */
0396             return ret;
0397
0398         return vsc82x4_config_autocross_enable(phydev);
0399     }
0400
0401     return genphy_config_aneg(phydev);
0402 }
0403
0404 /* Vitesse 82xx */
0405 static struct phy_driver vsc82xx_driver[] = {
0406 {
0407     .phy_id         = PHY_ID_VSC8234,
0408     .name           = "Vitesse VSC8234",
0409     .phy_id_mask    = 0x000ffff0,
0410     /* PHY_GBIT_FEATURES */
0411     .config_init    = &vsc824x_config_init,
0412     .config_aneg    = &vsc82x4_config_aneg,
0413     .config_intr    = &vsc82xx_config_intr,
0414     .handle_interrupt = &vsc82xx_handle_interrupt,
0415 }, {
0416     .phy_id     = PHY_ID_VSC8244,
0417     .name       = "Vitesse VSC8244",
0418     .phy_id_mask    = 0x000fffc0,
0419     /* PHY_GBIT_FEATURES */
0420     .config_init    = &vsc824x_config_init,
0421     .config_aneg    = &vsc82x4_config_aneg,
0422     .config_intr    = &vsc82xx_config_intr,
0423     .handle_interrupt = &vsc82xx_handle_interrupt,
0424 }, {
0425     .phy_id         = PHY_ID_VSC8572,
0426     .name           = "Vitesse VSC8572",
0427     .phy_id_mask    = 0x000ffff0,
0428     /* PHY_GBIT_FEATURES */
0429     .config_init    = &vsc824x_config_init,
0430     .config_aneg    = &vsc82x4_config_aneg,
0431     .config_intr    = &vsc82xx_config_intr,
0432     .handle_interrupt = &vsc82xx_handle_interrupt,
0433 }, {
0434     .phy_id         = PHY_ID_VSC8601,
0435     .name           = "Vitesse VSC8601",
0436     .phy_id_mask    = 0x000ffff0,
0437     /* PHY_GBIT_FEATURES */
0438     .config_init    = &vsc8601_config_init,
0439     .config_intr    = &vsc82xx_config_intr,
0440     .handle_interrupt = &vsc82xx_handle_interrupt,
0441 }, {
0442     .phy_id         = PHY_ID_VSC7385,
0443     .name           = "Vitesse VSC7385",
0444     .phy_id_mask    = 0x000ffff0,
0445     /* PHY_GBIT_FEATURES */
0446     .config_init    = vsc738x_config_init,
0447     .config_aneg    = vsc73xx_config_aneg,
0448     .read_page      = vsc73xx_read_page,
0449     .write_page     = vsc73xx_write_page,
0450 }, {
0451     .phy_id         = PHY_ID_VSC7388,
0452     .name           = "Vitesse VSC7388",
0453     .phy_id_mask    = 0x000ffff0,
0454     /* PHY_GBIT_FEATURES */
0455     .config_init    = vsc738x_config_init,
0456     .config_aneg    = vsc73xx_config_aneg,
0457     .read_page      = vsc73xx_read_page,
0458     .write_page     = vsc73xx_write_page,
0459 }, {
0460     .phy_id         = PHY_ID_VSC7395,
0461     .name           = "Vitesse VSC7395",
0462     .phy_id_mask    = 0x000ffff0,
0463     /* PHY_GBIT_FEATURES */
0464     .config_init    = vsc739x_config_init,
0465     .config_aneg    = vsc73xx_config_aneg,
0466     .read_page      = vsc73xx_read_page,
0467     .write_page     = vsc73xx_write_page,
0468 }, {
0469     .phy_id         = PHY_ID_VSC7398,
0470     .name           = "Vitesse VSC7398",
0471     .phy_id_mask    = 0x000ffff0,
0472     /* PHY_GBIT_FEATURES */
0473     .config_init    = vsc739x_config_init,
0474     .config_aneg    = vsc73xx_config_aneg,
0475     .read_page      = vsc73xx_read_page,
0476     .write_page     = vsc73xx_write_page,
0477 }, {
0478     .phy_id         = PHY_ID_VSC8662,
0479     .name           = "Vitesse VSC8662",
0480     .phy_id_mask    = 0x000ffff0,
0481     /* PHY_GBIT_FEATURES */
0482     .config_init    = &vsc824x_config_init,
0483     .config_aneg    = &vsc82x4_config_aneg,
0484     .config_intr    = &vsc82xx_config_intr,
0485     .handle_interrupt = &vsc82xx_handle_interrupt,
0486 }, {
0487     /* Vitesse 8221 */
0488     .phy_id     = PHY_ID_VSC8221,
0489     .phy_id_mask    = 0x000ffff0,
0490     .name       = "Vitesse VSC8221",
0491     /* PHY_GBIT_FEATURES */
0492     .config_init    = &vsc8221_config_init,
0493     .config_intr    = &vsc82xx_config_intr,
0494     .handle_interrupt = &vsc82xx_handle_interrupt,
0495 }, {
0496     /* Vitesse 8211 */
0497     .phy_id     = PHY_ID_VSC8211,
0498     .phy_id_mask    = 0x000ffff0,
0499     .name       = "Vitesse VSC8211",
0500     /* PHY_GBIT_FEATURES */
0501     .config_init    = &vsc8221_config_init,
0502     .config_intr    = &vsc82xx_config_intr,
0503     .handle_interrupt = &vsc82xx_handle_interrupt,
0504 } };
0505
0506 module_phy_driver(vsc82xx_driver);
0507
0508 static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
0509     { PHY_ID_VSC8234, 0x000ffff0 },
0510     { PHY_ID_VSC8244, 0x000fffc0 },
0511     { PHY_ID_VSC8572, 0x000ffff0 },
0512     { PHY_ID_VSC7385, 0x000ffff0 },
0513     { PHY_ID_VSC7388, 0x000ffff0 },
0514     { PHY_ID_VSC7395, 0x000ffff0 },
0515     { PHY_ID_VSC7398, 0x000ffff0 },
0516     { PHY_ID_VSC8662, 0x000ffff0 },
0517     { PHY_ID_VSC8221, 0x000ffff0 },
0518     { PHY_ID_VSC8211, 0x000ffff0 },
0519     { }
0520 };
0521
0522 MODULE_DEVICE_TABLE(mdio, vitesse_tbl);