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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* drivers/net/phy/realtek.c
0003  *
0004  * Driver for Realtek PHYs
0005  *
0006  * Author: Johnson Leung <r58129@freescale.com>
0007  *
0008  * Copyright (c) 2004 Freescale Semiconductor, Inc.
0009  */
0010 #include <linux/bitops.h>
0011 #include <linux/of.h>
0012 #include <linux/phy.h>
0013 #include <linux/module.h>
0014 #include <linux/delay.h>
0015 
0016 #define RTL821x_PHYSR               0x11
0017 #define RTL821x_PHYSR_DUPLEX            BIT(13)
0018 #define RTL821x_PHYSR_SPEED         GENMASK(15, 14)
0019 
0020 #define RTL821x_INER                0x12
0021 #define RTL8211B_INER_INIT          0x6400
0022 #define RTL8211E_INER_LINK_STATUS       BIT(10)
0023 #define RTL8211F_INER_LINK_STATUS       BIT(4)
0024 
0025 #define RTL821x_INSR                0x13
0026 
0027 #define RTL821x_EXT_PAGE_SELECT         0x1e
0028 #define RTL821x_PAGE_SELECT         0x1f
0029 
0030 #define RTL8211F_PHYCR1             0x18
0031 #define RTL8211F_PHYCR2             0x19
0032 #define RTL8211F_INSR               0x1d
0033 
0034 #define RTL8211F_TX_DELAY           BIT(8)
0035 #define RTL8211F_RX_DELAY           BIT(3)
0036 
0037 #define RTL8211F_ALDPS_PLL_OFF          BIT(1)
0038 #define RTL8211F_ALDPS_ENABLE           BIT(2)
0039 #define RTL8211F_ALDPS_XTAL_OFF         BIT(12)
0040 
0041 #define RTL8211E_CTRL_DELAY         BIT(13)
0042 #define RTL8211E_TX_DELAY           BIT(12)
0043 #define RTL8211E_RX_DELAY           BIT(11)
0044 
0045 #define RTL8211F_CLKOUT_EN          BIT(0)
0046 
0047 #define RTL8201F_ISR                0x1e
0048 #define RTL8201F_ISR_ANERR          BIT(15)
0049 #define RTL8201F_ISR_DUPLEX         BIT(13)
0050 #define RTL8201F_ISR_LINK           BIT(11)
0051 #define RTL8201F_ISR_MASK           (RTL8201F_ISR_ANERR | \
0052                          RTL8201F_ISR_DUPLEX | \
0053                          RTL8201F_ISR_LINK)
0054 #define RTL8201F_IER                0x13
0055 
0056 #define RTL8366RB_POWER_SAVE            0x15
0057 #define RTL8366RB_POWER_SAVE_ON         BIT(12)
0058 
0059 #define RTL_SUPPORTS_5000FULL           BIT(14)
0060 #define RTL_SUPPORTS_2500FULL           BIT(13)
0061 #define RTL_SUPPORTS_10000FULL          BIT(0)
0062 #define RTL_ADV_2500FULL            BIT(7)
0063 #define RTL_LPADV_10000FULL         BIT(11)
0064 #define RTL_LPADV_5000FULL          BIT(6)
0065 #define RTL_LPADV_2500FULL          BIT(5)
0066 
0067 #define RTL9000A_GINMR              0x14
0068 #define RTL9000A_GINMR_LINK_STATUS      BIT(4)
0069 
0070 #define RTLGEN_SPEED_MASK           0x0630
0071 
0072 #define RTL_GENERIC_PHYID           0x001cc800
0073 
0074 MODULE_DESCRIPTION("Realtek PHY driver");
0075 MODULE_AUTHOR("Johnson Leung");
0076 MODULE_LICENSE("GPL");
0077 
0078 struct rtl821x_priv {
0079     u16 phycr1;
0080     u16 phycr2;
0081 };
0082 
0083 static int rtl821x_read_page(struct phy_device *phydev)
0084 {
0085     return __phy_read(phydev, RTL821x_PAGE_SELECT);
0086 }
0087 
0088 static int rtl821x_write_page(struct phy_device *phydev, int page)
0089 {
0090     return __phy_write(phydev, RTL821x_PAGE_SELECT, page);
0091 }
0092 
0093 static int rtl821x_probe(struct phy_device *phydev)
0094 {
0095     struct device *dev = &phydev->mdio.dev;
0096     struct rtl821x_priv *priv;
0097     int ret;
0098 
0099     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0100     if (!priv)
0101         return -ENOMEM;
0102 
0103     ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR1);
0104     if (ret < 0)
0105         return ret;
0106 
0107     priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF);
0108     if (of_property_read_bool(dev->of_node, "realtek,aldps-enable"))
0109         priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF;
0110 
0111     ret = phy_read_paged(phydev, 0xa43, RTL8211F_PHYCR2);
0112     if (ret < 0)
0113         return ret;
0114 
0115     priv->phycr2 = ret & RTL8211F_CLKOUT_EN;
0116     if (of_property_read_bool(dev->of_node, "realtek,clkout-disable"))
0117         priv->phycr2 &= ~RTL8211F_CLKOUT_EN;
0118 
0119     phydev->priv = priv;
0120 
0121     return 0;
0122 }
0123 
0124 static int rtl8201_ack_interrupt(struct phy_device *phydev)
0125 {
0126     int err;
0127 
0128     err = phy_read(phydev, RTL8201F_ISR);
0129 
0130     return (err < 0) ? err : 0;
0131 }
0132 
0133 static int rtl821x_ack_interrupt(struct phy_device *phydev)
0134 {
0135     int err;
0136 
0137     err = phy_read(phydev, RTL821x_INSR);
0138 
0139     return (err < 0) ? err : 0;
0140 }
0141 
0142 static int rtl8211f_ack_interrupt(struct phy_device *phydev)
0143 {
0144     int err;
0145 
0146     err = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
0147 
0148     return (err < 0) ? err : 0;
0149 }
0150 
0151 static int rtl8201_config_intr(struct phy_device *phydev)
0152 {
0153     u16 val;
0154     int err;
0155 
0156     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0157         err = rtl8201_ack_interrupt(phydev);
0158         if (err)
0159             return err;
0160 
0161         val = BIT(13) | BIT(12) | BIT(11);
0162         err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
0163     } else {
0164         val = 0;
0165         err = phy_write_paged(phydev, 0x7, RTL8201F_IER, val);
0166         if (err)
0167             return err;
0168 
0169         err = rtl8201_ack_interrupt(phydev);
0170     }
0171 
0172     return err;
0173 }
0174 
0175 static int rtl8211b_config_intr(struct phy_device *phydev)
0176 {
0177     int err;
0178 
0179     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0180         err = rtl821x_ack_interrupt(phydev);
0181         if (err)
0182             return err;
0183 
0184         err = phy_write(phydev, RTL821x_INER,
0185                 RTL8211B_INER_INIT);
0186     } else {
0187         err = phy_write(phydev, RTL821x_INER, 0);
0188         if (err)
0189             return err;
0190 
0191         err = rtl821x_ack_interrupt(phydev);
0192     }
0193 
0194     return err;
0195 }
0196 
0197 static int rtl8211e_config_intr(struct phy_device *phydev)
0198 {
0199     int err;
0200 
0201     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0202         err = rtl821x_ack_interrupt(phydev);
0203         if (err)
0204             return err;
0205 
0206         err = phy_write(phydev, RTL821x_INER,
0207                 RTL8211E_INER_LINK_STATUS);
0208     } else {
0209         err = phy_write(phydev, RTL821x_INER, 0);
0210         if (err)
0211             return err;
0212 
0213         err = rtl821x_ack_interrupt(phydev);
0214     }
0215 
0216     return err;
0217 }
0218 
0219 static int rtl8211f_config_intr(struct phy_device *phydev)
0220 {
0221     u16 val;
0222     int err;
0223 
0224     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0225         err = rtl8211f_ack_interrupt(phydev);
0226         if (err)
0227             return err;
0228 
0229         val = RTL8211F_INER_LINK_STATUS;
0230         err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
0231     } else {
0232         val = 0;
0233         err = phy_write_paged(phydev, 0xa42, RTL821x_INER, val);
0234         if (err)
0235             return err;
0236 
0237         err = rtl8211f_ack_interrupt(phydev);
0238     }
0239 
0240     return err;
0241 }
0242 
0243 static irqreturn_t rtl8201_handle_interrupt(struct phy_device *phydev)
0244 {
0245     int irq_status;
0246 
0247     irq_status = phy_read(phydev, RTL8201F_ISR);
0248     if (irq_status < 0) {
0249         phy_error(phydev);
0250         return IRQ_NONE;
0251     }
0252 
0253     if (!(irq_status & RTL8201F_ISR_MASK))
0254         return IRQ_NONE;
0255 
0256     phy_trigger_machine(phydev);
0257 
0258     return IRQ_HANDLED;
0259 }
0260 
0261 static irqreturn_t rtl821x_handle_interrupt(struct phy_device *phydev)
0262 {
0263     int irq_status, irq_enabled;
0264 
0265     irq_status = phy_read(phydev, RTL821x_INSR);
0266     if (irq_status < 0) {
0267         phy_error(phydev);
0268         return IRQ_NONE;
0269     }
0270 
0271     irq_enabled = phy_read(phydev, RTL821x_INER);
0272     if (irq_enabled < 0) {
0273         phy_error(phydev);
0274         return IRQ_NONE;
0275     }
0276 
0277     if (!(irq_status & irq_enabled))
0278         return IRQ_NONE;
0279 
0280     phy_trigger_machine(phydev);
0281 
0282     return IRQ_HANDLED;
0283 }
0284 
0285 static irqreturn_t rtl8211f_handle_interrupt(struct phy_device *phydev)
0286 {
0287     int irq_status;
0288 
0289     irq_status = phy_read_paged(phydev, 0xa43, RTL8211F_INSR);
0290     if (irq_status < 0) {
0291         phy_error(phydev);
0292         return IRQ_NONE;
0293     }
0294 
0295     if (!(irq_status & RTL8211F_INER_LINK_STATUS))
0296         return IRQ_NONE;
0297 
0298     phy_trigger_machine(phydev);
0299 
0300     return IRQ_HANDLED;
0301 }
0302 
0303 static int rtl8211_config_aneg(struct phy_device *phydev)
0304 {
0305     int ret;
0306 
0307     ret = genphy_config_aneg(phydev);
0308     if (ret < 0)
0309         return ret;
0310 
0311     /* Quirk was copied from vendor driver. Unfortunately it includes no
0312      * description of the magic numbers.
0313      */
0314     if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) {
0315         phy_write(phydev, 0x17, 0x2138);
0316         phy_write(phydev, 0x0e, 0x0260);
0317     } else {
0318         phy_write(phydev, 0x17, 0x2108);
0319         phy_write(phydev, 0x0e, 0x0000);
0320     }
0321 
0322     return 0;
0323 }
0324 
0325 static int rtl8211c_config_init(struct phy_device *phydev)
0326 {
0327     /* RTL8211C has an issue when operating in Gigabit slave mode */
0328     return phy_set_bits(phydev, MII_CTRL1000,
0329                 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
0330 }
0331 
0332 static int rtl8211f_config_init(struct phy_device *phydev)
0333 {
0334     struct rtl821x_priv *priv = phydev->priv;
0335     struct device *dev = &phydev->mdio.dev;
0336     u16 val_txdly, val_rxdly;
0337     int ret;
0338 
0339     ret = phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1,
0340                        RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF,
0341                        priv->phycr1);
0342     if (ret < 0) {
0343         dev_err(dev, "aldps mode  configuration failed: %pe\n",
0344             ERR_PTR(ret));
0345         return ret;
0346     }
0347 
0348     switch (phydev->interface) {
0349     case PHY_INTERFACE_MODE_RGMII:
0350         val_txdly = 0;
0351         val_rxdly = 0;
0352         break;
0353 
0354     case PHY_INTERFACE_MODE_RGMII_RXID:
0355         val_txdly = 0;
0356         val_rxdly = RTL8211F_RX_DELAY;
0357         break;
0358 
0359     case PHY_INTERFACE_MODE_RGMII_TXID:
0360         val_txdly = RTL8211F_TX_DELAY;
0361         val_rxdly = 0;
0362         break;
0363 
0364     case PHY_INTERFACE_MODE_RGMII_ID:
0365         val_txdly = RTL8211F_TX_DELAY;
0366         val_rxdly = RTL8211F_RX_DELAY;
0367         break;
0368 
0369     default: /* the rest of the modes imply leaving delay as is. */
0370         return 0;
0371     }
0372 
0373     ret = phy_modify_paged_changed(phydev, 0xd08, 0x11, RTL8211F_TX_DELAY,
0374                        val_txdly);
0375     if (ret < 0) {
0376         dev_err(dev, "Failed to update the TX delay register\n");
0377         return ret;
0378     } else if (ret) {
0379         dev_dbg(dev,
0380             "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n",
0381             val_txdly ? "Enabling" : "Disabling");
0382     } else {
0383         dev_dbg(dev,
0384             "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n",
0385             val_txdly ? "enabled" : "disabled");
0386     }
0387 
0388     ret = phy_modify_paged_changed(phydev, 0xd08, 0x15, RTL8211F_RX_DELAY,
0389                        val_rxdly);
0390     if (ret < 0) {
0391         dev_err(dev, "Failed to update the RX delay register\n");
0392         return ret;
0393     } else if (ret) {
0394         dev_dbg(dev,
0395             "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n",
0396             val_rxdly ? "Enabling" : "Disabling");
0397     } else {
0398         dev_dbg(dev,
0399             "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n",
0400             val_rxdly ? "enabled" : "disabled");
0401     }
0402 
0403     ret = phy_modify_paged(phydev, 0xa43, RTL8211F_PHYCR2,
0404                    RTL8211F_CLKOUT_EN, priv->phycr2);
0405     if (ret < 0) {
0406         dev_err(dev, "clkout configuration failed: %pe\n",
0407             ERR_PTR(ret));
0408         return ret;
0409     }
0410 
0411     return genphy_soft_reset(phydev);
0412 }
0413 
0414 static int rtl821x_resume(struct phy_device *phydev)
0415 {
0416     int ret;
0417 
0418     ret = genphy_resume(phydev);
0419     if (ret < 0)
0420         return ret;
0421 
0422     msleep(20);
0423 
0424     return 0;
0425 }
0426 
0427 static int rtl8211e_config_init(struct phy_device *phydev)
0428 {
0429     int ret = 0, oldpage;
0430     u16 val;
0431 
0432     /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */
0433     switch (phydev->interface) {
0434     case PHY_INTERFACE_MODE_RGMII:
0435         val = RTL8211E_CTRL_DELAY | 0;
0436         break;
0437     case PHY_INTERFACE_MODE_RGMII_ID:
0438         val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY;
0439         break;
0440     case PHY_INTERFACE_MODE_RGMII_RXID:
0441         val = RTL8211E_CTRL_DELAY | RTL8211E_RX_DELAY;
0442         break;
0443     case PHY_INTERFACE_MODE_RGMII_TXID:
0444         val = RTL8211E_CTRL_DELAY | RTL8211E_TX_DELAY;
0445         break;
0446     default: /* the rest of the modes imply leaving delays as is. */
0447         return 0;
0448     }
0449 
0450     /* According to a sample driver there is a 0x1c config register on the
0451      * 0xa4 extension page (0x7) layout. It can be used to disable/enable
0452      * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins.
0453      * The configuration register definition:
0454      * 14 = reserved
0455      * 13 = Force Tx RX Delay controlled by bit12 bit11,
0456      * 12 = RX Delay, 11 = TX Delay
0457      * 10:0 = Test && debug settings reserved by realtek
0458      */
0459     oldpage = phy_select_page(phydev, 0x7);
0460     if (oldpage < 0)
0461         goto err_restore_page;
0462 
0463     ret = __phy_write(phydev, RTL821x_EXT_PAGE_SELECT, 0xa4);
0464     if (ret)
0465         goto err_restore_page;
0466 
0467     ret = __phy_modify(phydev, 0x1c, RTL8211E_CTRL_DELAY
0468                | RTL8211E_TX_DELAY | RTL8211E_RX_DELAY,
0469                val);
0470 
0471 err_restore_page:
0472     return phy_restore_page(phydev, oldpage, ret);
0473 }
0474 
0475 static int rtl8211b_suspend(struct phy_device *phydev)
0476 {
0477     phy_write(phydev, MII_MMD_DATA, BIT(9));
0478 
0479     return genphy_suspend(phydev);
0480 }
0481 
0482 static int rtl8211b_resume(struct phy_device *phydev)
0483 {
0484     phy_write(phydev, MII_MMD_DATA, 0);
0485 
0486     return genphy_resume(phydev);
0487 }
0488 
0489 static int rtl8366rb_config_init(struct phy_device *phydev)
0490 {
0491     int ret;
0492 
0493     ret = phy_set_bits(phydev, RTL8366RB_POWER_SAVE,
0494                RTL8366RB_POWER_SAVE_ON);
0495     if (ret) {
0496         dev_err(&phydev->mdio.dev,
0497             "error enabling power management\n");
0498     }
0499 
0500     return ret;
0501 }
0502 
0503 /* get actual speed to cover the downshift case */
0504 static int rtlgen_get_speed(struct phy_device *phydev)
0505 {
0506     int val;
0507 
0508     if (!phydev->link)
0509         return 0;
0510 
0511     val = phy_read_paged(phydev, 0xa43, 0x12);
0512     if (val < 0)
0513         return val;
0514 
0515     switch (val & RTLGEN_SPEED_MASK) {
0516     case 0x0000:
0517         phydev->speed = SPEED_10;
0518         break;
0519     case 0x0010:
0520         phydev->speed = SPEED_100;
0521         break;
0522     case 0x0020:
0523         phydev->speed = SPEED_1000;
0524         break;
0525     case 0x0200:
0526         phydev->speed = SPEED_10000;
0527         break;
0528     case 0x0210:
0529         phydev->speed = SPEED_2500;
0530         break;
0531     case 0x0220:
0532         phydev->speed = SPEED_5000;
0533         break;
0534     default:
0535         break;
0536     }
0537 
0538     return 0;
0539 }
0540 
0541 static int rtlgen_read_status(struct phy_device *phydev)
0542 {
0543     int ret;
0544 
0545     ret = genphy_read_status(phydev);
0546     if (ret < 0)
0547         return ret;
0548 
0549     return rtlgen_get_speed(phydev);
0550 }
0551 
0552 static int rtlgen_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
0553 {
0554     int ret;
0555 
0556     if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE) {
0557         rtl821x_write_page(phydev, 0xa5c);
0558         ret = __phy_read(phydev, 0x12);
0559         rtl821x_write_page(phydev, 0);
0560     } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
0561         rtl821x_write_page(phydev, 0xa5d);
0562         ret = __phy_read(phydev, 0x10);
0563         rtl821x_write_page(phydev, 0);
0564     } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE) {
0565         rtl821x_write_page(phydev, 0xa5d);
0566         ret = __phy_read(phydev, 0x11);
0567         rtl821x_write_page(phydev, 0);
0568     } else {
0569         ret = -EOPNOTSUPP;
0570     }
0571 
0572     return ret;
0573 }
0574 
0575 static int rtlgen_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
0576                 u16 val)
0577 {
0578     int ret;
0579 
0580     if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV) {
0581         rtl821x_write_page(phydev, 0xa5d);
0582         ret = __phy_write(phydev, 0x10, val);
0583         rtl821x_write_page(phydev, 0);
0584     } else {
0585         ret = -EOPNOTSUPP;
0586     }
0587 
0588     return ret;
0589 }
0590 
0591 static int rtl822x_read_mmd(struct phy_device *phydev, int devnum, u16 regnum)
0592 {
0593     int ret = rtlgen_read_mmd(phydev, devnum, regnum);
0594 
0595     if (ret != -EOPNOTSUPP)
0596         return ret;
0597 
0598     if (devnum == MDIO_MMD_PCS && regnum == MDIO_PCS_EEE_ABLE2) {
0599         rtl821x_write_page(phydev, 0xa6e);
0600         ret = __phy_read(phydev, 0x16);
0601         rtl821x_write_page(phydev, 0);
0602     } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
0603         rtl821x_write_page(phydev, 0xa6d);
0604         ret = __phy_read(phydev, 0x12);
0605         rtl821x_write_page(phydev, 0);
0606     } else if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_LPABLE2) {
0607         rtl821x_write_page(phydev, 0xa6d);
0608         ret = __phy_read(phydev, 0x10);
0609         rtl821x_write_page(phydev, 0);
0610     }
0611 
0612     return ret;
0613 }
0614 
0615 static int rtl822x_write_mmd(struct phy_device *phydev, int devnum, u16 regnum,
0616                  u16 val)
0617 {
0618     int ret = rtlgen_write_mmd(phydev, devnum, regnum, val);
0619 
0620     if (ret != -EOPNOTSUPP)
0621         return ret;
0622 
0623     if (devnum == MDIO_MMD_AN && regnum == MDIO_AN_EEE_ADV2) {
0624         rtl821x_write_page(phydev, 0xa6d);
0625         ret = __phy_write(phydev, 0x12, val);
0626         rtl821x_write_page(phydev, 0);
0627     }
0628 
0629     return ret;
0630 }
0631 
0632 static int rtl822x_get_features(struct phy_device *phydev)
0633 {
0634     int val;
0635 
0636     val = phy_read_paged(phydev, 0xa61, 0x13);
0637     if (val < 0)
0638         return val;
0639 
0640     linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
0641              phydev->supported, val & RTL_SUPPORTS_2500FULL);
0642     linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
0643              phydev->supported, val & RTL_SUPPORTS_5000FULL);
0644     linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
0645              phydev->supported, val & RTL_SUPPORTS_10000FULL);
0646 
0647     return genphy_read_abilities(phydev);
0648 }
0649 
0650 static int rtl822x_config_aneg(struct phy_device *phydev)
0651 {
0652     int ret = 0;
0653 
0654     if (phydev->autoneg == AUTONEG_ENABLE) {
0655         u16 adv2500 = 0;
0656 
0657         if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
0658                       phydev->advertising))
0659             adv2500 = RTL_ADV_2500FULL;
0660 
0661         ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12,
0662                            RTL_ADV_2500FULL, adv2500);
0663         if (ret < 0)
0664             return ret;
0665     }
0666 
0667     return __genphy_config_aneg(phydev, ret);
0668 }
0669 
0670 static int rtl822x_read_status(struct phy_device *phydev)
0671 {
0672     int ret;
0673 
0674     if (phydev->autoneg == AUTONEG_ENABLE) {
0675         int lpadv = phy_read_paged(phydev, 0xa5d, 0x13);
0676 
0677         if (lpadv < 0)
0678             return lpadv;
0679 
0680         linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
0681             phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL);
0682         linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
0683             phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL);
0684         linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
0685             phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL);
0686     }
0687 
0688     ret = genphy_read_status(phydev);
0689     if (ret < 0)
0690         return ret;
0691 
0692     return rtlgen_get_speed(phydev);
0693 }
0694 
0695 static bool rtlgen_supports_2_5gbps(struct phy_device *phydev)
0696 {
0697     int val;
0698 
0699     phy_write(phydev, RTL821x_PAGE_SELECT, 0xa61);
0700     val = phy_read(phydev, 0x13);
0701     phy_write(phydev, RTL821x_PAGE_SELECT, 0);
0702 
0703     return val >= 0 && val & RTL_SUPPORTS_2500FULL;
0704 }
0705 
0706 static int rtlgen_match_phy_device(struct phy_device *phydev)
0707 {
0708     return phydev->phy_id == RTL_GENERIC_PHYID &&
0709            !rtlgen_supports_2_5gbps(phydev);
0710 }
0711 
0712 static int rtl8226_match_phy_device(struct phy_device *phydev)
0713 {
0714     return phydev->phy_id == RTL_GENERIC_PHYID &&
0715            rtlgen_supports_2_5gbps(phydev);
0716 }
0717 
0718 static int rtlgen_resume(struct phy_device *phydev)
0719 {
0720     int ret = genphy_resume(phydev);
0721 
0722     /* Internal PHY's from RTL8168h up may not be instantly ready */
0723     msleep(20);
0724 
0725     return ret;
0726 }
0727 
0728 static int rtl9000a_config_init(struct phy_device *phydev)
0729 {
0730     phydev->autoneg = AUTONEG_DISABLE;
0731     phydev->speed = SPEED_100;
0732     phydev->duplex = DUPLEX_FULL;
0733 
0734     return 0;
0735 }
0736 
0737 static int rtl9000a_config_aneg(struct phy_device *phydev)
0738 {
0739     int ret;
0740     u16 ctl = 0;
0741 
0742     switch (phydev->master_slave_set) {
0743     case MASTER_SLAVE_CFG_MASTER_FORCE:
0744         ctl |= CTL1000_AS_MASTER;
0745         break;
0746     case MASTER_SLAVE_CFG_SLAVE_FORCE:
0747         break;
0748     case MASTER_SLAVE_CFG_UNKNOWN:
0749     case MASTER_SLAVE_CFG_UNSUPPORTED:
0750         return 0;
0751     default:
0752         phydev_warn(phydev, "Unsupported Master/Slave mode\n");
0753         return -EOPNOTSUPP;
0754     }
0755 
0756     ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
0757     if (ret == 1)
0758         ret = genphy_soft_reset(phydev);
0759 
0760     return ret;
0761 }
0762 
0763 static int rtl9000a_read_status(struct phy_device *phydev)
0764 {
0765     int ret;
0766 
0767     phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
0768     phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN;
0769 
0770     ret = genphy_update_link(phydev);
0771     if (ret)
0772         return ret;
0773 
0774     ret = phy_read(phydev, MII_CTRL1000);
0775     if (ret < 0)
0776         return ret;
0777     if (ret & CTL1000_AS_MASTER)
0778         phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
0779     else
0780         phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
0781 
0782     ret = phy_read(phydev, MII_STAT1000);
0783     if (ret < 0)
0784         return ret;
0785     if (ret & LPA_1000MSRES)
0786         phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
0787     else
0788         phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
0789 
0790     return 0;
0791 }
0792 
0793 static int rtl9000a_ack_interrupt(struct phy_device *phydev)
0794 {
0795     int err;
0796 
0797     err = phy_read(phydev, RTL8211F_INSR);
0798 
0799     return (err < 0) ? err : 0;
0800 }
0801 
0802 static int rtl9000a_config_intr(struct phy_device *phydev)
0803 {
0804     u16 val;
0805     int err;
0806 
0807     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0808         err = rtl9000a_ack_interrupt(phydev);
0809         if (err)
0810             return err;
0811 
0812         val = (u16)~RTL9000A_GINMR_LINK_STATUS;
0813         err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
0814     } else {
0815         val = ~0;
0816         err = phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
0817         if (err)
0818             return err;
0819 
0820         err = rtl9000a_ack_interrupt(phydev);
0821     }
0822 
0823     return phy_write_paged(phydev, 0xa42, RTL9000A_GINMR, val);
0824 }
0825 
0826 static irqreturn_t rtl9000a_handle_interrupt(struct phy_device *phydev)
0827 {
0828     int irq_status;
0829 
0830     irq_status = phy_read(phydev, RTL8211F_INSR);
0831     if (irq_status < 0) {
0832         phy_error(phydev);
0833         return IRQ_NONE;
0834     }
0835 
0836     if (!(irq_status & RTL8211F_INER_LINK_STATUS))
0837         return IRQ_NONE;
0838 
0839     phy_trigger_machine(phydev);
0840 
0841     return IRQ_HANDLED;
0842 }
0843 
0844 static struct phy_driver realtek_drvs[] = {
0845     {
0846         PHY_ID_MATCH_EXACT(0x00008201),
0847         .name           = "RTL8201CP Ethernet",
0848         .read_page  = rtl821x_read_page,
0849         .write_page = rtl821x_write_page,
0850     }, {
0851         PHY_ID_MATCH_EXACT(0x001cc816),
0852         .name       = "RTL8201F Fast Ethernet",
0853         .config_intr    = &rtl8201_config_intr,
0854         .handle_interrupt = rtl8201_handle_interrupt,
0855         .suspend    = genphy_suspend,
0856         .resume     = genphy_resume,
0857         .read_page  = rtl821x_read_page,
0858         .write_page = rtl821x_write_page,
0859     }, {
0860         PHY_ID_MATCH_MODEL(0x001cc880),
0861         .name       = "RTL8208 Fast Ethernet",
0862         .read_mmd   = genphy_read_mmd_unsupported,
0863         .write_mmd  = genphy_write_mmd_unsupported,
0864         .suspend    = genphy_suspend,
0865         .resume     = genphy_resume,
0866         .read_page  = rtl821x_read_page,
0867         .write_page = rtl821x_write_page,
0868     }, {
0869         PHY_ID_MATCH_EXACT(0x001cc910),
0870         .name       = "RTL8211 Gigabit Ethernet",
0871         .config_aneg    = rtl8211_config_aneg,
0872         .read_mmd   = &genphy_read_mmd_unsupported,
0873         .write_mmd  = &genphy_write_mmd_unsupported,
0874         .read_page  = rtl821x_read_page,
0875         .write_page = rtl821x_write_page,
0876     }, {
0877         PHY_ID_MATCH_EXACT(0x001cc912),
0878         .name       = "RTL8211B Gigabit Ethernet",
0879         .config_intr    = &rtl8211b_config_intr,
0880         .handle_interrupt = rtl821x_handle_interrupt,
0881         .read_mmd   = &genphy_read_mmd_unsupported,
0882         .write_mmd  = &genphy_write_mmd_unsupported,
0883         .suspend    = rtl8211b_suspend,
0884         .resume     = rtl8211b_resume,
0885         .read_page  = rtl821x_read_page,
0886         .write_page = rtl821x_write_page,
0887     }, {
0888         PHY_ID_MATCH_EXACT(0x001cc913),
0889         .name       = "RTL8211C Gigabit Ethernet",
0890         .config_init    = rtl8211c_config_init,
0891         .read_mmd   = &genphy_read_mmd_unsupported,
0892         .write_mmd  = &genphy_write_mmd_unsupported,
0893         .read_page  = rtl821x_read_page,
0894         .write_page = rtl821x_write_page,
0895     }, {
0896         PHY_ID_MATCH_EXACT(0x001cc914),
0897         .name       = "RTL8211DN Gigabit Ethernet",
0898         .config_intr    = rtl8211e_config_intr,
0899         .handle_interrupt = rtl821x_handle_interrupt,
0900         .suspend    = genphy_suspend,
0901         .resume     = genphy_resume,
0902         .read_page  = rtl821x_read_page,
0903         .write_page = rtl821x_write_page,
0904     }, {
0905         PHY_ID_MATCH_EXACT(0x001cc915),
0906         .name       = "RTL8211E Gigabit Ethernet",
0907         .config_init    = &rtl8211e_config_init,
0908         .config_intr    = &rtl8211e_config_intr,
0909         .handle_interrupt = rtl821x_handle_interrupt,
0910         .suspend    = genphy_suspend,
0911         .resume     = genphy_resume,
0912         .read_page  = rtl821x_read_page,
0913         .write_page = rtl821x_write_page,
0914     }, {
0915         PHY_ID_MATCH_EXACT(0x001cc916),
0916         .name       = "RTL8211F Gigabit Ethernet",
0917         .probe      = rtl821x_probe,
0918         .config_init    = &rtl8211f_config_init,
0919         .read_status    = rtlgen_read_status,
0920         .config_intr    = &rtl8211f_config_intr,
0921         .handle_interrupt = rtl8211f_handle_interrupt,
0922         .suspend    = genphy_suspend,
0923         .resume     = rtl821x_resume,
0924         .read_page  = rtl821x_read_page,
0925         .write_page = rtl821x_write_page,
0926     }, {
0927         .name       = "Generic FE-GE Realtek PHY",
0928         .match_phy_device = rtlgen_match_phy_device,
0929         .read_status    = rtlgen_read_status,
0930         .suspend    = genphy_suspend,
0931         .resume     = rtlgen_resume,
0932         .read_page  = rtl821x_read_page,
0933         .write_page = rtl821x_write_page,
0934         .read_mmd   = rtlgen_read_mmd,
0935         .write_mmd  = rtlgen_write_mmd,
0936     }, {
0937         .name       = "RTL8226 2.5Gbps PHY",
0938         .match_phy_device = rtl8226_match_phy_device,
0939         .get_features   = rtl822x_get_features,
0940         .config_aneg    = rtl822x_config_aneg,
0941         .read_status    = rtl822x_read_status,
0942         .suspend    = genphy_suspend,
0943         .resume     = rtlgen_resume,
0944         .read_page  = rtl821x_read_page,
0945         .write_page = rtl821x_write_page,
0946         .read_mmd   = rtl822x_read_mmd,
0947         .write_mmd  = rtl822x_write_mmd,
0948     }, {
0949         PHY_ID_MATCH_EXACT(0x001cc840),
0950         .name       = "RTL8226B_RTL8221B 2.5Gbps PHY",
0951         .get_features   = rtl822x_get_features,
0952         .config_aneg    = rtl822x_config_aneg,
0953         .read_status    = rtl822x_read_status,
0954         .suspend    = genphy_suspend,
0955         .resume     = rtlgen_resume,
0956         .read_page  = rtl821x_read_page,
0957         .write_page = rtl821x_write_page,
0958         .read_mmd   = rtl822x_read_mmd,
0959         .write_mmd  = rtl822x_write_mmd,
0960     }, {
0961         PHY_ID_MATCH_EXACT(0x001cc838),
0962         .name           = "RTL8226-CG 2.5Gbps PHY",
0963         .get_features   = rtl822x_get_features,
0964         .config_aneg    = rtl822x_config_aneg,
0965         .read_status    = rtl822x_read_status,
0966         .suspend        = genphy_suspend,
0967         .resume         = rtlgen_resume,
0968         .read_page      = rtl821x_read_page,
0969         .write_page     = rtl821x_write_page,
0970     }, {
0971         PHY_ID_MATCH_EXACT(0x001cc848),
0972         .name           = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
0973         .get_features   = rtl822x_get_features,
0974         .config_aneg    = rtl822x_config_aneg,
0975         .read_status    = rtl822x_read_status,
0976         .suspend        = genphy_suspend,
0977         .resume         = rtlgen_resume,
0978         .read_page      = rtl821x_read_page,
0979         .write_page     = rtl821x_write_page,
0980     }, {
0981         PHY_ID_MATCH_EXACT(0x001cc849),
0982         .name           = "RTL8221B-VB-CG 2.5Gbps PHY",
0983         .get_features   = rtl822x_get_features,
0984         .config_aneg    = rtl822x_config_aneg,
0985         .read_status    = rtl822x_read_status,
0986         .suspend        = genphy_suspend,
0987         .resume         = rtlgen_resume,
0988         .read_page      = rtl821x_read_page,
0989         .write_page     = rtl821x_write_page,
0990     }, {
0991         PHY_ID_MATCH_EXACT(0x001cc84a),
0992         .name           = "RTL8221B-VM-CG 2.5Gbps PHY",
0993         .get_features   = rtl822x_get_features,
0994         .config_aneg    = rtl822x_config_aneg,
0995         .read_status    = rtl822x_read_status,
0996         .suspend        = genphy_suspend,
0997         .resume         = rtlgen_resume,
0998         .read_page      = rtl821x_read_page,
0999         .write_page     = rtl821x_write_page,
1000     }, {
1001         PHY_ID_MATCH_EXACT(0x001cc961),
1002         .name       = "RTL8366RB Gigabit Ethernet",
1003         .config_init    = &rtl8366rb_config_init,
1004         /* These interrupts are handled by the irq controller
1005          * embedded inside the RTL8366RB, they get unmasked when the
1006          * irq is requested and ACKed by reading the status register,
1007          * which is done by the irqchip code.
1008          */
1009         .config_intr    = genphy_no_config_intr,
1010         .handle_interrupt = genphy_handle_interrupt_no_ack,
1011         .suspend    = genphy_suspend,
1012         .resume     = genphy_resume,
1013     }, {
1014         PHY_ID_MATCH_EXACT(0x001ccb00),
1015         .name       = "RTL9000AA_RTL9000AN Ethernet",
1016         .features       = PHY_BASIC_T1_FEATURES,
1017         .config_init    = rtl9000a_config_init,
1018         .config_aneg    = rtl9000a_config_aneg,
1019         .read_status    = rtl9000a_read_status,
1020         .config_intr    = rtl9000a_config_intr,
1021         .handle_interrupt = rtl9000a_handle_interrupt,
1022         .suspend    = genphy_suspend,
1023         .resume     = genphy_resume,
1024         .read_page  = rtl821x_read_page,
1025         .write_page = rtl821x_write_page,
1026     }, {
1027         PHY_ID_MATCH_EXACT(0x001cc942),
1028         .name       = "RTL8365MB-VC Gigabit Ethernet",
1029         /* Interrupt handling analogous to RTL8366RB */
1030         .config_intr    = genphy_no_config_intr,
1031         .handle_interrupt = genphy_handle_interrupt_no_ack,
1032         .suspend    = genphy_suspend,
1033         .resume     = genphy_resume,
1034     },
1035 };
1036 
1037 module_phy_driver(realtek_drvs);
1038 
1039 static const struct mdio_device_id __maybe_unused realtek_tbl[] = {
1040     { PHY_ID_MATCH_VENDOR(0x001cc800) },
1041     { }
1042 };
1043 
1044 MODULE_DEVICE_TABLE(mdio, realtek_tbl);
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