net/phy/nxp-tja11xx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* NXP TJA1100 BroadRReach PHY driver
0003  *
0004  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
0005  */
0006 #include <linux/delay.h>
0007 #include <linux/ethtool.h>
0008 #include <linux/ethtool_netlink.h>
0009 #include <linux/kernel.h>
0010 #include <linux/mdio.h>
0011 #include <linux/mii.h>
0012 #include <linux/module.h>
0013 #include <linux/phy.h>
0014 #include <linux/hwmon.h>
0015 #include <linux/bitfield.h>
0016 #include <linux/of_mdio.h>
0017 #include <linux/of_irq.h>
0018
0019 #define PHY_ID_MASK         0xfffffff0
0020 #define PHY_ID_TJA1100          0x0180dc40
0021 #define PHY_ID_TJA1101          0x0180dd00
0022 #define PHY_ID_TJA1102          0x0180dc80
0023
0024 #define MII_ECTRL           17
0025 #define MII_ECTRL_LINK_CONTROL      BIT(15)
0026 #define MII_ECTRL_POWER_MODE_MASK   GENMASK(14, 11)
0027 #define MII_ECTRL_POWER_MODE_NO_CHANGE  (0x0 << 11)
0028 #define MII_ECTRL_POWER_MODE_NORMAL (0x3 << 11)
0029 #define MII_ECTRL_POWER_MODE_STANDBY    (0xc << 11)
0030 #define MII_ECTRL_CABLE_TEST        BIT(5)
0031 #define MII_ECTRL_CONFIG_EN     BIT(2)
0032 #define MII_ECTRL_WAKE_REQUEST      BIT(0)
0033
0034 #define MII_CFG1            18
0035 #define MII_CFG1_MASTER_SLAVE       BIT(15)
0036 #define MII_CFG1_AUTO_OP        BIT(14)
0037 #define MII_CFG1_SLEEP_CONFIRM      BIT(6)
0038 #define MII_CFG1_LED_MODE_MASK      GENMASK(5, 4)
0039 #define MII_CFG1_LED_MODE_LINKUP    0
0040 #define MII_CFG1_LED_ENABLE     BIT(3)
0041
0042 #define MII_CFG2            19
0043 #define MII_CFG2_SLEEP_REQUEST_TO   GENMASK(1, 0)
0044 #define MII_CFG2_SLEEP_REQUEST_TO_16MS  0x3
0045
0046 #define MII_INTSRC          21
0047 #define MII_INTSRC_LINK_FAIL        BIT(10)
0048 #define MII_INTSRC_LINK_UP      BIT(9)
0049 #define MII_INTSRC_MASK         (MII_INTSRC_LINK_FAIL | MII_INTSRC_LINK_UP)
0050 #define MII_INTSRC_UV_ERR       BIT(3)
0051 #define MII_INTSRC_TEMP_ERR     BIT(1)
0052
0053 #define MII_INTEN           22
0054 #define MII_INTEN_LINK_FAIL     BIT(10)
0055 #define MII_INTEN_LINK_UP       BIT(9)
0056 #define MII_INTEN_UV_ERR        BIT(3)
0057 #define MII_INTEN_TEMP_ERR      BIT(1)
0058
0059 #define MII_COMMSTAT            23
0060 #define MII_COMMSTAT_LINK_UP        BIT(15)
0061 #define MII_COMMSTAT_SQI_STATE      GENMASK(7, 5)
0062 #define MII_COMMSTAT_SQI_MAX        7
0063
0064 #define MII_GENSTAT         24
0065 #define MII_GENSTAT_PLL_LOCKED      BIT(14)
0066
0067 #define MII_EXTSTAT         25
0068 #define MII_EXTSTAT_SHORT_DETECT    BIT(8)
0069 #define MII_EXTSTAT_OPEN_DETECT     BIT(7)
0070 #define MII_EXTSTAT_POLARITY_DETECT BIT(6)
0071
0072 #define MII_COMMCFG         27
0073 #define MII_COMMCFG_AUTO_OP     BIT(15)
0074
0075 struct tja11xx_priv {
0076     char        *hwmon_name;
0077     struct device   *hwmon_dev;
0078     struct phy_device *phydev;
0079     struct work_struct phy_register_work;
0080 };
0081
0082 struct tja11xx_phy_stats {
0083     const char  *string;
0084     u8      reg;
0085     u8      off;
0086     u16     mask;
0087 };
0088
0089 static struct tja11xx_phy_stats tja11xx_hw_stats[] = {
0090     { "phy_symbol_error_count", 20, 0, GENMASK(15, 0) },
0091     { "phy_polarity_detect", 25, 6, BIT(6) },
0092     { "phy_open_detect", 25, 7, BIT(7) },
0093     { "phy_short_detect", 25, 8, BIT(8) },
0094     { "phy_rem_rcvr_count", 26, 0, GENMASK(7, 0) },
0095     { "phy_loc_rcvr_count", 26, 8, GENMASK(15, 8) },
0096 };
0097
0098 static int tja11xx_check(struct phy_device *phydev, u8 reg, u16 mask, u16 set)
0099 {
0100     int val;
0101
0102     return phy_read_poll_timeout(phydev, reg, val, (val & mask) == set,
0103                      150, 30000, false);
0104 }
0105
0106 static int phy_modify_check(struct phy_device *phydev, u8 reg,
0107                 u16 mask, u16 set)
0108 {
0109     int ret;
0110
0111     ret = phy_modify(phydev, reg, mask, set);
0112     if (ret)
0113         return ret;
0114
0115     return tja11xx_check(phydev, reg, mask, set);
0116 }
0117
0118 static int tja11xx_enable_reg_write(struct phy_device *phydev)
0119 {
0120     return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CONFIG_EN);
0121 }
0122
0123 static int tja11xx_enable_link_control(struct phy_device *phydev)
0124 {
0125     return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
0126 }
0127
0128 static int tja11xx_disable_link_control(struct phy_device *phydev)
0129 {
0130     return phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_LINK_CONTROL);
0131 }
0132
0133 static int tja11xx_wakeup(struct phy_device *phydev)
0134 {
0135     int ret;
0136
0137     ret = phy_read(phydev, MII_ECTRL);
0138     if (ret < 0)
0139         return ret;
0140
0141     switch (ret & MII_ECTRL_POWER_MODE_MASK) {
0142     case MII_ECTRL_POWER_MODE_NO_CHANGE:
0143         break;
0144     case MII_ECTRL_POWER_MODE_NORMAL:
0145         ret = phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
0146         if (ret)
0147             return ret;
0148
0149         ret = phy_clear_bits(phydev, MII_ECTRL, MII_ECTRL_WAKE_REQUEST);
0150         if (ret)
0151             return ret;
0152         break;
0153     case MII_ECTRL_POWER_MODE_STANDBY:
0154         ret = phy_modify_check(phydev, MII_ECTRL,
0155                        MII_ECTRL_POWER_MODE_MASK,
0156                        MII_ECTRL_POWER_MODE_STANDBY);
0157         if (ret)
0158             return ret;
0159
0160         ret = phy_modify(phydev, MII_ECTRL, MII_ECTRL_POWER_MODE_MASK,
0161                  MII_ECTRL_POWER_MODE_NORMAL);
0162         if (ret)
0163             return ret;
0164
0165         ret = phy_modify_check(phydev, MII_GENSTAT,
0166                        MII_GENSTAT_PLL_LOCKED,
0167                        MII_GENSTAT_PLL_LOCKED);
0168         if (ret)
0169             return ret;
0170
0171         return tja11xx_enable_link_control(phydev);
0172     default:
0173         break;
0174     }
0175
0176     return 0;
0177 }
0178
0179 static int tja11xx_soft_reset(struct phy_device *phydev)
0180 {
0181     int ret;
0182
0183     ret = tja11xx_enable_reg_write(phydev);
0184     if (ret)
0185         return ret;
0186
0187     return genphy_soft_reset(phydev);
0188 }
0189
0190 static int tja11xx_config_aneg_cable_test(struct phy_device *phydev)
0191 {
0192     bool finished = false;
0193     int ret;
0194
0195     if (phydev->link)
0196         return 0;
0197
0198     if (!phydev->drv->cable_test_start ||
0199         !phydev->drv->cable_test_get_status)
0200         return 0;
0201
0202     ret = ethnl_cable_test_alloc(phydev, ETHTOOL_MSG_CABLE_TEST_NTF);
0203     if (ret)
0204         return ret;
0205
0206     ret = phydev->drv->cable_test_start(phydev);
0207     if (ret)
0208         return ret;
0209
0210     /* According to the documentation this test takes 100 usec */
0211     usleep_range(100, 200);
0212
0213     ret = phydev->drv->cable_test_get_status(phydev, &finished);
0214     if (ret)
0215         return ret;
0216
0217     if (finished)
0218         ethnl_cable_test_finished(phydev);
0219
0220     return 0;
0221 }
0222
0223 static int tja11xx_config_aneg(struct phy_device *phydev)
0224 {
0225     int ret, changed = 0;
0226     u16 ctl = 0;
0227
0228     switch (phydev->master_slave_set) {
0229     case MASTER_SLAVE_CFG_MASTER_FORCE:
0230         ctl |= MII_CFG1_MASTER_SLAVE;
0231         break;
0232     case MASTER_SLAVE_CFG_SLAVE_FORCE:
0233         break;
0234     case MASTER_SLAVE_CFG_UNKNOWN:
0235     case MASTER_SLAVE_CFG_UNSUPPORTED:
0236         goto do_test;
0237     default:
0238         phydev_warn(phydev, "Unsupported Master/Slave mode\n");
0239         return -ENOTSUPP;
0240     }
0241
0242     changed = phy_modify_changed(phydev, MII_CFG1, MII_CFG1_MASTER_SLAVE, ctl);
0243     if (changed < 0)
0244         return changed;
0245
0246 do_test:
0247     ret = tja11xx_config_aneg_cable_test(phydev);
0248     if (ret)
0249         return ret;
0250
0251     return __genphy_config_aneg(phydev, changed);
0252 }
0253
0254 static int tja11xx_config_init(struct phy_device *phydev)
0255 {
0256     int ret;
0257
0258     ret = tja11xx_enable_reg_write(phydev);
0259     if (ret)
0260         return ret;
0261
0262     phydev->autoneg = AUTONEG_DISABLE;
0263     phydev->speed = SPEED_100;
0264     phydev->duplex = DUPLEX_FULL;
0265
0266     switch (phydev->phy_id & PHY_ID_MASK) {
0267     case PHY_ID_TJA1100:
0268         ret = phy_modify(phydev, MII_CFG1,
0269                  MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_MASK |
0270                  MII_CFG1_LED_ENABLE,
0271                  MII_CFG1_AUTO_OP | MII_CFG1_LED_MODE_LINKUP |
0272                  MII_CFG1_LED_ENABLE);
0273         if (ret)
0274             return ret;
0275         break;
0276     case PHY_ID_TJA1101:
0277     case PHY_ID_TJA1102:
0278         ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
0279         if (ret)
0280             return ret;
0281         break;
0282     default:
0283         return -EINVAL;
0284     }
0285
0286     ret = phy_clear_bits(phydev, MII_CFG1, MII_CFG1_SLEEP_CONFIRM);
0287     if (ret)
0288         return ret;
0289
0290     ret = phy_modify(phydev, MII_CFG2, MII_CFG2_SLEEP_REQUEST_TO,
0291              MII_CFG2_SLEEP_REQUEST_TO_16MS);
0292     if (ret)
0293         return ret;
0294
0295     ret = tja11xx_wakeup(phydev);
0296     if (ret < 0)
0297         return ret;
0298
0299     /* ACK interrupts by reading the status register */
0300     ret = phy_read(phydev, MII_INTSRC);
0301     if (ret < 0)
0302         return ret;
0303
0304     return 0;
0305 }
0306
0307 static int tja11xx_read_status(struct phy_device *phydev)
0308 {
0309     int ret;
0310
0311     phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN;
0312     phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
0313
0314     ret = genphy_update_link(phydev);
0315     if (ret)
0316         return ret;
0317
0318     ret = phy_read(phydev, MII_CFG1);
0319     if (ret < 0)
0320         return ret;
0321
0322     if (ret & MII_CFG1_MASTER_SLAVE)
0323         phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE;
0324     else
0325         phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE;
0326
0327     if (phydev->link) {
0328         ret = phy_read(phydev, MII_COMMSTAT);
0329         if (ret < 0)
0330             return ret;
0331
0332         if (!(ret & MII_COMMSTAT_LINK_UP))
0333             phydev->link = 0;
0334     }
0335
0336     return 0;
0337 }
0338
0339 static int tja11xx_get_sqi(struct phy_device *phydev)
0340 {
0341     int ret;
0342
0343     ret = phy_read(phydev, MII_COMMSTAT);
0344     if (ret < 0)
0345         return ret;
0346
0347     return FIELD_GET(MII_COMMSTAT_SQI_STATE, ret);
0348 }
0349
0350 static int tja11xx_get_sqi_max(struct phy_device *phydev)
0351 {
0352     return MII_COMMSTAT_SQI_MAX;
0353 }
0354
0355 static int tja11xx_get_sset_count(struct phy_device *phydev)
0356 {
0357     return ARRAY_SIZE(tja11xx_hw_stats);
0358 }
0359
0360 static void tja11xx_get_strings(struct phy_device *phydev, u8 *data)
0361 {
0362     int i;
0363
0364     for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
0365         strncpy(data + i * ETH_GSTRING_LEN,
0366             tja11xx_hw_stats[i].string, ETH_GSTRING_LEN);
0367     }
0368 }
0369
0370 static void tja11xx_get_stats(struct phy_device *phydev,
0371                   struct ethtool_stats *stats, u64 *data)
0372 {
0373     int i, ret;
0374
0375     for (i = 0; i < ARRAY_SIZE(tja11xx_hw_stats); i++) {
0376         ret = phy_read(phydev, tja11xx_hw_stats[i].reg);
0377         if (ret < 0)
0378             data[i] = U64_MAX;
0379         else {
0380             data[i] = ret & tja11xx_hw_stats[i].mask;
0381             data[i] >>= tja11xx_hw_stats[i].off;
0382         }
0383     }
0384 }
0385
0386 static int tja11xx_hwmon_read(struct device *dev,
0387                   enum hwmon_sensor_types type,
0388                   u32 attr, int channel, long *value)
0389 {
0390     struct phy_device *phydev = dev_get_drvdata(dev);
0391     int ret;
0392
0393     if (type == hwmon_in && attr == hwmon_in_lcrit_alarm) {
0394         ret = phy_read(phydev, MII_INTSRC);
0395         if (ret < 0)
0396             return ret;
0397
0398         *value = !!(ret & MII_INTSRC_TEMP_ERR);
0399         return 0;
0400     }
0401
0402     if (type == hwmon_temp && attr == hwmon_temp_crit_alarm) {
0403         ret = phy_read(phydev, MII_INTSRC);
0404         if (ret < 0)
0405             return ret;
0406
0407         *value = !!(ret & MII_INTSRC_UV_ERR);
0408         return 0;
0409     }
0410
0411     return -EOPNOTSUPP;
0412 }
0413
0414 static umode_t tja11xx_hwmon_is_visible(const void *data,
0415                     enum hwmon_sensor_types type,
0416                     u32 attr, int channel)
0417 {
0418     if (type == hwmon_in && attr == hwmon_in_lcrit_alarm)
0419         return 0444;
0420
0421     if (type == hwmon_temp && attr == hwmon_temp_crit_alarm)
0422         return 0444;
0423
0424     return 0;
0425 }
0426
0427 static const struct hwmon_channel_info *tja11xx_hwmon_info[] = {
0428     HWMON_CHANNEL_INFO(in, HWMON_I_LCRIT_ALARM),
0429     HWMON_CHANNEL_INFO(temp, HWMON_T_CRIT_ALARM),
0430     NULL
0431 };
0432
0433 static const struct hwmon_ops tja11xx_hwmon_hwmon_ops = {
0434     .is_visible = tja11xx_hwmon_is_visible,
0435     .read       = tja11xx_hwmon_read,
0436 };
0437
0438 static const struct hwmon_chip_info tja11xx_hwmon_chip_info = {
0439     .ops        = &tja11xx_hwmon_hwmon_ops,
0440     .info       = tja11xx_hwmon_info,
0441 };
0442
0443 static int tja11xx_hwmon_register(struct phy_device *phydev,
0444                   struct tja11xx_priv *priv)
0445 {
0446     struct device *dev = &phydev->mdio.dev;
0447
0448     priv->hwmon_name = devm_hwmon_sanitize_name(dev, dev_name(dev));
0449     if (IS_ERR(priv->hwmon_name))
0450         return PTR_ERR(priv->hwmon_name);
0451
0452     priv->hwmon_dev =
0453         devm_hwmon_device_register_with_info(dev, priv->hwmon_name,
0454                              phydev,
0455                              &tja11xx_hwmon_chip_info,
0456                              NULL);
0457
0458     return PTR_ERR_OR_ZERO(priv->hwmon_dev);
0459 }
0460
0461 static int tja11xx_probe(struct phy_device *phydev)
0462 {
0463     struct device *dev = &phydev->mdio.dev;
0464     struct tja11xx_priv *priv;
0465
0466     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0467     if (!priv)
0468         return -ENOMEM;
0469
0470     priv->phydev = phydev;
0471
0472     return tja11xx_hwmon_register(phydev, priv);
0473 }
0474
0475 static void tja1102_p1_register(struct work_struct *work)
0476 {
0477     struct tja11xx_priv *priv = container_of(work, struct tja11xx_priv,
0478                          phy_register_work);
0479     struct phy_device *phydev_phy0 = priv->phydev;
0480     struct mii_bus *bus = phydev_phy0->mdio.bus;
0481     struct device *dev = &phydev_phy0->mdio.dev;
0482     struct device_node *np = dev->of_node;
0483     struct device_node *child;
0484     int ret;
0485
0486     for_each_available_child_of_node(np, child) {
0487         struct phy_device *phy;
0488         int addr;
0489
0490         addr = of_mdio_parse_addr(dev, child);
0491         if (addr < 0) {
0492             dev_err(dev, "Can't parse addr\n");
0493             continue;
0494         } else if (addr != phydev_phy0->mdio.addr + 1) {
0495             /* Currently we care only about double PHY chip TJA1102.
0496              * If some day NXP will decide to bring chips with more
0497              * PHYs, this logic should be reworked.
0498              */
0499             dev_err(dev, "Unexpected address. Should be: %i\n",
0500                 phydev_phy0->mdio.addr + 1);
0501             continue;
0502         }
0503
0504         if (mdiobus_is_registered_device(bus, addr)) {
0505             dev_err(dev, "device is already registered\n");
0506             continue;
0507         }
0508
0509         /* Real PHY ID of Port 1 is 0 */
0510         phy = phy_device_create(bus, addr, PHY_ID_TJA1102, false, NULL);
0511         if (IS_ERR(phy)) {
0512             dev_err(dev, "Can't create PHY device for Port 1: %i\n",
0513                 addr);
0514             continue;
0515         }
0516
0517         /* Overwrite parent device. phy_device_create() set parent to
0518          * the mii_bus->dev, which is not correct in case.
0519          */
0520         phy->mdio.dev.parent = dev;
0521
0522         ret = of_mdiobus_phy_device_register(bus, phy, child, addr);
0523         if (ret) {
0524             /* All resources needed for Port 1 should be already
0525              * available for Port 0. Both ports use the same
0526              * interrupt line, so -EPROBE_DEFER would make no sense
0527              * here.
0528              */
0529             dev_err(dev, "Can't register Port 1. Unexpected error: %i\n",
0530                 ret);
0531             phy_device_free(phy);
0532         }
0533     }
0534 }
0535
0536 static int tja1102_p0_probe(struct phy_device *phydev)
0537 {
0538     struct device *dev = &phydev->mdio.dev;
0539     struct tja11xx_priv *priv;
0540     int ret;
0541
0542     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0543     if (!priv)
0544         return -ENOMEM;
0545
0546     priv->phydev = phydev;
0547     INIT_WORK(&priv->phy_register_work, tja1102_p1_register);
0548
0549     ret = tja11xx_hwmon_register(phydev, priv);
0550     if (ret)
0551         return ret;
0552
0553     schedule_work(&priv->phy_register_work);
0554
0555     return 0;
0556 }
0557
0558 static int tja1102_match_phy_device(struct phy_device *phydev, bool port0)
0559 {
0560     int ret;
0561
0562     if ((phydev->phy_id & PHY_ID_MASK) != PHY_ID_TJA1102)
0563         return 0;
0564
0565     ret = phy_read(phydev, MII_PHYSID2);
0566     if (ret < 0)
0567         return ret;
0568
0569     /* TJA1102 Port 1 has phyid 0 and doesn't support temperature
0570      * and undervoltage alarms.
0571      */
0572     if (port0)
0573         return ret ? 1 : 0;
0574
0575     return !ret;
0576 }
0577
0578 static int tja1102_p0_match_phy_device(struct phy_device *phydev)
0579 {
0580     return tja1102_match_phy_device(phydev, true);
0581 }
0582
0583 static int tja1102_p1_match_phy_device(struct phy_device *phydev)
0584 {
0585     return tja1102_match_phy_device(phydev, false);
0586 }
0587
0588 static int tja11xx_ack_interrupt(struct phy_device *phydev)
0589 {
0590     int ret;
0591
0592     ret = phy_read(phydev, MII_INTSRC);
0593
0594     return (ret < 0) ? ret : 0;
0595 }
0596
0597 static int tja11xx_config_intr(struct phy_device *phydev)
0598 {
0599     int value = 0;
0600     int err;
0601
0602     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0603         err = tja11xx_ack_interrupt(phydev);
0604         if (err)
0605             return err;
0606
0607         value = MII_INTEN_LINK_FAIL | MII_INTEN_LINK_UP |
0608             MII_INTEN_UV_ERR | MII_INTEN_TEMP_ERR;
0609         err = phy_write(phydev, MII_INTEN, value);
0610     } else {
0611         err = phy_write(phydev, MII_INTEN, value);
0612         if (err)
0613             return err;
0614
0615         err = tja11xx_ack_interrupt(phydev);
0616     }
0617
0618     return err;
0619 }
0620
0621 static irqreturn_t tja11xx_handle_interrupt(struct phy_device *phydev)
0622 {
0623     struct device *dev = &phydev->mdio.dev;
0624     int irq_status;
0625
0626     irq_status = phy_read(phydev, MII_INTSRC);
0627     if (irq_status < 0) {
0628         phy_error(phydev);
0629         return IRQ_NONE;
0630     }
0631
0632     if (irq_status & MII_INTSRC_TEMP_ERR)
0633         dev_warn(dev, "Overtemperature error detected (temp > 155C°).\n");
0634     if (irq_status & MII_INTSRC_UV_ERR)
0635         dev_warn(dev, "Undervoltage error detected.\n");
0636
0637     if (!(irq_status & MII_INTSRC_MASK))
0638         return IRQ_NONE;
0639
0640     phy_trigger_machine(phydev);
0641
0642     return IRQ_HANDLED;
0643 }
0644
0645 static int tja11xx_cable_test_start(struct phy_device *phydev)
0646 {
0647     int ret;
0648
0649     ret = phy_clear_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
0650     if (ret)
0651         return ret;
0652
0653     ret = tja11xx_wakeup(phydev);
0654     if (ret < 0)
0655         return ret;
0656
0657     ret = tja11xx_disable_link_control(phydev);
0658     if (ret < 0)
0659         return ret;
0660
0661     return phy_set_bits(phydev, MII_ECTRL, MII_ECTRL_CABLE_TEST);
0662 }
0663
0664 /*
0665  * | BI_DA+           | BI_DA-                 | Result
0666  * | open             | open                   | open
0667  * | + short to -     | - short to +           | short
0668  * | short to Vdd     | open                   | open
0669  * | open             | shot to Vdd            | open
0670  * | short to Vdd     | short to Vdd           | short
0671  * | shot to GND      | open                   | open
0672  * | open             | shot to GND            | open
0673  * | short to GND     | shot to GND            | short
0674  * | connected to active link partner (master) | shot and open
0675  */
0676 static int tja11xx_cable_test_report_trans(u32 result)
0677 {
0678     u32 mask = MII_EXTSTAT_SHORT_DETECT | MII_EXTSTAT_OPEN_DETECT;
0679
0680     if ((result & mask) == mask) {
0681         /* connected to active link partner (master) */
0682         return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
0683     } else if ((result & mask) == 0) {
0684         return ETHTOOL_A_CABLE_RESULT_CODE_OK;
0685     } else if (result & MII_EXTSTAT_SHORT_DETECT) {
0686         return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
0687     } else if (result & MII_EXTSTAT_OPEN_DETECT) {
0688         return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
0689     } else {
0690         return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
0691     }
0692 }
0693
0694 static int tja11xx_cable_test_report(struct phy_device *phydev)
0695 {
0696     int ret;
0697
0698     ret = phy_read(phydev, MII_EXTSTAT);
0699     if (ret < 0)
0700         return ret;
0701
0702     ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
0703                 tja11xx_cable_test_report_trans(ret));
0704
0705     return 0;
0706 }
0707
0708 static int tja11xx_cable_test_get_status(struct phy_device *phydev,
0709                      bool *finished)
0710 {
0711     int ret;
0712
0713     *finished = false;
0714
0715     ret = phy_read(phydev, MII_ECTRL);
0716     if (ret < 0)
0717         return ret;
0718
0719     if (!(ret & MII_ECTRL_CABLE_TEST)) {
0720         *finished = true;
0721
0722         ret = phy_set_bits(phydev, MII_COMMCFG, MII_COMMCFG_AUTO_OP);
0723         if (ret)
0724             return ret;
0725
0726         return tja11xx_cable_test_report(phydev);
0727     }
0728
0729     return 0;
0730 }
0731
0732 static struct phy_driver tja11xx_driver[] = {
0733     {
0734         PHY_ID_MATCH_MODEL(PHY_ID_TJA1100),
0735         .name       = "NXP TJA1100",
0736         .features       = PHY_BASIC_T1_FEATURES,
0737         .probe      = tja11xx_probe,
0738         .soft_reset = tja11xx_soft_reset,
0739         .config_aneg    = tja11xx_config_aneg,
0740         .config_init    = tja11xx_config_init,
0741         .read_status    = tja11xx_read_status,
0742         .get_sqi    = tja11xx_get_sqi,
0743         .get_sqi_max    = tja11xx_get_sqi_max,
0744         .suspend    = genphy_suspend,
0745         .resume     = genphy_resume,
0746         .set_loopback   = genphy_loopback,
0747         /* Statistics */
0748         .get_sset_count = tja11xx_get_sset_count,
0749         .get_strings    = tja11xx_get_strings,
0750         .get_stats  = tja11xx_get_stats,
0751     }, {
0752         PHY_ID_MATCH_MODEL(PHY_ID_TJA1101),
0753         .name       = "NXP TJA1101",
0754         .features       = PHY_BASIC_T1_FEATURES,
0755         .probe      = tja11xx_probe,
0756         .soft_reset = tja11xx_soft_reset,
0757         .config_aneg    = tja11xx_config_aneg,
0758         .config_init    = tja11xx_config_init,
0759         .read_status    = tja11xx_read_status,
0760         .get_sqi    = tja11xx_get_sqi,
0761         .get_sqi_max    = tja11xx_get_sqi_max,
0762         .suspend    = genphy_suspend,
0763         .resume     = genphy_resume,
0764         .set_loopback   = genphy_loopback,
0765         /* Statistics */
0766         .get_sset_count = tja11xx_get_sset_count,
0767         .get_strings    = tja11xx_get_strings,
0768         .get_stats  = tja11xx_get_stats,
0769     }, {
0770         .name       = "NXP TJA1102 Port 0",
0771         .features       = PHY_BASIC_T1_FEATURES,
0772         .flags          = PHY_POLL_CABLE_TEST,
0773         .probe      = tja1102_p0_probe,
0774         .soft_reset = tja11xx_soft_reset,
0775         .config_aneg    = tja11xx_config_aneg,
0776         .config_init    = tja11xx_config_init,
0777         .read_status    = tja11xx_read_status,
0778         .get_sqi    = tja11xx_get_sqi,
0779         .get_sqi_max    = tja11xx_get_sqi_max,
0780         .match_phy_device = tja1102_p0_match_phy_device,
0781         .suspend    = genphy_suspend,
0782         .resume     = genphy_resume,
0783         .set_loopback   = genphy_loopback,
0784         /* Statistics */
0785         .get_sset_count = tja11xx_get_sset_count,
0786         .get_strings    = tja11xx_get_strings,
0787         .get_stats  = tja11xx_get_stats,
0788         .config_intr    = tja11xx_config_intr,
0789         .handle_interrupt = tja11xx_handle_interrupt,
0790         .cable_test_start = tja11xx_cable_test_start,
0791         .cable_test_get_status = tja11xx_cable_test_get_status,
0792     }, {
0793         .name       = "NXP TJA1102 Port 1",
0794         .features       = PHY_BASIC_T1_FEATURES,
0795         .flags          = PHY_POLL_CABLE_TEST,
0796         /* currently no probe for Port 1 is need */
0797         .soft_reset = tja11xx_soft_reset,
0798         .config_aneg    = tja11xx_config_aneg,
0799         .config_init    = tja11xx_config_init,
0800         .read_status    = tja11xx_read_status,
0801         .get_sqi    = tja11xx_get_sqi,
0802         .get_sqi_max    = tja11xx_get_sqi_max,
0803         .match_phy_device = tja1102_p1_match_phy_device,
0804         .suspend    = genphy_suspend,
0805         .resume     = genphy_resume,
0806         .set_loopback   = genphy_loopback,
0807         /* Statistics */
0808         .get_sset_count = tja11xx_get_sset_count,
0809         .get_strings    = tja11xx_get_strings,
0810         .get_stats  = tja11xx_get_stats,
0811         .config_intr    = tja11xx_config_intr,
0812         .handle_interrupt = tja11xx_handle_interrupt,
0813         .cable_test_start = tja11xx_cable_test_start,
0814         .cable_test_get_status = tja11xx_cable_test_get_status,
0815     }
0816 };
0817
0818 module_phy_driver(tja11xx_driver);
0819
0820 static struct mdio_device_id __maybe_unused tja11xx_tbl[] = {
0821     { PHY_ID_MATCH_MODEL(PHY_ID_TJA1100) },
0822     { PHY_ID_MATCH_MODEL(PHY_ID_TJA1101) },
0823     { PHY_ID_MATCH_MODEL(PHY_ID_TJA1102) },
0824     { }
0825 };
0826
0827 MODULE_DEVICE_TABLE(mdio, tja11xx_tbl);
0828
0829 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
0830 MODULE_DESCRIPTION("NXP TJA11xx BoardR-Reach PHY driver");
0831 MODULE_LICENSE("GPL");