net/phy/national.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * drivers/net/phy/national.c
0004  *
0005  * Driver for National Semiconductor PHYs
0006  *
0007  * Author: Stuart Menefy <stuart.menefy@st.com>
0008  * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
0009  *
0010  * Copyright (c) 2008 STMicroelectronics Limited
0011  */
0012
0013 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0014
0015 #include <linux/kernel.h>
0016 #include <linux/module.h>
0017 #include <linux/mii.h>
0018 #include <linux/ethtool.h>
0019 #include <linux/phy.h>
0020 #include <linux/netdevice.h>
0021
0022 /* DP83865 phy identifier values */
0023 #define DP83865_PHY_ID  0x20005c7a
0024
0025 #define DP83865_INT_STATUS  0x14
0026 #define DP83865_INT_MASK    0x15
0027 #define DP83865_INT_CLEAR   0x17
0028
0029 #define DP83865_INT_REMOTE_FAULT 0x0008
0030 #define DP83865_INT_ANE_COMPLETED 0x0010
0031 #define DP83865_INT_LINK_CHANGE 0xe000
0032 #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
0033                 DP83865_INT_ANE_COMPLETED | \
0034                 DP83865_INT_LINK_CHANGE)
0035
0036 /* Advanced proprietary configuration */
0037 #define NS_EXP_MEM_CTL  0x16
0038 #define NS_EXP_MEM_DATA 0x1d
0039 #define NS_EXP_MEM_ADD  0x1e
0040
0041 #define LED_CTRL_REG 0x13
0042 #define AN_FALLBACK_AN 0x0001
0043 #define AN_FALLBACK_CRC 0x0002
0044 #define AN_FALLBACK_IE 0x0004
0045 #define ALL_FALLBACK_ON (AN_FALLBACK_AN |  AN_FALLBACK_CRC | AN_FALLBACK_IE)
0046
0047 enum hdx_loopback {
0048     hdx_loopback_on = 0,
0049     hdx_loopback_off = 1,
0050 };
0051
0052 static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
0053 {
0054     phy_write(phydev, NS_EXP_MEM_ADD, reg);
0055     return phy_read(phydev, NS_EXP_MEM_DATA);
0056 }
0057
0058 static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
0059 {
0060     phy_write(phydev, NS_EXP_MEM_ADD, reg);
0061     phy_write(phydev, NS_EXP_MEM_DATA, data);
0062 }
0063
0064 static int ns_ack_interrupt(struct phy_device *phydev)
0065 {
0066     int ret = phy_read(phydev, DP83865_INT_STATUS);
0067     if (ret < 0)
0068         return ret;
0069
0070     /* Clear the interrupt status bit by writing a “1”
0071      * to the corresponding bit in INT_CLEAR (2:0 are reserved)
0072      */
0073     ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
0074
0075     return ret;
0076 }
0077
0078 static irqreturn_t ns_handle_interrupt(struct phy_device *phydev)
0079 {
0080     int irq_status;
0081
0082     irq_status = phy_read(phydev, DP83865_INT_STATUS);
0083     if (irq_status < 0) {
0084         phy_error(phydev);
0085         return IRQ_NONE;
0086     }
0087
0088     if (!(irq_status & DP83865_INT_MASK_DEFAULT))
0089         return IRQ_NONE;
0090
0091     /* clear the interrupt */
0092     phy_write(phydev, DP83865_INT_CLEAR, irq_status & ~0x7);
0093
0094     phy_trigger_machine(phydev);
0095
0096     return IRQ_HANDLED;
0097 }
0098
0099 static int ns_config_intr(struct phy_device *phydev)
0100 {
0101     int err;
0102
0103     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0104         err = ns_ack_interrupt(phydev);
0105         if (err)
0106             return err;
0107
0108         err = phy_write(phydev, DP83865_INT_MASK,
0109                 DP83865_INT_MASK_DEFAULT);
0110     } else {
0111         err = phy_write(phydev, DP83865_INT_MASK, 0);
0112         if (err)
0113             return err;
0114
0115         err = ns_ack_interrupt(phydev);
0116     }
0117
0118     return err;
0119 }
0120
0121 static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
0122 {
0123     int bmcr = phy_read(phydev, MII_BMCR);
0124
0125     phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
0126
0127     /* Enable 8 bit expended memory read/write (no auto increment) */
0128     phy_write(phydev, NS_EXP_MEM_CTL, 0);
0129     phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
0130     phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
0131     phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
0132     phy_write(phydev, LED_CTRL_REG, mode);
0133 }
0134
0135 static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
0136 {
0137     u16 lb_dis = BIT(1);
0138
0139     if (disable)
0140         ns_exp_write(phydev, 0x1c0,
0141                  ns_exp_read(phydev, 0x1c0) | lb_dis);
0142     else
0143         ns_exp_write(phydev, 0x1c0,
0144                  ns_exp_read(phydev, 0x1c0) & ~lb_dis);
0145
0146     pr_debug("10BASE-T HDX loopback %s\n",
0147          (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on");
0148 }
0149
0150 static int ns_config_init(struct phy_device *phydev)
0151 {
0152     ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
0153     /* In the latest MAC or switches design, the 10 Mbps loopback
0154      * is desired to be turned off.
0155      */
0156     ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
0157     return ns_ack_interrupt(phydev);
0158 }
0159
0160 static struct phy_driver dp83865_driver[] = { {
0161     .phy_id = DP83865_PHY_ID,
0162     .phy_id_mask = 0xfffffff0,
0163     .name = "NatSemi DP83865",
0164     /* PHY_GBIT_FEATURES */
0165     .config_init = ns_config_init,
0166     .config_intr = ns_config_intr,
0167     .handle_interrupt = ns_handle_interrupt,
0168 } };
0169
0170 module_phy_driver(dp83865_driver);
0171
0172 MODULE_DESCRIPTION("NatSemi PHY driver");
0173 MODULE_AUTHOR("Stuart Menefy");
0174 MODULE_LICENSE("GPL");
0175
0176 static struct mdio_device_id __maybe_unused ns_tbl[] = {
0177     { DP83865_PHY_ID, 0xfffffff0 },
0178     { }
0179 };
0180
0181 MODULE_DEVICE_TABLE(mdio, ns_tbl);