phy/mscc/mscc_serdes.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /*
0003  * Driver for Microsemi VSC85xx PHYs
0004  *
0005  * Copyright (c) 2021 Microsemi Corporation
0006  */
0007
0008 #ifndef _MSCC_SERDES_PHY_H_
0009 #define _MSCC_SERDES_PHY_H_
0010
0011 #define PHY_S6G_PLL5G_CFG2_GAIN_MASK      GENMASK(9, 5)
0012 #define PHY_S6G_PLL5G_CFG2_ENA_GAIN       1
0013
0014 #define PHY_S6G_DES_PHY_CTRL_POS      13
0015 #define PHY_S6G_DES_MBTR_CTRL_POS     10
0016 #define PHY_S6G_DES_CPMD_SEL_POS      8
0017 #define PHY_S6G_DES_BW_HYST_POS       5
0018 #define PHY_S6G_DES_BW_ANA_POS        1
0019 #define PHY_S6G_DES_CFG           0x21
0020 #define PHY_S6G_IB_CFG0           0x22
0021 #define PHY_S6G_IB_CFG1           0x23
0022 #define PHY_S6G_IB_CFG2           0x24
0023 #define PHY_S6G_IB_CFG3           0x25
0024 #define PHY_S6G_IB_CFG4           0x26
0025 #define PHY_S6G_GP_CFG            0x2E
0026 #define PHY_S6G_DFT_CFG0          0x35
0027 #define PHY_S6G_IB_DFT_CFG2       0x37
0028
0029 int vsc85xx_sd6g_config_v2(struct phy_device *phydev);
0030
0031 #endif /* _MSCC_PHY_SERDES_H_ */