phy/mscc/mscc_fc_buffer.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /*
0003  * Driver for Microsemi VSC85xx PHYs
0004  *
0005  * Copyright (C) 2020 Microsemi Corporation
0006  */
0007
0008 #ifndef _MSCC_PHY_FC_BUFFER_H_
0009 #define _MSCC_PHY_FC_BUFFER_H_
0010
0011 #define MSCC_FCBUF_ENA_CFG                  0x00
0012 #define MSCC_FCBUF_MODE_CFG                 0x01
0013 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG            0x02
0014 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG                0x03
0015 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG                0x04
0016 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG                0x05
0017 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG          0x06
0018 #define MSCC_FCBUF_FC_READ_THRESH_CFG               0x07
0019 #define MSCC_FCBUF_TX_FRM_GAP_COMP              0x08
0020
0021 #define MSCC_FCBUF_ENA_CFG_TX_ENA               BIT(0)
0022 #define MSCC_FCBUF_ENA_CFG_RX_ENA               BIT(4)
0023
0024 #define MSCC_FCBUF_MODE_CFG_DROP_BEHAVIOUR          BIT(4)
0025 #define MSCC_FCBUF_MODE_CFG_PAUSE_REACT_ENA         BIT(8)
0026 #define MSCC_FCBUF_MODE_CFG_RX_PPM_RATE_ADAPT_ENA       BIT(12)
0027 #define MSCC_FCBUF_MODE_CFG_TX_PPM_RATE_ADAPT_ENA       BIT(16)
0028 #define MSCC_FCBUF_MODE_CFG_TX_CTRL_QUEUE_ENA           BIT(20)
0029 #define MSCC_FCBUF_MODE_CFG_PAUSE_GEN_ENA           BIT(24)
0030 #define MSCC_FCBUF_MODE_CFG_INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN BIT(28)
0031
0032 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH(x)   (x)
0033 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_THRESH_M    GENMASK(15, 0)
0034 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET(x)   ((x) << 16)
0035 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_TX_OFFSET_M    GENMASK(19, 16)
0036 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH(x)   ((x) << 20)
0037 #define MSCC_FCBUF_PPM_RATE_ADAPT_THRESH_CFG_RX_THRESH_M    GENMASK(31, 20)
0038
0039 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START(x)           (x)
0040 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_START_M            GENMASK(15, 0)
0041 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END(x)         ((x) << 16)
0042 #define MSCC_FCBUF_TX_CTRL_QUEUE_CFG_END_M          GENMASK(31, 16)
0043
0044 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START(x)           (x)
0045 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_START_M            GENMASK(15, 0)
0046 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END(x)         ((x) << 16)
0047 #define MSCC_FCBUF_TX_DATA_QUEUE_CFG_END_M          GENMASK(31, 16)
0048
0049 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START(x)           (x)
0050 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_START_M            GENMASK(15, 0)
0051 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END(x)         ((x) << 16)
0052 #define MSCC_FCBUF_RX_DATA_QUEUE_CFG_END_M          GENMASK(31, 16)
0053
0054 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH(x)   (x)
0055 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XOFF_THRESH_M    GENMASK(15, 0)
0056 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH(x)    ((x) << 16)
0057 #define MSCC_FCBUF_TX_BUFF_XON_XOFF_THRESH_CFG_XON_THRESH_M GENMASK(31, 16)
0058
0059 #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH(x)      (x)
0060 #define MSCC_FCBUF_FC_READ_THRESH_CFG_TX_THRESH_M       GENMASK(15, 0)
0061 #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH(x)      ((x) << 16)
0062 #define MSCC_FCBUF_FC_READ_THRESH_CFG_RX_THRESH_M       GENMASK(31, 16)
0063
0064 #endif /* _MSCC_PHY_FC_BUFFER_H_ */