net/phy/mediatek-ge.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 #include <linux/bitfield.h>
0003 #include <linux/module.h>
0004 #include <linux/phy.h>
0005
0006 #define MTK_EXT_PAGE_ACCESS     0x1f
0007 #define MTK_PHY_PAGE_STANDARD       0x0000
0008 #define MTK_PHY_PAGE_EXTENDED       0x0001
0009 #define MTK_PHY_PAGE_EXTENDED_2     0x0002
0010 #define MTK_PHY_PAGE_EXTENDED_3     0x0003
0011 #define MTK_PHY_PAGE_EXTENDED_2A30  0x2a30
0012 #define MTK_PHY_PAGE_EXTENDED_52B5  0x52b5
0013
0014 static int mtk_gephy_read_page(struct phy_device *phydev)
0015 {
0016     return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
0017 }
0018
0019 static int mtk_gephy_write_page(struct phy_device *phydev, int page)
0020 {
0021     return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
0022 }
0023
0024 static void mtk_gephy_config_init(struct phy_device *phydev)
0025 {
0026     /* Disable EEE */
0027     phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
0028
0029     /* Enable HW auto downshift */
0030     phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED, 0x14, 0, BIT(4));
0031
0032     /* Increase SlvDPSready time */
0033     phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
0034     __phy_write(phydev, 0x10, 0xafae);
0035     __phy_write(phydev, 0x12, 0x2f);
0036     __phy_write(phydev, 0x10, 0x8fae);
0037     phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
0038
0039     /* Adjust 100_mse_threshold */
0040     phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x123, 0xffff);
0041
0042     /* Disable mcc */
0043     phy_write_mmd(phydev, MDIO_MMD_VEND1, 0xa6, 0x300);
0044 }
0045
0046 static int mt7530_phy_config_init(struct phy_device *phydev)
0047 {
0048     mtk_gephy_config_init(phydev);
0049
0050     /* Increase post_update_timer */
0051     phy_write_paged(phydev, MTK_PHY_PAGE_EXTENDED_3, 0x11, 0x4b);
0052
0053     return 0;
0054 }
0055
0056 static int mt7531_phy_config_init(struct phy_device *phydev)
0057 {
0058     mtk_gephy_config_init(phydev);
0059
0060     /* PHY link down power saving enable */
0061     phy_set_bits(phydev, 0x17, BIT(4));
0062     phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 0xc6, 0x300);
0063
0064     /* Set TX Pair delay selection */
0065     phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x13, 0x404);
0066     phy_write_mmd(phydev, MDIO_MMD_VEND1, 0x14, 0x404);
0067
0068     return 0;
0069 }
0070
0071 static struct phy_driver mtk_gephy_driver[] = {
0072     {
0073         PHY_ID_MATCH_EXACT(0x03a29412),
0074         .name       = "MediaTek MT7530 PHY",
0075         .config_init    = mt7530_phy_config_init,
0076         /* Interrupts are handled by the switch, not the PHY
0077          * itself.
0078          */
0079         .config_intr    = genphy_no_config_intr,
0080         .handle_interrupt = genphy_handle_interrupt_no_ack,
0081         .suspend    = genphy_suspend,
0082         .resume     = genphy_resume,
0083         .read_page  = mtk_gephy_read_page,
0084         .write_page = mtk_gephy_write_page,
0085     },
0086     {
0087         PHY_ID_MATCH_EXACT(0x03a29441),
0088         .name       = "MediaTek MT7531 PHY",
0089         .config_init    = mt7531_phy_config_init,
0090         /* Interrupts are handled by the switch, not the PHY
0091          * itself.
0092          */
0093         .config_intr    = genphy_no_config_intr,
0094         .handle_interrupt = genphy_handle_interrupt_no_ack,
0095         .suspend    = genphy_suspend,
0096         .resume     = genphy_resume,
0097         .read_page  = mtk_gephy_read_page,
0098         .write_page = mtk_gephy_write_page,
0099     },
0100 };
0101
0102 module_phy_driver(mtk_gephy_driver);
0103
0104 static struct mdio_device_id __maybe_unused mtk_gephy_tbl[] = {
0105     { PHY_ID_MATCH_VENDOR(0x03a29400) },
0106     { }
0107 };
0108
0109 MODULE_DESCRIPTION("MediaTek Gigabit Ethernet PHY driver");
0110 MODULE_AUTHOR("DENG, Qingfang <dqfext@gmail.com>");
0111 MODULE_LICENSE("GPL");
0112
0113 MODULE_DEVICE_TABLE(mdio, mtk_gephy_tbl);