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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Driver for the Texas Instruments DP83869 PHY
0003  * Copyright (C) 2019 Texas Instruments Inc.
0004  */
0005 
0006 #include <linux/ethtool.h>
0007 #include <linux/etherdevice.h>
0008 #include <linux/kernel.h>
0009 #include <linux/mii.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/phy.h>
0013 #include <linux/delay.h>
0014 #include <linux/bitfield.h>
0015 
0016 #include <dt-bindings/net/ti-dp83869.h>
0017 
0018 #define DP83869_PHY_ID      0x2000a0f1
0019 #define DP83561_PHY_ID      0x2000a1a4
0020 #define DP83869_DEVADDR     0x1f
0021 
0022 #define MII_DP83869_PHYCTRL 0x10
0023 #define MII_DP83869_MICR    0x12
0024 #define MII_DP83869_ISR     0x13
0025 #define DP83869_CFG2        0x14
0026 #define DP83869_CTRL        0x1f
0027 #define DP83869_CFG4        0x1e
0028 
0029 /* Extended Registers */
0030 #define DP83869_GEN_CFG3        0x0031
0031 #define DP83869_RGMIICTL    0x0032
0032 #define DP83869_STRAP_STS1  0x006e
0033 #define DP83869_RGMIIDCTL   0x0086
0034 #define DP83869_RXFCFG      0x0134
0035 #define DP83869_RXFPMD1     0x0136
0036 #define DP83869_RXFPMD2     0x0137
0037 #define DP83869_RXFPMD3     0x0138
0038 #define DP83869_RXFSOP1     0x0139
0039 #define DP83869_RXFSOP2     0x013A
0040 #define DP83869_RXFSOP3     0x013B
0041 #define DP83869_IO_MUX_CFG  0x0170
0042 #define DP83869_OP_MODE     0x01df
0043 #define DP83869_FX_CTRL     0x0c00
0044 
0045 #define DP83869_SW_RESET    BIT(15)
0046 #define DP83869_SW_RESTART  BIT(14)
0047 
0048 /* MICR Interrupt bits */
0049 #define MII_DP83869_MICR_AN_ERR_INT_EN      BIT(15)
0050 #define MII_DP83869_MICR_SPEED_CHNG_INT_EN  BIT(14)
0051 #define MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
0052 #define MII_DP83869_MICR_PAGE_RXD_INT_EN    BIT(12)
0053 #define MII_DP83869_MICR_AUTONEG_COMP_INT_EN    BIT(11)
0054 #define MII_DP83869_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
0055 #define MII_DP83869_MICR_FALSE_CARRIER_INT_EN   BIT(8)
0056 #define MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
0057 #define MII_DP83869_MICR_WOL_INT_EN     BIT(3)
0058 #define MII_DP83869_MICR_XGMII_ERR_INT_EN   BIT(2)
0059 #define MII_DP83869_MICR_POL_CHNG_INT_EN    BIT(1)
0060 #define MII_DP83869_MICR_JABBER_INT_EN      BIT(0)
0061 
0062 #define MII_DP83869_BMCR_DEFAULT    (BMCR_ANENABLE | \
0063                      BMCR_FULLDPLX | \
0064                      BMCR_SPEED1000)
0065 
0066 #define MII_DP83869_FIBER_ADVERTISE    (ADVERTISED_FIBRE | \
0067                     ADVERTISED_Pause | \
0068                     ADVERTISED_Asym_Pause)
0069 
0070 /* This is the same bit mask as the BMCR so re-use the BMCR default */
0071 #define DP83869_FX_CTRL_DEFAULT MII_DP83869_BMCR_DEFAULT
0072 
0073 /* CFG1 bits */
0074 #define DP83869_CFG1_DEFAULT    (ADVERTISE_1000HALF | \
0075                  ADVERTISE_1000FULL | \
0076                  CTL1000_AS_MASTER)
0077 
0078 /* RGMIICTL bits */
0079 #define DP83869_RGMII_TX_CLK_DELAY_EN       BIT(1)
0080 #define DP83869_RGMII_RX_CLK_DELAY_EN       BIT(0)
0081 
0082 /* RGMIIDCTL */
0083 #define DP83869_RGMII_CLK_DELAY_SHIFT       4
0084 #define DP83869_CLK_DELAY_DEF           7
0085 
0086 /* STRAP_STS1 bits */
0087 #define DP83869_STRAP_OP_MODE_MASK      GENMASK(2, 0)
0088 #define DP83869_STRAP_STS1_RESERVED     BIT(11)
0089 #define DP83869_STRAP_MIRROR_ENABLED           BIT(12)
0090 
0091 /* PHYCTRL bits */
0092 #define DP83869_RX_FIFO_SHIFT   12
0093 #define DP83869_TX_FIFO_SHIFT   14
0094 
0095 /* PHY_CTRL lower bytes 0x48 are declared as reserved */
0096 #define DP83869_PHY_CTRL_DEFAULT    0x48
0097 #define DP83869_PHYCR_FIFO_DEPTH_MASK   GENMASK(15, 12)
0098 #define DP83869_PHYCR_RESERVED_MASK BIT(11)
0099 
0100 /* IO_MUX_CFG bits */
0101 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
0102 
0103 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
0104 #define DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
0105 #define DP83869_IO_MUX_CFG_CLK_O_SEL_MASK   (0x1f << 8)
0106 #define DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT  8
0107 
0108 /* CFG3 bits */
0109 #define DP83869_CFG3_PORT_MIRROR_EN              BIT(0)
0110 
0111 /* CFG4 bits */
0112 #define DP83869_INT_OE  BIT(7)
0113 
0114 /* OP MODE */
0115 #define DP83869_OP_MODE_MII         BIT(5)
0116 #define DP83869_SGMII_RGMII_BRIDGE      BIT(6)
0117 
0118 /* RXFCFG bits*/
0119 #define DP83869_WOL_MAGIC_EN        BIT(0)
0120 #define DP83869_WOL_PATTERN_EN      BIT(1)
0121 #define DP83869_WOL_BCAST_EN        BIT(2)
0122 #define DP83869_WOL_UCAST_EN        BIT(4)
0123 #define DP83869_WOL_SEC_EN      BIT(5)
0124 #define DP83869_WOL_ENH_MAC     BIT(7)
0125 
0126 /* CFG2 bits */
0127 #define DP83869_DOWNSHIFT_EN        (BIT(8) | BIT(9))
0128 #define DP83869_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
0129 #define DP83869_DOWNSHIFT_1_COUNT_VAL   0
0130 #define DP83869_DOWNSHIFT_2_COUNT_VAL   1
0131 #define DP83869_DOWNSHIFT_4_COUNT_VAL   2
0132 #define DP83869_DOWNSHIFT_8_COUNT_VAL   3
0133 #define DP83869_DOWNSHIFT_1_COUNT   1
0134 #define DP83869_DOWNSHIFT_2_COUNT   2
0135 #define DP83869_DOWNSHIFT_4_COUNT   4
0136 #define DP83869_DOWNSHIFT_8_COUNT   8
0137 
0138 enum {
0139     DP83869_PORT_MIRRORING_KEEP,
0140     DP83869_PORT_MIRRORING_EN,
0141     DP83869_PORT_MIRRORING_DIS,
0142 };
0143 
0144 struct dp83869_private {
0145     int tx_fifo_depth;
0146     int rx_fifo_depth;
0147     s32 rx_int_delay;
0148     s32 tx_int_delay;
0149     int io_impedance;
0150     int port_mirroring;
0151     bool rxctrl_strap_quirk;
0152     int clk_output_sel;
0153     int mode;
0154 };
0155 
0156 static int dp83869_read_status(struct phy_device *phydev)
0157 {
0158     struct dp83869_private *dp83869 = phydev->priv;
0159     int ret;
0160 
0161     ret = genphy_read_status(phydev);
0162     if (ret)
0163         return ret;
0164 
0165     if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
0166         if (phydev->link) {
0167             if (dp83869->mode == DP83869_RGMII_100_BASE)
0168                 phydev->speed = SPEED_100;
0169         } else {
0170             phydev->speed = SPEED_UNKNOWN;
0171             phydev->duplex = DUPLEX_UNKNOWN;
0172         }
0173     }
0174 
0175     return 0;
0176 }
0177 
0178 static int dp83869_ack_interrupt(struct phy_device *phydev)
0179 {
0180     int err = phy_read(phydev, MII_DP83869_ISR);
0181 
0182     if (err < 0)
0183         return err;
0184 
0185     return 0;
0186 }
0187 
0188 static int dp83869_config_intr(struct phy_device *phydev)
0189 {
0190     int micr_status = 0, err;
0191 
0192     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0193         err = dp83869_ack_interrupt(phydev);
0194         if (err)
0195             return err;
0196 
0197         micr_status = phy_read(phydev, MII_DP83869_MICR);
0198         if (micr_status < 0)
0199             return micr_status;
0200 
0201         micr_status |=
0202             (MII_DP83869_MICR_AN_ERR_INT_EN |
0203             MII_DP83869_MICR_SPEED_CHNG_INT_EN |
0204             MII_DP83869_MICR_AUTONEG_COMP_INT_EN |
0205             MII_DP83869_MICR_LINK_STS_CHNG_INT_EN |
0206             MII_DP83869_MICR_DUP_MODE_CHNG_INT_EN |
0207             MII_DP83869_MICR_SLEEP_MODE_CHNG_INT_EN);
0208 
0209         err = phy_write(phydev, MII_DP83869_MICR, micr_status);
0210     } else {
0211         err = phy_write(phydev, MII_DP83869_MICR, micr_status);
0212         if (err)
0213             return err;
0214 
0215         err = dp83869_ack_interrupt(phydev);
0216     }
0217 
0218     return err;
0219 }
0220 
0221 static irqreturn_t dp83869_handle_interrupt(struct phy_device *phydev)
0222 {
0223     int irq_status, irq_enabled;
0224 
0225     irq_status = phy_read(phydev, MII_DP83869_ISR);
0226     if (irq_status < 0) {
0227         phy_error(phydev);
0228         return IRQ_NONE;
0229     }
0230 
0231     irq_enabled = phy_read(phydev, MII_DP83869_MICR);
0232     if (irq_enabled < 0) {
0233         phy_error(phydev);
0234         return IRQ_NONE;
0235     }
0236 
0237     if (!(irq_status & irq_enabled))
0238         return IRQ_NONE;
0239 
0240     phy_trigger_machine(phydev);
0241 
0242     return IRQ_HANDLED;
0243 }
0244 
0245 static int dp83869_set_wol(struct phy_device *phydev,
0246                struct ethtool_wolinfo *wol)
0247 {
0248     struct net_device *ndev = phydev->attached_dev;
0249     int val_rxcfg, val_micr;
0250     const u8 *mac;
0251     int ret;
0252 
0253     val_rxcfg = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
0254     if (val_rxcfg < 0)
0255         return val_rxcfg;
0256 
0257     val_micr = phy_read(phydev, MII_DP83869_MICR);
0258     if (val_micr < 0)
0259         return val_micr;
0260 
0261     if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
0262                 WAKE_BCAST)) {
0263         val_rxcfg |= DP83869_WOL_ENH_MAC;
0264         val_micr |= MII_DP83869_MICR_WOL_INT_EN;
0265 
0266         if (wol->wolopts & WAKE_MAGIC ||
0267             wol->wolopts & WAKE_MAGICSECURE) {
0268             mac = (const u8 *)ndev->dev_addr;
0269 
0270             if (!is_valid_ether_addr(mac))
0271                 return -EINVAL;
0272 
0273             ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0274                         DP83869_RXFPMD1,
0275                         mac[1] << 8 | mac[0]);
0276             if (ret)
0277                 return ret;
0278 
0279             ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0280                         DP83869_RXFPMD2,
0281                         mac[3] << 8 | mac[2]);
0282             if (ret)
0283                 return ret;
0284 
0285             ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0286                         DP83869_RXFPMD3,
0287                         mac[5] << 8 | mac[4]);
0288             if (ret)
0289                 return ret;
0290 
0291             val_rxcfg |= DP83869_WOL_MAGIC_EN;
0292         } else {
0293             val_rxcfg &= ~DP83869_WOL_MAGIC_EN;
0294         }
0295 
0296         if (wol->wolopts & WAKE_MAGICSECURE) {
0297             ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0298                         DP83869_RXFSOP1,
0299                         (wol->sopass[1] << 8) | wol->sopass[0]);
0300             if (ret)
0301                 return ret;
0302 
0303             ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0304                         DP83869_RXFSOP2,
0305                         (wol->sopass[3] << 8) | wol->sopass[2]);
0306             if (ret)
0307                 return ret;
0308             ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0309                         DP83869_RXFSOP3,
0310                         (wol->sopass[5] << 8) | wol->sopass[4]);
0311             if (ret)
0312                 return ret;
0313 
0314             val_rxcfg |= DP83869_WOL_SEC_EN;
0315         } else {
0316             val_rxcfg &= ~DP83869_WOL_SEC_EN;
0317         }
0318 
0319         if (wol->wolopts & WAKE_UCAST)
0320             val_rxcfg |= DP83869_WOL_UCAST_EN;
0321         else
0322             val_rxcfg &= ~DP83869_WOL_UCAST_EN;
0323 
0324         if (wol->wolopts & WAKE_BCAST)
0325             val_rxcfg |= DP83869_WOL_BCAST_EN;
0326         else
0327             val_rxcfg &= ~DP83869_WOL_BCAST_EN;
0328     } else {
0329         val_rxcfg &= ~DP83869_WOL_ENH_MAC;
0330         val_micr &= ~MII_DP83869_MICR_WOL_INT_EN;
0331     }
0332 
0333     ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG, val_rxcfg);
0334     if (ret)
0335         return ret;
0336 
0337     return phy_write(phydev, MII_DP83869_MICR, val_micr);
0338 }
0339 
0340 static void dp83869_get_wol(struct phy_device *phydev,
0341                 struct ethtool_wolinfo *wol)
0342 {
0343     int value, sopass_val;
0344 
0345     wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
0346             WAKE_MAGICSECURE);
0347     wol->wolopts = 0;
0348 
0349     value = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RXFCFG);
0350     if (value < 0) {
0351         phydev_err(phydev, "Failed to read RX CFG\n");
0352         return;
0353     }
0354 
0355     if (value & DP83869_WOL_UCAST_EN)
0356         wol->wolopts |= WAKE_UCAST;
0357 
0358     if (value & DP83869_WOL_BCAST_EN)
0359         wol->wolopts |= WAKE_BCAST;
0360 
0361     if (value & DP83869_WOL_MAGIC_EN)
0362         wol->wolopts |= WAKE_MAGIC;
0363 
0364     if (value & DP83869_WOL_SEC_EN) {
0365         sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
0366                       DP83869_RXFSOP1);
0367         if (sopass_val < 0) {
0368             phydev_err(phydev, "Failed to read RX SOP 1\n");
0369             return;
0370         }
0371 
0372         wol->sopass[0] = (sopass_val & 0xff);
0373         wol->sopass[1] = (sopass_val >> 8);
0374 
0375         sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
0376                       DP83869_RXFSOP2);
0377         if (sopass_val < 0) {
0378             phydev_err(phydev, "Failed to read RX SOP 2\n");
0379             return;
0380         }
0381 
0382         wol->sopass[2] = (sopass_val & 0xff);
0383         wol->sopass[3] = (sopass_val >> 8);
0384 
0385         sopass_val = phy_read_mmd(phydev, DP83869_DEVADDR,
0386                       DP83869_RXFSOP3);
0387         if (sopass_val < 0) {
0388             phydev_err(phydev, "Failed to read RX SOP 3\n");
0389             return;
0390         }
0391 
0392         wol->sopass[4] = (sopass_val & 0xff);
0393         wol->sopass[5] = (sopass_val >> 8);
0394 
0395         wol->wolopts |= WAKE_MAGICSECURE;
0396     }
0397 
0398     if (!(value & DP83869_WOL_ENH_MAC))
0399         wol->wolopts = 0;
0400 }
0401 
0402 static int dp83869_get_downshift(struct phy_device *phydev, u8 *data)
0403 {
0404     int val, cnt, enable, count;
0405 
0406     val = phy_read(phydev, DP83869_CFG2);
0407     if (val < 0)
0408         return val;
0409 
0410     enable = FIELD_GET(DP83869_DOWNSHIFT_EN, val);
0411     cnt = FIELD_GET(DP83869_DOWNSHIFT_ATTEMPT_MASK, val);
0412 
0413     switch (cnt) {
0414     case DP83869_DOWNSHIFT_1_COUNT_VAL:
0415         count = DP83869_DOWNSHIFT_1_COUNT;
0416         break;
0417     case DP83869_DOWNSHIFT_2_COUNT_VAL:
0418         count = DP83869_DOWNSHIFT_2_COUNT;
0419         break;
0420     case DP83869_DOWNSHIFT_4_COUNT_VAL:
0421         count = DP83869_DOWNSHIFT_4_COUNT;
0422         break;
0423     case DP83869_DOWNSHIFT_8_COUNT_VAL:
0424         count = DP83869_DOWNSHIFT_8_COUNT;
0425         break;
0426     default:
0427         return -EINVAL;
0428     }
0429 
0430     *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
0431 
0432     return 0;
0433 }
0434 
0435 static int dp83869_set_downshift(struct phy_device *phydev, u8 cnt)
0436 {
0437     int val, count;
0438 
0439     if (cnt > DP83869_DOWNSHIFT_8_COUNT)
0440         return -EINVAL;
0441 
0442     if (!cnt)
0443         return phy_clear_bits(phydev, DP83869_CFG2,
0444                       DP83869_DOWNSHIFT_EN);
0445 
0446     switch (cnt) {
0447     case DP83869_DOWNSHIFT_1_COUNT:
0448         count = DP83869_DOWNSHIFT_1_COUNT_VAL;
0449         break;
0450     case DP83869_DOWNSHIFT_2_COUNT:
0451         count = DP83869_DOWNSHIFT_2_COUNT_VAL;
0452         break;
0453     case DP83869_DOWNSHIFT_4_COUNT:
0454         count = DP83869_DOWNSHIFT_4_COUNT_VAL;
0455         break;
0456     case DP83869_DOWNSHIFT_8_COUNT:
0457         count = DP83869_DOWNSHIFT_8_COUNT_VAL;
0458         break;
0459     default:
0460         phydev_err(phydev,
0461                "Downshift count must be 1, 2, 4 or 8\n");
0462         return -EINVAL;
0463     }
0464 
0465     val = DP83869_DOWNSHIFT_EN;
0466     val |= FIELD_PREP(DP83869_DOWNSHIFT_ATTEMPT_MASK, count);
0467 
0468     return phy_modify(phydev, DP83869_CFG2,
0469               DP83869_DOWNSHIFT_EN | DP83869_DOWNSHIFT_ATTEMPT_MASK,
0470               val);
0471 }
0472 
0473 static int dp83869_get_tunable(struct phy_device *phydev,
0474                    struct ethtool_tunable *tuna, void *data)
0475 {
0476     switch (tuna->id) {
0477     case ETHTOOL_PHY_DOWNSHIFT:
0478         return dp83869_get_downshift(phydev, data);
0479     default:
0480         return -EOPNOTSUPP;
0481     }
0482 }
0483 
0484 static int dp83869_set_tunable(struct phy_device *phydev,
0485                    struct ethtool_tunable *tuna, const void *data)
0486 {
0487     switch (tuna->id) {
0488     case ETHTOOL_PHY_DOWNSHIFT:
0489         return dp83869_set_downshift(phydev, *(const u8 *)data);
0490     default:
0491         return -EOPNOTSUPP;
0492     }
0493 }
0494 
0495 static int dp83869_config_port_mirroring(struct phy_device *phydev)
0496 {
0497     struct dp83869_private *dp83869 = phydev->priv;
0498 
0499     if (dp83869->port_mirroring == DP83869_PORT_MIRRORING_EN)
0500         return phy_set_bits_mmd(phydev, DP83869_DEVADDR,
0501                     DP83869_GEN_CFG3,
0502                     DP83869_CFG3_PORT_MIRROR_EN);
0503     else
0504         return phy_clear_bits_mmd(phydev, DP83869_DEVADDR,
0505                       DP83869_GEN_CFG3,
0506                       DP83869_CFG3_PORT_MIRROR_EN);
0507 }
0508 
0509 static int dp83869_set_strapped_mode(struct phy_device *phydev)
0510 {
0511     struct dp83869_private *dp83869 = phydev->priv;
0512     int val;
0513 
0514     val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
0515     if (val < 0)
0516         return val;
0517 
0518     dp83869->mode = val & DP83869_STRAP_OP_MODE_MASK;
0519 
0520     return 0;
0521 }
0522 
0523 #if IS_ENABLED(CONFIG_OF_MDIO)
0524 static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
0525                          1750, 2000, 2250, 2500, 2750, 3000,
0526                          3250, 3500, 3750, 4000};
0527 
0528 static int dp83869_of_init(struct phy_device *phydev)
0529 {
0530     struct dp83869_private *dp83869 = phydev->priv;
0531     struct device *dev = &phydev->mdio.dev;
0532     struct device_node *of_node = dev->of_node;
0533     int delay_size = ARRAY_SIZE(dp83869_internal_delay);
0534     int ret;
0535 
0536     if (!of_node)
0537         return -ENODEV;
0538 
0539     dp83869->io_impedance = -EINVAL;
0540 
0541     /* Optional configuration */
0542     ret = of_property_read_u32(of_node, "ti,clk-output-sel",
0543                    &dp83869->clk_output_sel);
0544     if (ret || dp83869->clk_output_sel > DP83869_CLK_O_SEL_REF_CLK)
0545         dp83869->clk_output_sel = DP83869_CLK_O_SEL_REF_CLK;
0546 
0547     ret = of_property_read_u32(of_node, "ti,op-mode", &dp83869->mode);
0548     if (ret == 0) {
0549         if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
0550             dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
0551             return -EINVAL;
0552     } else {
0553         ret = dp83869_set_strapped_mode(phydev);
0554         if (ret)
0555             return ret;
0556     }
0557 
0558     if (of_property_read_bool(of_node, "ti,max-output-impedance"))
0559         dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MAX;
0560     else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
0561         dp83869->io_impedance = DP83869_IO_MUX_CFG_IO_IMPEDANCE_MIN;
0562 
0563     if (of_property_read_bool(of_node, "enet-phy-lane-swap")) {
0564         dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
0565     } else {
0566         /* If the lane swap is not in the DT then check the straps */
0567         ret = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_STRAP_STS1);
0568         if (ret < 0)
0569             return ret;
0570 
0571         if (ret & DP83869_STRAP_MIRROR_ENABLED)
0572             dp83869->port_mirroring = DP83869_PORT_MIRRORING_EN;
0573         else
0574             dp83869->port_mirroring = DP83869_PORT_MIRRORING_DIS;
0575 
0576         ret = 0;
0577     }
0578 
0579     if (of_property_read_u32(of_node, "rx-fifo-depth",
0580                  &dp83869->rx_fifo_depth))
0581         dp83869->rx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
0582 
0583     if (of_property_read_u32(of_node, "tx-fifo-depth",
0584                  &dp83869->tx_fifo_depth))
0585         dp83869->tx_fifo_depth = DP83869_PHYCR_FIFO_DEPTH_4_B_NIB;
0586 
0587     dp83869->rx_int_delay = phy_get_internal_delay(phydev, dev,
0588                                &dp83869_internal_delay[0],
0589                                delay_size, true);
0590     if (dp83869->rx_int_delay < 0)
0591         dp83869->rx_int_delay =
0592                 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
0593 
0594     dp83869->tx_int_delay = phy_get_internal_delay(phydev, dev,
0595                                &dp83869_internal_delay[0],
0596                                delay_size, false);
0597     if (dp83869->tx_int_delay < 0)
0598         dp83869->tx_int_delay =
0599                 dp83869_internal_delay[DP83869_CLK_DELAY_DEF];
0600 
0601     return ret;
0602 }
0603 #else
0604 static int dp83869_of_init(struct phy_device *phydev)
0605 {
0606     return dp83869_set_strapped_mode(phydev);
0607 }
0608 #endif /* CONFIG_OF_MDIO */
0609 
0610 static int dp83869_configure_rgmii(struct phy_device *phydev,
0611                    struct dp83869_private *dp83869)
0612 {
0613     int ret = 0, val;
0614 
0615     if (phy_interface_is_rgmii(phydev)) {
0616         val = phy_read(phydev, MII_DP83869_PHYCTRL);
0617         if (val < 0)
0618             return val;
0619 
0620         val &= ~DP83869_PHYCR_FIFO_DEPTH_MASK;
0621         val |= (dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT);
0622         val |= (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT);
0623 
0624         ret = phy_write(phydev, MII_DP83869_PHYCTRL, val);
0625         if (ret)
0626             return ret;
0627     }
0628 
0629     if (dp83869->io_impedance >= 0)
0630         ret = phy_modify_mmd(phydev, DP83869_DEVADDR,
0631                      DP83869_IO_MUX_CFG,
0632                      DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL,
0633                      dp83869->io_impedance &
0634                      DP83869_IO_MUX_CFG_IO_IMPEDANCE_CTRL);
0635 
0636     return ret;
0637 }
0638 
0639 static int dp83869_configure_fiber(struct phy_device *phydev,
0640                    struct dp83869_private *dp83869)
0641 {
0642     int bmcr;
0643     int ret;
0644 
0645     /* Only allow advertising what this PHY supports */
0646     linkmode_and(phydev->advertising, phydev->advertising,
0647              phydev->supported);
0648 
0649     linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
0650     linkmode_set_bit(ADVERTISED_FIBRE, phydev->advertising);
0651 
0652     if (dp83869->mode == DP83869_RGMII_1000_BASE) {
0653         linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
0654                  phydev->supported);
0655     } else {
0656         linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT,
0657                  phydev->supported);
0658         linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
0659                  phydev->supported);
0660 
0661         /* Auto neg is not supported in 100base FX mode */
0662         bmcr = phy_read(phydev, MII_BMCR);
0663         if (bmcr < 0)
0664             return bmcr;
0665 
0666         phydev->autoneg = AUTONEG_DISABLE;
0667         linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
0668         linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->advertising);
0669 
0670         if (bmcr & BMCR_ANENABLE) {
0671             ret =  phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
0672             if (ret < 0)
0673                 return ret;
0674         }
0675     }
0676 
0677     /* Update advertising from supported */
0678     linkmode_or(phydev->advertising, phydev->advertising,
0679             phydev->supported);
0680 
0681     return 0;
0682 }
0683 
0684 static int dp83869_configure_mode(struct phy_device *phydev,
0685                   struct dp83869_private *dp83869)
0686 {
0687     int phy_ctrl_val;
0688     int ret;
0689 
0690     if (dp83869->mode < DP83869_RGMII_COPPER_ETHERNET ||
0691         dp83869->mode > DP83869_SGMII_COPPER_ETHERNET)
0692         return -EINVAL;
0693 
0694     /* Below init sequence for each operational mode is defined in
0695      * section 9.4.8 of the datasheet.
0696      */
0697     ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
0698                 dp83869->mode);
0699     if (ret)
0700         return ret;
0701 
0702     ret = phy_write(phydev, MII_BMCR, MII_DP83869_BMCR_DEFAULT);
0703     if (ret)
0704         return ret;
0705 
0706     phy_ctrl_val = (dp83869->rx_fifo_depth << DP83869_RX_FIFO_SHIFT |
0707             dp83869->tx_fifo_depth << DP83869_TX_FIFO_SHIFT |
0708             DP83869_PHY_CTRL_DEFAULT);
0709 
0710     switch (dp83869->mode) {
0711     case DP83869_RGMII_COPPER_ETHERNET:
0712         ret = phy_write(phydev, MII_DP83869_PHYCTRL,
0713                 phy_ctrl_val);
0714         if (ret)
0715             return ret;
0716 
0717         ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
0718         if (ret)
0719             return ret;
0720 
0721         ret = dp83869_configure_rgmii(phydev, dp83869);
0722         if (ret)
0723             return ret;
0724         break;
0725     case DP83869_RGMII_SGMII_BRIDGE:
0726         ret = phy_modify_mmd(phydev, DP83869_DEVADDR, DP83869_OP_MODE,
0727                      DP83869_SGMII_RGMII_BRIDGE,
0728                      DP83869_SGMII_RGMII_BRIDGE);
0729         if (ret)
0730             return ret;
0731 
0732         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0733                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
0734         if (ret)
0735             return ret;
0736 
0737         break;
0738     case DP83869_1000M_MEDIA_CONVERT:
0739         ret = phy_write(phydev, MII_DP83869_PHYCTRL,
0740                 phy_ctrl_val);
0741         if (ret)
0742             return ret;
0743 
0744         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0745                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
0746         if (ret)
0747             return ret;
0748         break;
0749     case DP83869_100M_MEDIA_CONVERT:
0750         ret = phy_write(phydev, MII_DP83869_PHYCTRL,
0751                 phy_ctrl_val);
0752         if (ret)
0753             return ret;
0754         break;
0755     case DP83869_SGMII_COPPER_ETHERNET:
0756         ret = phy_write(phydev, MII_DP83869_PHYCTRL,
0757                 phy_ctrl_val);
0758         if (ret)
0759             return ret;
0760 
0761         ret = phy_write(phydev, MII_CTRL1000, DP83869_CFG1_DEFAULT);
0762         if (ret)
0763             return ret;
0764 
0765         ret = phy_write_mmd(phydev, DP83869_DEVADDR,
0766                     DP83869_FX_CTRL, DP83869_FX_CTRL_DEFAULT);
0767         if (ret)
0768             return ret;
0769 
0770         break;
0771     case DP83869_RGMII_1000_BASE:
0772     case DP83869_RGMII_100_BASE:
0773         ret = dp83869_configure_fiber(phydev, dp83869);
0774         break;
0775     default:
0776         return -EINVAL;
0777     }
0778 
0779     return ret;
0780 }
0781 
0782 static int dp83869_config_init(struct phy_device *phydev)
0783 {
0784     struct dp83869_private *dp83869 = phydev->priv;
0785     int ret, val;
0786 
0787     /* Force speed optimization for the PHY even if it strapped */
0788     ret = phy_modify(phydev, DP83869_CFG2, DP83869_DOWNSHIFT_EN,
0789              DP83869_DOWNSHIFT_EN);
0790     if (ret)
0791         return ret;
0792 
0793     ret = dp83869_configure_mode(phydev, dp83869);
0794     if (ret)
0795         return ret;
0796 
0797     /* Enable Interrupt output INT_OE in CFG4 register */
0798     if (phy_interrupt_is_valid(phydev)) {
0799         val = phy_read(phydev, DP83869_CFG4);
0800         val |= DP83869_INT_OE;
0801         phy_write(phydev, DP83869_CFG4, val);
0802     }
0803 
0804     if (dp83869->port_mirroring != DP83869_PORT_MIRRORING_KEEP)
0805         dp83869_config_port_mirroring(phydev);
0806 
0807     /* Clock output selection if muxing property is set */
0808     if (dp83869->clk_output_sel != DP83869_CLK_O_SEL_REF_CLK)
0809         ret = phy_modify_mmd(phydev,
0810                      DP83869_DEVADDR, DP83869_IO_MUX_CFG,
0811                      DP83869_IO_MUX_CFG_CLK_O_SEL_MASK,
0812                      dp83869->clk_output_sel <<
0813                      DP83869_IO_MUX_CFG_CLK_O_SEL_SHIFT);
0814 
0815     if (phy_interface_is_rgmii(phydev)) {
0816         ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIIDCTL,
0817                     dp83869->rx_int_delay |
0818             dp83869->tx_int_delay << DP83869_RGMII_CLK_DELAY_SHIFT);
0819         if (ret)
0820             return ret;
0821 
0822         val = phy_read_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL);
0823         val |= (DP83869_RGMII_TX_CLK_DELAY_EN |
0824             DP83869_RGMII_RX_CLK_DELAY_EN);
0825 
0826         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
0827             val &= ~(DP83869_RGMII_TX_CLK_DELAY_EN |
0828                  DP83869_RGMII_RX_CLK_DELAY_EN);
0829 
0830         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
0831             val &= ~DP83869_RGMII_TX_CLK_DELAY_EN;
0832 
0833         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
0834             val &= ~DP83869_RGMII_RX_CLK_DELAY_EN;
0835 
0836         ret = phy_write_mmd(phydev, DP83869_DEVADDR, DP83869_RGMIICTL,
0837                     val);
0838     }
0839 
0840     return ret;
0841 }
0842 
0843 static int dp83869_probe(struct phy_device *phydev)
0844 {
0845     struct dp83869_private *dp83869;
0846     int ret;
0847 
0848     dp83869 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83869),
0849                    GFP_KERNEL);
0850     if (!dp83869)
0851         return -ENOMEM;
0852 
0853     phydev->priv = dp83869;
0854 
0855     ret = dp83869_of_init(phydev);
0856     if (ret)
0857         return ret;
0858 
0859     if (dp83869->mode == DP83869_RGMII_100_BASE ||
0860         dp83869->mode == DP83869_RGMII_1000_BASE)
0861         phydev->port = PORT_FIBRE;
0862 
0863     return dp83869_config_init(phydev);
0864 }
0865 
0866 static int dp83869_phy_reset(struct phy_device *phydev)
0867 {
0868     int ret;
0869 
0870     ret = phy_write(phydev, DP83869_CTRL, DP83869_SW_RESET);
0871     if (ret < 0)
0872         return ret;
0873 
0874     usleep_range(10, 20);
0875 
0876     /* Global sw reset sets all registers to default.
0877      * Need to set the registers in the PHY to the right config.
0878      */
0879     return dp83869_config_init(phydev);
0880 }
0881 
0882 
0883 #define DP83869_PHY_DRIVER(_id, _name)              \
0884 {                               \
0885     PHY_ID_MATCH_MODEL(_id),                \
0886     .name       = (_name),              \
0887     .probe          = dp83869_probe,            \
0888     .config_init    = dp83869_config_init,          \
0889     .soft_reset = dp83869_phy_reset,            \
0890     .config_intr    = dp83869_config_intr,          \
0891     .handle_interrupt = dp83869_handle_interrupt,       \
0892     .read_status    = dp83869_read_status,          \
0893     .get_tunable    = dp83869_get_tunable,          \
0894     .set_tunable    = dp83869_set_tunable,          \
0895     .get_wol    = dp83869_get_wol,          \
0896     .set_wol    = dp83869_set_wol,          \
0897     .suspend    = genphy_suspend,           \
0898     .resume     = genphy_resume,            \
0899 }
0900 
0901 static struct phy_driver dp83869_driver[] = {
0902     DP83869_PHY_DRIVER(DP83869_PHY_ID, "TI DP83869"),
0903     DP83869_PHY_DRIVER(DP83561_PHY_ID, "TI DP83561-SP"),
0904 
0905 };
0906 module_phy_driver(dp83869_driver);
0907 
0908 static struct mdio_device_id __maybe_unused dp83869_tbl[] = {
0909     { PHY_ID_MATCH_MODEL(DP83869_PHY_ID) },
0910     { PHY_ID_MATCH_MODEL(DP83561_PHY_ID) },
0911     { }
0912 };
0913 MODULE_DEVICE_TABLE(mdio, dp83869_tbl);
0914 
0915 MODULE_DESCRIPTION("Texas Instruments DP83869 PHY driver");
0916 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
0917 MODULE_LICENSE("GPL v2");
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