net/phy/dp83867.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Driver for the Texas Instruments DP83867 PHY
0003  *
0004  * Copyright (C) 2015 Texas Instruments Inc.
0005  */
0006
0007 #include <linux/ethtool.h>
0008 #include <linux/kernel.h>
0009 #include <linux/mii.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/phy.h>
0013 #include <linux/delay.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/etherdevice.h>
0016 #include <linux/bitfield.h>
0017 #include <linux/nvmem-consumer.h>
0018
0019 #include <dt-bindings/net/ti-dp83867.h>
0020
0021 #define DP83867_PHY_ID      0x2000a231
0022 #define DP83867_DEVADDR     0x1f
0023
0024 #define MII_DP83867_PHYCTRL 0x10
0025 #define MII_DP83867_PHYSTS  0x11
0026 #define MII_DP83867_MICR    0x12
0027 #define MII_DP83867_ISR     0x13
0028 #define DP83867_CFG2        0x14
0029 #define DP83867_CFG3        0x1e
0030 #define DP83867_CTRL        0x1f
0031
0032 /* Extended Registers */
0033 #define DP83867_FLD_THR_CFG 0x002e
0034 #define DP83867_CFG4        0x0031
0035 #define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
0036 #define DP83867_CFG4_SGMII_ANEG_TIMER_11MS   (3 << 5)
0037 #define DP83867_CFG4_SGMII_ANEG_TIMER_800US  (2 << 5)
0038 #define DP83867_CFG4_SGMII_ANEG_TIMER_2US    (1 << 5)
0039 #define DP83867_CFG4_SGMII_ANEG_TIMER_16MS   (0 << 5)
0040
0041 #define DP83867_RGMIICTL    0x0032
0042 #define DP83867_STRAP_STS1  0x006E
0043 #define DP83867_STRAP_STS2  0x006f
0044 #define DP83867_RGMIIDCTL   0x0086
0045 #define DP83867_RXFCFG      0x0134
0046 #define DP83867_RXFPMD1 0x0136
0047 #define DP83867_RXFPMD2 0x0137
0048 #define DP83867_RXFPMD3 0x0138
0049 #define DP83867_RXFSOP1 0x0139
0050 #define DP83867_RXFSOP2 0x013A
0051 #define DP83867_RXFSOP3 0x013B
0052 #define DP83867_IO_MUX_CFG  0x0170
0053 #define DP83867_SGMIICTL    0x00D3
0054 #define DP83867_10M_SGMII_CFG   0x016F
0055 #define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
0056
0057 #define DP83867_SW_RESET    BIT(15)
0058 #define DP83867_SW_RESTART  BIT(14)
0059
0060 /* MICR Interrupt bits */
0061 #define MII_DP83867_MICR_AN_ERR_INT_EN      BIT(15)
0062 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN  BIT(14)
0063 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
0064 #define MII_DP83867_MICR_PAGE_RXD_INT_EN    BIT(12)
0065 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
0066 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
0067 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
0068 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
0069 #define MII_DP83867_MICR_WOL_INT_EN     BIT(3)
0070 #define MII_DP83867_MICR_XGMII_ERR_INT_EN   BIT(2)
0071 #define MII_DP83867_MICR_POL_CHNG_INT_EN    BIT(1)
0072 #define MII_DP83867_MICR_JABBER_INT_EN      BIT(0)
0073
0074 /* RGMIICTL bits */
0075 #define DP83867_RGMII_TX_CLK_DELAY_EN       BIT(1)
0076 #define DP83867_RGMII_RX_CLK_DELAY_EN       BIT(0)
0077
0078 /* SGMIICTL bits */
0079 #define DP83867_SGMII_TYPE      BIT(14)
0080
0081 /* RXFCFG bits*/
0082 #define DP83867_WOL_MAGIC_EN        BIT(0)
0083 #define DP83867_WOL_BCAST_EN        BIT(2)
0084 #define DP83867_WOL_UCAST_EN        BIT(4)
0085 #define DP83867_WOL_SEC_EN      BIT(5)
0086 #define DP83867_WOL_ENH_MAC     BIT(7)
0087
0088 /* STRAP_STS1 bits */
0089 #define DP83867_STRAP_STS1_RESERVED     BIT(11)
0090
0091 /* STRAP_STS2 bits */
0092 #define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
0093 #define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT    4
0094 #define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
0095 #define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT    0
0096 #define DP83867_STRAP_STS2_CLK_SKEW_NONE    BIT(2)
0097 #define DP83867_STRAP_STS2_STRAP_FLD        BIT(10)
0098
0099 /* PHY CTRL bits */
0100 #define DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT   14
0101 #define DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT   12
0102 #define DP83867_PHYCR_FIFO_DEPTH_MAX        0x03
0103 #define DP83867_PHYCR_TX_FIFO_DEPTH_MASK    GENMASK(15, 14)
0104 #define DP83867_PHYCR_RX_FIFO_DEPTH_MASK    GENMASK(13, 12)
0105 #define DP83867_PHYCR_RESERVED_MASK     BIT(11)
0106 #define DP83867_PHYCR_FORCE_LINK_GOOD       BIT(10)
0107
0108 /* RGMIIDCTL bits */
0109 #define DP83867_RGMII_TX_CLK_DELAY_MAX      0xf
0110 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT    4
0111 #define DP83867_RGMII_TX_CLK_DELAY_INV  (DP83867_RGMII_TX_CLK_DELAY_MAX + 1)
0112 #define DP83867_RGMII_RX_CLK_DELAY_MAX      0xf
0113 #define DP83867_RGMII_RX_CLK_DELAY_SHIFT    0
0114 #define DP83867_RGMII_RX_CLK_DELAY_INV  (DP83867_RGMII_RX_CLK_DELAY_MAX + 1)
0115
0116 /* IO_MUX_CFG bits */
0117 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK    0x1f
0118 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
0119 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
0120 #define DP83867_IO_MUX_CFG_CLK_O_DISABLE    BIT(6)
0121 #define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK   (0x1f << 8)
0122 #define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT  8
0123
0124 /* PHY STS bits */
0125 #define DP83867_PHYSTS_1000         BIT(15)
0126 #define DP83867_PHYSTS_100          BIT(14)
0127 #define DP83867_PHYSTS_DUPLEX           BIT(13)
0128 #define DP83867_PHYSTS_LINK         BIT(10)
0129
0130 /* CFG2 bits */
0131 #define DP83867_DOWNSHIFT_EN        (BIT(8) | BIT(9))
0132 #define DP83867_DOWNSHIFT_ATTEMPT_MASK  (BIT(10) | BIT(11))
0133 #define DP83867_DOWNSHIFT_1_COUNT_VAL   0
0134 #define DP83867_DOWNSHIFT_2_COUNT_VAL   1
0135 #define DP83867_DOWNSHIFT_4_COUNT_VAL   2
0136 #define DP83867_DOWNSHIFT_8_COUNT_VAL   3
0137 #define DP83867_DOWNSHIFT_1_COUNT   1
0138 #define DP83867_DOWNSHIFT_2_COUNT   2
0139 #define DP83867_DOWNSHIFT_4_COUNT   4
0140 #define DP83867_DOWNSHIFT_8_COUNT   8
0141 #define DP83867_SGMII_AUTONEG_EN    BIT(7)
0142
0143 /* CFG3 bits */
0144 #define DP83867_CFG3_INT_OE         BIT(7)
0145 #define DP83867_CFG3_ROBUST_AUTO_MDIX       BIT(9)
0146
0147 /* CFG4 bits */
0148 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
0149
0150 /* FLD_THR_CFG */
0151 #define DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK    0x7
0152
0153 enum {
0154     DP83867_PORT_MIRROING_KEEP,
0155     DP83867_PORT_MIRROING_EN,
0156     DP83867_PORT_MIRROING_DIS,
0157 };
0158
0159 struct dp83867_private {
0160     u32 rx_id_delay;
0161     u32 tx_id_delay;
0162     u32 tx_fifo_depth;
0163     u32 rx_fifo_depth;
0164     int io_impedance;
0165     int port_mirroring;
0166     bool rxctrl_strap_quirk;
0167     bool set_clk_output;
0168     u32 clk_output_sel;
0169     bool sgmii_ref_clk_en;
0170 };
0171
0172 static int dp83867_ack_interrupt(struct phy_device *phydev)
0173 {
0174     int err = phy_read(phydev, MII_DP83867_ISR);
0175
0176     if (err < 0)
0177         return err;
0178
0179     return 0;
0180 }
0181
0182 static int dp83867_set_wol(struct phy_device *phydev,
0183                struct ethtool_wolinfo *wol)
0184 {
0185     struct net_device *ndev = phydev->attached_dev;
0186     u16 val_rxcfg, val_micr;
0187     const u8 *mac;
0188
0189     val_rxcfg = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
0190     val_micr = phy_read(phydev, MII_DP83867_MICR);
0191
0192     if (wol->wolopts & (WAKE_MAGIC | WAKE_MAGICSECURE | WAKE_UCAST |
0193                 WAKE_BCAST)) {
0194         val_rxcfg |= DP83867_WOL_ENH_MAC;
0195         val_micr |= MII_DP83867_MICR_WOL_INT_EN;
0196
0197         if (wol->wolopts & WAKE_MAGIC) {
0198             mac = (const u8 *)ndev->dev_addr;
0199
0200             if (!is_valid_ether_addr(mac))
0201                 return -EINVAL;
0202
0203             phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD1,
0204                       (mac[1] << 8 | mac[0]));
0205             phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD2,
0206                       (mac[3] << 8 | mac[2]));
0207             phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFPMD3,
0208                       (mac[5] << 8 | mac[4]));
0209
0210             val_rxcfg |= DP83867_WOL_MAGIC_EN;
0211         } else {
0212             val_rxcfg &= ~DP83867_WOL_MAGIC_EN;
0213         }
0214
0215         if (wol->wolopts & WAKE_MAGICSECURE) {
0216             phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP1,
0217                       (wol->sopass[1] << 8) | wol->sopass[0]);
0218             phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP2,
0219                       (wol->sopass[3] << 8) | wol->sopass[2]);
0220             phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFSOP3,
0221                       (wol->sopass[5] << 8) | wol->sopass[4]);
0222
0223             val_rxcfg |= DP83867_WOL_SEC_EN;
0224         } else {
0225             val_rxcfg &= ~DP83867_WOL_SEC_EN;
0226         }
0227
0228         if (wol->wolopts & WAKE_UCAST)
0229             val_rxcfg |= DP83867_WOL_UCAST_EN;
0230         else
0231             val_rxcfg &= ~DP83867_WOL_UCAST_EN;
0232
0233         if (wol->wolopts & WAKE_BCAST)
0234             val_rxcfg |= DP83867_WOL_BCAST_EN;
0235         else
0236             val_rxcfg &= ~DP83867_WOL_BCAST_EN;
0237     } else {
0238         val_rxcfg &= ~DP83867_WOL_ENH_MAC;
0239         val_micr &= ~MII_DP83867_MICR_WOL_INT_EN;
0240     }
0241
0242     phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG, val_rxcfg);
0243     phy_write(phydev, MII_DP83867_MICR, val_micr);
0244
0245     return 0;
0246 }
0247
0248 static void dp83867_get_wol(struct phy_device *phydev,
0249                 struct ethtool_wolinfo *wol)
0250 {
0251     u16 value, sopass_val;
0252
0253     wol->supported = (WAKE_UCAST | WAKE_BCAST | WAKE_MAGIC |
0254             WAKE_MAGICSECURE);
0255     wol->wolopts = 0;
0256
0257     value = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RXFCFG);
0258
0259     if (value & DP83867_WOL_UCAST_EN)
0260         wol->wolopts |= WAKE_UCAST;
0261
0262     if (value & DP83867_WOL_BCAST_EN)
0263         wol->wolopts |= WAKE_BCAST;
0264
0265     if (value & DP83867_WOL_MAGIC_EN)
0266         wol->wolopts |= WAKE_MAGIC;
0267
0268     if (value & DP83867_WOL_SEC_EN) {
0269         sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
0270                       DP83867_RXFSOP1);
0271         wol->sopass[0] = (sopass_val & 0xff);
0272         wol->sopass[1] = (sopass_val >> 8);
0273
0274         sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
0275                       DP83867_RXFSOP2);
0276         wol->sopass[2] = (sopass_val & 0xff);
0277         wol->sopass[3] = (sopass_val >> 8);
0278
0279         sopass_val = phy_read_mmd(phydev, DP83867_DEVADDR,
0280                       DP83867_RXFSOP3);
0281         wol->sopass[4] = (sopass_val & 0xff);
0282         wol->sopass[5] = (sopass_val >> 8);
0283
0284         wol->wolopts |= WAKE_MAGICSECURE;
0285     }
0286
0287     if (!(value & DP83867_WOL_ENH_MAC))
0288         wol->wolopts = 0;
0289 }
0290
0291 static int dp83867_config_intr(struct phy_device *phydev)
0292 {
0293     int micr_status, err;
0294
0295     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0296         err = dp83867_ack_interrupt(phydev);
0297         if (err)
0298             return err;
0299
0300         micr_status = phy_read(phydev, MII_DP83867_MICR);
0301         if (micr_status < 0)
0302             return micr_status;
0303
0304         micr_status |=
0305             (MII_DP83867_MICR_AN_ERR_INT_EN |
0306             MII_DP83867_MICR_SPEED_CHNG_INT_EN |
0307             MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
0308             MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
0309             MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
0310             MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
0311
0312         err = phy_write(phydev, MII_DP83867_MICR, micr_status);
0313     } else {
0314         micr_status = 0x0;
0315         err = phy_write(phydev, MII_DP83867_MICR, micr_status);
0316         if (err)
0317             return err;
0318
0319         err = dp83867_ack_interrupt(phydev);
0320     }
0321
0322     return err;
0323 }
0324
0325 static irqreturn_t dp83867_handle_interrupt(struct phy_device *phydev)
0326 {
0327     int irq_status, irq_enabled;
0328
0329     irq_status = phy_read(phydev, MII_DP83867_ISR);
0330     if (irq_status < 0) {
0331         phy_error(phydev);
0332         return IRQ_NONE;
0333     }
0334
0335     irq_enabled = phy_read(phydev, MII_DP83867_MICR);
0336     if (irq_enabled < 0) {
0337         phy_error(phydev);
0338         return IRQ_NONE;
0339     }
0340
0341     if (!(irq_status & irq_enabled))
0342         return IRQ_NONE;
0343
0344     phy_trigger_machine(phydev);
0345
0346     return IRQ_HANDLED;
0347 }
0348
0349 static int dp83867_read_status(struct phy_device *phydev)
0350 {
0351     int status = phy_read(phydev, MII_DP83867_PHYSTS);
0352     int ret;
0353
0354     ret = genphy_read_status(phydev);
0355     if (ret)
0356         return ret;
0357
0358     if (status < 0)
0359         return status;
0360
0361     if (status & DP83867_PHYSTS_DUPLEX)
0362         phydev->duplex = DUPLEX_FULL;
0363     else
0364         phydev->duplex = DUPLEX_HALF;
0365
0366     if (status & DP83867_PHYSTS_1000)
0367         phydev->speed = SPEED_1000;
0368     else if (status & DP83867_PHYSTS_100)
0369         phydev->speed = SPEED_100;
0370     else
0371         phydev->speed = SPEED_10;
0372
0373     return 0;
0374 }
0375
0376 static int dp83867_get_downshift(struct phy_device *phydev, u8 *data)
0377 {
0378     int val, cnt, enable, count;
0379
0380     val = phy_read(phydev, DP83867_CFG2);
0381     if (val < 0)
0382         return val;
0383
0384     enable = FIELD_GET(DP83867_DOWNSHIFT_EN, val);
0385     cnt = FIELD_GET(DP83867_DOWNSHIFT_ATTEMPT_MASK, val);
0386
0387     switch (cnt) {
0388     case DP83867_DOWNSHIFT_1_COUNT_VAL:
0389         count = DP83867_DOWNSHIFT_1_COUNT;
0390         break;
0391     case DP83867_DOWNSHIFT_2_COUNT_VAL:
0392         count = DP83867_DOWNSHIFT_2_COUNT;
0393         break;
0394     case DP83867_DOWNSHIFT_4_COUNT_VAL:
0395         count = DP83867_DOWNSHIFT_4_COUNT;
0396         break;
0397     case DP83867_DOWNSHIFT_8_COUNT_VAL:
0398         count = DP83867_DOWNSHIFT_8_COUNT;
0399         break;
0400     default:
0401         return -EINVAL;
0402     }
0403
0404     *data = enable ? count : DOWNSHIFT_DEV_DISABLE;
0405
0406     return 0;
0407 }
0408
0409 static int dp83867_set_downshift(struct phy_device *phydev, u8 cnt)
0410 {
0411     int val, count;
0412
0413     if (cnt > DP83867_DOWNSHIFT_8_COUNT)
0414         return -E2BIG;
0415
0416     if (!cnt)
0417         return phy_clear_bits(phydev, DP83867_CFG2,
0418                       DP83867_DOWNSHIFT_EN);
0419
0420     switch (cnt) {
0421     case DP83867_DOWNSHIFT_1_COUNT:
0422         count = DP83867_DOWNSHIFT_1_COUNT_VAL;
0423         break;
0424     case DP83867_DOWNSHIFT_2_COUNT:
0425         count = DP83867_DOWNSHIFT_2_COUNT_VAL;
0426         break;
0427     case DP83867_DOWNSHIFT_4_COUNT:
0428         count = DP83867_DOWNSHIFT_4_COUNT_VAL;
0429         break;
0430     case DP83867_DOWNSHIFT_8_COUNT:
0431         count = DP83867_DOWNSHIFT_8_COUNT_VAL;
0432         break;
0433     default:
0434         phydev_err(phydev,
0435                "Downshift count must be 1, 2, 4 or 8\n");
0436         return -EINVAL;
0437     }
0438
0439     val = DP83867_DOWNSHIFT_EN;
0440     val |= FIELD_PREP(DP83867_DOWNSHIFT_ATTEMPT_MASK, count);
0441
0442     return phy_modify(phydev, DP83867_CFG2,
0443               DP83867_DOWNSHIFT_EN | DP83867_DOWNSHIFT_ATTEMPT_MASK,
0444               val);
0445 }
0446
0447 static int dp83867_get_tunable(struct phy_device *phydev,
0448                    struct ethtool_tunable *tuna, void *data)
0449 {
0450     switch (tuna->id) {
0451     case ETHTOOL_PHY_DOWNSHIFT:
0452         return dp83867_get_downshift(phydev, data);
0453     default:
0454         return -EOPNOTSUPP;
0455     }
0456 }
0457
0458 static int dp83867_set_tunable(struct phy_device *phydev,
0459                    struct ethtool_tunable *tuna, const void *data)
0460 {
0461     switch (tuna->id) {
0462     case ETHTOOL_PHY_DOWNSHIFT:
0463         return dp83867_set_downshift(phydev, *(const u8 *)data);
0464     default:
0465         return -EOPNOTSUPP;
0466     }
0467 }
0468
0469 static int dp83867_config_port_mirroring(struct phy_device *phydev)
0470 {
0471     struct dp83867_private *dp83867 =
0472         (struct dp83867_private *)phydev->priv;
0473
0474     if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
0475         phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
0476                  DP83867_CFG4_PORT_MIRROR_EN);
0477     else
0478         phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
0479                    DP83867_CFG4_PORT_MIRROR_EN);
0480     return 0;
0481 }
0482
0483 static int dp83867_verify_rgmii_cfg(struct phy_device *phydev)
0484 {
0485     struct dp83867_private *dp83867 = phydev->priv;
0486
0487     /* Existing behavior was to use default pin strapping delay in rgmii
0488      * mode, but rgmii should have meant no delay.  Warn existing users.
0489      */
0490     if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
0491         const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR,
0492                          DP83867_STRAP_STS2);
0493         const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
0494                    DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
0495         const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
0496                    DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
0497
0498         if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
0499             rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
0500             phydev_warn(phydev,
0501                     "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
0502                     "Should be 'rgmii-id' to use internal delays txskew:%x rxskew:%x\n",
0503                     txskew, rxskew);
0504     }
0505
0506     /* RX delay *must* be specified if internal delay of RX is used. */
0507     if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
0508          phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) &&
0509          dp83867->rx_id_delay == DP83867_RGMII_RX_CLK_DELAY_INV) {
0510         phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
0511         return -EINVAL;
0512     }
0513
0514     /* TX delay *must* be specified if internal delay of TX is used. */
0515     if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
0516          phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) &&
0517          dp83867->tx_id_delay == DP83867_RGMII_TX_CLK_DELAY_INV) {
0518         phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
0519         return -EINVAL;
0520     }
0521
0522     return 0;
0523 }
0524
0525 #if IS_ENABLED(CONFIG_OF_MDIO)
0526 static int dp83867_of_init_io_impedance(struct phy_device *phydev)
0527 {
0528     struct dp83867_private *dp83867 = phydev->priv;
0529     struct device *dev = &phydev->mdio.dev;
0530     struct device_node *of_node = dev->of_node;
0531     struct nvmem_cell *cell;
0532     u8 *buf, val;
0533     int ret;
0534
0535     cell = of_nvmem_cell_get(of_node, "io_impedance_ctrl");
0536     if (IS_ERR(cell)) {
0537         ret = PTR_ERR(cell);
0538         if (ret != -ENOENT && ret != -EOPNOTSUPP)
0539             return phydev_err_probe(phydev, ret,
0540                         "failed to get nvmem cell io_impedance_ctrl\n");
0541
0542         /* If no nvmem cell, check for the boolean properties. */
0543         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
0544             dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
0545         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
0546             dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
0547         else
0548             dp83867->io_impedance = -1; /* leave at default */
0549
0550         return 0;
0551     }
0552
0553     buf = nvmem_cell_read(cell, NULL);
0554     nvmem_cell_put(cell);
0555
0556     if (IS_ERR(buf))
0557         return PTR_ERR(buf);
0558
0559     val = *buf;
0560     kfree(buf);
0561
0562     if ((val & DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK) != val) {
0563         phydev_err(phydev, "nvmem cell 'io_impedance_ctrl' contents out of range\n");
0564         return -ERANGE;
0565     }
0566     dp83867->io_impedance = val;
0567
0568     return 0;
0569 }
0570
0571 static int dp83867_of_init(struct phy_device *phydev)
0572 {
0573     struct dp83867_private *dp83867 = phydev->priv;
0574     struct device *dev = &phydev->mdio.dev;
0575     struct device_node *of_node = dev->of_node;
0576     int ret;
0577
0578     if (!of_node)
0579         return -ENODEV;
0580
0581     /* Optional configuration */
0582     ret = of_property_read_u32(of_node, "ti,clk-output-sel",
0583                    &dp83867->clk_output_sel);
0584     /* If not set, keep default */
0585     if (!ret) {
0586         dp83867->set_clk_output = true;
0587         /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
0588          * DP83867_CLK_O_SEL_OFF.
0589          */
0590         if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
0591             dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
0592             phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
0593                    dp83867->clk_output_sel);
0594             return -EINVAL;
0595         }
0596     }
0597
0598     ret = dp83867_of_init_io_impedance(phydev);
0599     if (ret)
0600         return ret;
0601
0602     dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
0603                                 "ti,dp83867-rxctrl-strap-quirk");
0604
0605     dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
0606                               "ti,sgmii-ref-clock-output-enable");
0607
0608     dp83867->rx_id_delay = DP83867_RGMII_RX_CLK_DELAY_INV;
0609     ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
0610                    &dp83867->rx_id_delay);
0611     if (!ret && dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
0612         phydev_err(phydev,
0613                "ti,rx-internal-delay value of %u out of range\n",
0614                dp83867->rx_id_delay);
0615         return -EINVAL;
0616     }
0617
0618     dp83867->tx_id_delay = DP83867_RGMII_TX_CLK_DELAY_INV;
0619     ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
0620                    &dp83867->tx_id_delay);
0621     if (!ret && dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
0622         phydev_err(phydev,
0623                "ti,tx-internal-delay value of %u out of range\n",
0624                dp83867->tx_id_delay);
0625         return -EINVAL;
0626     }
0627
0628     if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
0629         dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
0630
0631     if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
0632         dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
0633
0634     ret = of_property_read_u32(of_node, "ti,fifo-depth",
0635                    &dp83867->tx_fifo_depth);
0636     if (ret) {
0637         ret = of_property_read_u32(of_node, "tx-fifo-depth",
0638                        &dp83867->tx_fifo_depth);
0639         if (ret)
0640             dp83867->tx_fifo_depth =
0641                     DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
0642     }
0643
0644     if (dp83867->tx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
0645         phydev_err(phydev, "tx-fifo-depth value %u out of range\n",
0646                dp83867->tx_fifo_depth);
0647         return -EINVAL;
0648     }
0649
0650     ret = of_property_read_u32(of_node, "rx-fifo-depth",
0651                    &dp83867->rx_fifo_depth);
0652     if (ret)
0653         dp83867->rx_fifo_depth = DP83867_PHYCR_FIFO_DEPTH_4_B_NIB;
0654
0655     if (dp83867->rx_fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
0656         phydev_err(phydev, "rx-fifo-depth value %u out of range\n",
0657                dp83867->rx_fifo_depth);
0658         return -EINVAL;
0659     }
0660
0661     return 0;
0662 }
0663 #else
0664 static int dp83867_of_init(struct phy_device *phydev)
0665 {
0666     struct dp83867_private *dp83867 = phydev->priv;
0667     u16 delay;
0668
0669     /* For non-OF device, the RX and TX ID values are either strapped
0670      * or take from default value. So, we init RX & TX ID values here
0671      * so that the RGMIIDCTL is configured correctly later in
0672      * dp83867_config_init();
0673      */
0674     delay = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL);
0675     dp83867->rx_id_delay = delay & DP83867_RGMII_RX_CLK_DELAY_MAX;
0676     dp83867->tx_id_delay = (delay >> DP83867_RGMII_TX_CLK_DELAY_SHIFT) &
0677                    DP83867_RGMII_TX_CLK_DELAY_MAX;
0678
0679     /* Per datasheet, IO impedance is default to 50-ohm, so we set the
0680      * same here or else the default '0' means highest IO impedance
0681      * which is wrong.
0682      */
0683     dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN / 2;
0684
0685     return 0;
0686 }
0687 #endif /* CONFIG_OF_MDIO */
0688
0689 static int dp83867_probe(struct phy_device *phydev)
0690 {
0691     struct dp83867_private *dp83867;
0692
0693     dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
0694                    GFP_KERNEL);
0695     if (!dp83867)
0696         return -ENOMEM;
0697
0698     phydev->priv = dp83867;
0699
0700     return dp83867_of_init(phydev);
0701 }
0702
0703 static int dp83867_config_init(struct phy_device *phydev)
0704 {
0705     struct dp83867_private *dp83867 = phydev->priv;
0706     int ret, val, bs;
0707     u16 delay;
0708
0709     /* Force speed optimization for the PHY even if it strapped */
0710     ret = phy_modify(phydev, DP83867_CFG2, DP83867_DOWNSHIFT_EN,
0711              DP83867_DOWNSHIFT_EN);
0712     if (ret)
0713         return ret;
0714
0715     ret = dp83867_verify_rgmii_cfg(phydev);
0716     if (ret)
0717         return ret;
0718
0719     /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
0720     if (dp83867->rxctrl_strap_quirk)
0721         phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
0722                    BIT(7));
0723
0724     bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
0725     if (bs & DP83867_STRAP_STS2_STRAP_FLD) {
0726         /* When using strap to enable FLD, the ENERGY_LOST_FLD_THR will
0727          * be set to 0x2. This may causes the PHY link to be unstable -
0728          * the default value 0x1 need to be restored.
0729          */
0730         ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
0731                      DP83867_FLD_THR_CFG,
0732                      DP83867_FLD_THR_CFG_ENERGY_LOST_THR_MASK,
0733                      0x1);
0734         if (ret)
0735             return ret;
0736     }
0737
0738     if (phy_interface_is_rgmii(phydev) ||
0739         phydev->interface == PHY_INTERFACE_MODE_SGMII) {
0740         val = phy_read(phydev, MII_DP83867_PHYCTRL);
0741         if (val < 0)
0742             return val;
0743
0744         val &= ~DP83867_PHYCR_TX_FIFO_DEPTH_MASK;
0745         val |= (dp83867->tx_fifo_depth <<
0746             DP83867_PHYCR_TX_FIFO_DEPTH_SHIFT);
0747
0748         if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
0749             val &= ~DP83867_PHYCR_RX_FIFO_DEPTH_MASK;
0750             val |= (dp83867->rx_fifo_depth <<
0751                 DP83867_PHYCR_RX_FIFO_DEPTH_SHIFT);
0752         }
0753
0754         ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
0755         if (ret)
0756             return ret;
0757     }
0758
0759     if (phy_interface_is_rgmii(phydev)) {
0760         val = phy_read(phydev, MII_DP83867_PHYCTRL);
0761         if (val < 0)
0762             return val;
0763
0764         /* The code below checks if "port mirroring" N/A MODE4 has been
0765          * enabled during power on bootstrap.
0766          *
0767          * Such N/A mode enabled by mistake can put PHY IC in some
0768          * internal testing mode and disable RGMII transmission.
0769          *
0770          * In this particular case one needs to check STRAP_STS1
0771          * register's bit 11 (marked as RESERVED).
0772          */
0773
0774         bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
0775         if (bs & DP83867_STRAP_STS1_RESERVED)
0776             val &= ~DP83867_PHYCR_RESERVED_MASK;
0777
0778         ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
0779         if (ret)
0780             return ret;
0781
0782         /* If rgmii mode with no internal delay is selected, we do NOT use
0783          * aligned mode as one might expect.  Instead we use the PHY's default
0784          * based on pin strapping.  And the "mode 0" default is to *use*
0785          * internal delay with a value of 7 (2.00 ns).
0786          *
0787          * Set up RGMII delays
0788          */
0789         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
0790
0791         val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
0792         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
0793             val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
0794
0795         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
0796             val |= DP83867_RGMII_TX_CLK_DELAY_EN;
0797
0798         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
0799             val |= DP83867_RGMII_RX_CLK_DELAY_EN;
0800
0801         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
0802
0803         delay = 0;
0804         if (dp83867->rx_id_delay != DP83867_RGMII_RX_CLK_DELAY_INV)
0805             delay |= dp83867->rx_id_delay;
0806         if (dp83867->tx_id_delay != DP83867_RGMII_TX_CLK_DELAY_INV)
0807             delay |= dp83867->tx_id_delay <<
0808                  DP83867_RGMII_TX_CLK_DELAY_SHIFT;
0809
0810         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
0811                   delay);
0812     }
0813
0814     /* If specified, set io impedance */
0815     if (dp83867->io_impedance >= 0)
0816         phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
0817                    DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
0818                    dp83867->io_impedance);
0819
0820     if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
0821         /* For support SPEED_10 in SGMII mode
0822          * DP83867_10M_SGMII_RATE_ADAPT bit
0823          * has to be cleared by software. That
0824          * does not affect SPEED_100 and
0825          * SPEED_1000.
0826          */
0827         ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
0828                      DP83867_10M_SGMII_CFG,
0829                      DP83867_10M_SGMII_RATE_ADAPT_MASK,
0830                      0);
0831         if (ret)
0832             return ret;
0833
0834         /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
0835          * are 01). That is not enough to finalize autoneg on some
0836          * devices. Increase this timer duration to maximum 16ms.
0837          */
0838         ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
0839                      DP83867_CFG4,
0840                      DP83867_CFG4_SGMII_ANEG_MASK,
0841                      DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
0842
0843         if (ret)
0844             return ret;
0845
0846         val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
0847         /* SGMII type is set to 4-wire mode by default.
0848          * If we place appropriate property in dts (see above)
0849          * switch on 6-wire mode.
0850          */
0851         if (dp83867->sgmii_ref_clk_en)
0852             val |= DP83867_SGMII_TYPE;
0853         else
0854             val &= ~DP83867_SGMII_TYPE;
0855         phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
0856     }
0857
0858     val = phy_read(phydev, DP83867_CFG3);
0859     /* Enable Interrupt output INT_OE in CFG3 register */
0860     if (phy_interrupt_is_valid(phydev))
0861         val |= DP83867_CFG3_INT_OE;
0862
0863     val |= DP83867_CFG3_ROBUST_AUTO_MDIX;
0864     phy_write(phydev, DP83867_CFG3, val);
0865
0866     if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
0867         dp83867_config_port_mirroring(phydev);
0868
0869     /* Clock output selection if muxing property is set */
0870     if (dp83867->set_clk_output) {
0871         u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
0872
0873         if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
0874             val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
0875         } else {
0876             mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
0877             val = dp83867->clk_output_sel <<
0878                   DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
0879         }
0880
0881         phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
0882                    mask, val);
0883     }
0884
0885     return 0;
0886 }
0887
0888 static int dp83867_phy_reset(struct phy_device *phydev)
0889 {
0890     int err;
0891
0892     err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESTART);
0893     if (err < 0)
0894         return err;
0895
0896     usleep_range(10, 20);
0897
0898     return phy_modify(phydev, MII_DP83867_PHYCTRL,
0899              DP83867_PHYCR_FORCE_LINK_GOOD, 0);
0900 }
0901
0902 static void dp83867_link_change_notify(struct phy_device *phydev)
0903 {
0904     /* There is a limitation in DP83867 PHY device where SGMII AN is
0905      * only triggered once after the device is booted up. Even after the
0906      * PHY TPI is down and up again, SGMII AN is not triggered and
0907      * hence no new in-band message from PHY to MAC side SGMII.
0908      * This could cause an issue during power up, when PHY is up prior
0909      * to MAC. At this condition, once MAC side SGMII is up, MAC side
0910      * SGMII wouldn`t receive new in-band message from TI PHY with
0911      * correct link status, speed and duplex info.
0912      * Thus, implemented a SW solution here to retrigger SGMII Auto-Neg
0913      * whenever there is a link change.
0914      */
0915     if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
0916         int val = 0;
0917
0918         val = phy_clear_bits(phydev, DP83867_CFG2,
0919                      DP83867_SGMII_AUTONEG_EN);
0920         if (val < 0)
0921             return;
0922
0923         phy_set_bits(phydev, DP83867_CFG2,
0924                  DP83867_SGMII_AUTONEG_EN);
0925     }
0926 }
0927
0928 static struct phy_driver dp83867_driver[] = {
0929     {
0930         .phy_id     = DP83867_PHY_ID,
0931         .phy_id_mask    = 0xfffffff0,
0932         .name       = "TI DP83867",
0933         /* PHY_GBIT_FEATURES */
0934
0935         .probe          = dp83867_probe,
0936         .config_init    = dp83867_config_init,
0937         .soft_reset = dp83867_phy_reset,
0938
0939         .read_status    = dp83867_read_status,
0940         .get_tunable    = dp83867_get_tunable,
0941         .set_tunable    = dp83867_set_tunable,
0942
0943         .get_wol    = dp83867_get_wol,
0944         .set_wol    = dp83867_set_wol,
0945
0946         /* IRQ related */
0947         .config_intr    = dp83867_config_intr,
0948         .handle_interrupt = dp83867_handle_interrupt,
0949
0950         .suspend    = genphy_suspend,
0951         .resume     = genphy_resume,
0952
0953         .link_change_notify = dp83867_link_change_notify,
0954     },
0955 };
0956 module_phy_driver(dp83867_driver);
0957
0958 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
0959     { DP83867_PHY_ID, 0xfffffff0 },
0960     { }
0961 };
0962
0963 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
0964
0965 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
0966 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
0967 MODULE_LICENSE("GPL v2");