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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Driver for the National Semiconductor DP83640 PHYTER
0004  *
0005  * Copyright (C) 2010 OMICRON electronics GmbH
0006  */
0007 
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009 
0010 #include <linux/crc32.h>
0011 #include <linux/ethtool.h>
0012 #include <linux/kernel.h>
0013 #include <linux/list.h>
0014 #include <linux/mii.h>
0015 #include <linux/module.h>
0016 #include <linux/net_tstamp.h>
0017 #include <linux/netdevice.h>
0018 #include <linux/if_vlan.h>
0019 #include <linux/phy.h>
0020 #include <linux/ptp_classify.h>
0021 #include <linux/ptp_clock_kernel.h>
0022 
0023 #include "dp83640_reg.h"
0024 
0025 #define DP83640_PHY_ID  0x20005ce1
0026 #define PAGESEL     0x13
0027 #define MAX_RXTS    64
0028 #define N_EXT_TS    6
0029 #define N_PER_OUT   7
0030 #define PSF_PTPVER  2
0031 #define PSF_EVNT    0x4000
0032 #define PSF_RX      0x2000
0033 #define PSF_TX      0x1000
0034 #define EXT_EVENT   1
0035 #define CAL_EVENT   7
0036 #define CAL_TRIGGER 1
0037 #define DP83640_N_PINS  12
0038 
0039 #define MII_DP83640_MICR 0x11
0040 #define MII_DP83640_MISR 0x12
0041 
0042 #define MII_DP83640_MICR_OE 0x1
0043 #define MII_DP83640_MICR_IE 0x2
0044 
0045 #define MII_DP83640_MISR_RHF_INT_EN 0x01
0046 #define MII_DP83640_MISR_FHF_INT_EN 0x02
0047 #define MII_DP83640_MISR_ANC_INT_EN 0x04
0048 #define MII_DP83640_MISR_DUP_INT_EN 0x08
0049 #define MII_DP83640_MISR_SPD_INT_EN 0x10
0050 #define MII_DP83640_MISR_LINK_INT_EN 0x20
0051 #define MII_DP83640_MISR_ED_INT_EN 0x40
0052 #define MII_DP83640_MISR_LQ_INT_EN 0x80
0053 #define MII_DP83640_MISR_ANC_INT 0x400
0054 #define MII_DP83640_MISR_DUP_INT 0x800
0055 #define MII_DP83640_MISR_SPD_INT 0x1000
0056 #define MII_DP83640_MISR_LINK_INT 0x2000
0057 #define MII_DP83640_MISR_INT_MASK (MII_DP83640_MISR_ANC_INT |\
0058                    MII_DP83640_MISR_DUP_INT |\
0059                    MII_DP83640_MISR_SPD_INT |\
0060                    MII_DP83640_MISR_LINK_INT)
0061 
0062 /* phyter seems to miss the mark by 16 ns */
0063 #define ADJTIME_FIX 16
0064 
0065 #define SKB_TIMESTAMP_TIMEOUT   2 /* jiffies */
0066 
0067 #if defined(__BIG_ENDIAN)
0068 #define ENDIAN_FLAG 0
0069 #elif defined(__LITTLE_ENDIAN)
0070 #define ENDIAN_FLAG PSF_ENDIAN
0071 #endif
0072 
0073 struct dp83640_skb_info {
0074     int ptp_type;
0075     unsigned long tmo;
0076 };
0077 
0078 struct phy_rxts {
0079     u16 ns_lo;   /* ns[15:0] */
0080     u16 ns_hi;   /* overflow[1:0], ns[29:16] */
0081     u16 sec_lo;  /* sec[15:0] */
0082     u16 sec_hi;  /* sec[31:16] */
0083     u16 seqid;   /* sequenceId[15:0] */
0084     u16 msgtype; /* messageType[3:0], hash[11:0] */
0085 };
0086 
0087 struct phy_txts {
0088     u16 ns_lo;   /* ns[15:0] */
0089     u16 ns_hi;   /* overflow[1:0], ns[29:16] */
0090     u16 sec_lo;  /* sec[15:0] */
0091     u16 sec_hi;  /* sec[31:16] */
0092 };
0093 
0094 struct rxts {
0095     struct list_head list;
0096     unsigned long tmo;
0097     u64 ns;
0098     u16 seqid;
0099     u8  msgtype;
0100     u16 hash;
0101 };
0102 
0103 struct dp83640_clock;
0104 
0105 struct dp83640_private {
0106     struct list_head list;
0107     struct dp83640_clock *clock;
0108     struct phy_device *phydev;
0109     struct mii_timestamper mii_ts;
0110     struct delayed_work ts_work;
0111     int hwts_tx_en;
0112     int hwts_rx_en;
0113     int layer;
0114     int version;
0115     /* remember state of cfg0 during calibration */
0116     int cfg0;
0117     /* remember the last event time stamp */
0118     struct phy_txts edata;
0119     /* list of rx timestamps */
0120     struct list_head rxts;
0121     struct list_head rxpool;
0122     struct rxts rx_pool_data[MAX_RXTS];
0123     /* protects above three fields from concurrent access */
0124     spinlock_t rx_lock;
0125     /* queues of incoming and outgoing packets */
0126     struct sk_buff_head rx_queue;
0127     struct sk_buff_head tx_queue;
0128 };
0129 
0130 struct dp83640_clock {
0131     /* keeps the instance in the 'phyter_clocks' list */
0132     struct list_head list;
0133     /* we create one clock instance per MII bus */
0134     struct mii_bus *bus;
0135     /* protects extended registers from concurrent access */
0136     struct mutex extreg_lock;
0137     /* remembers which page was last selected */
0138     int page;
0139     /* our advertised capabilities */
0140     struct ptp_clock_info caps;
0141     /* protects the three fields below from concurrent access */
0142     struct mutex clock_lock;
0143     /* the one phyter from which we shall read */
0144     struct dp83640_private *chosen;
0145     /* list of the other attached phyters, not chosen */
0146     struct list_head phylist;
0147     /* reference to our PTP hardware clock */
0148     struct ptp_clock *ptp_clock;
0149 };
0150 
0151 /* globals */
0152 
0153 enum {
0154     CALIBRATE_GPIO,
0155     PEROUT_GPIO,
0156     EXTTS0_GPIO,
0157     EXTTS1_GPIO,
0158     EXTTS2_GPIO,
0159     EXTTS3_GPIO,
0160     EXTTS4_GPIO,
0161     EXTTS5_GPIO,
0162     GPIO_TABLE_SIZE
0163 };
0164 
0165 static int chosen_phy = -1;
0166 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
0167     1, 2, 3, 4, 8, 9, 10, 11
0168 };
0169 
0170 module_param(chosen_phy, int, 0444);
0171 module_param_array(gpio_tab, ushort, NULL, 0444);
0172 
0173 MODULE_PARM_DESC(chosen_phy,
0174     "The address of the PHY to use for the ancillary clock features");
0175 MODULE_PARM_DESC(gpio_tab,
0176     "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
0177 
0178 static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
0179 {
0180     int i, index;
0181 
0182     for (i = 0; i < DP83640_N_PINS; i++) {
0183         snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
0184         pd[i].index = i;
0185     }
0186 
0187     for (i = 0; i < GPIO_TABLE_SIZE; i++) {
0188         if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
0189             pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
0190             return;
0191         }
0192     }
0193 
0194     index = gpio_tab[CALIBRATE_GPIO] - 1;
0195     pd[index].func = PTP_PF_PHYSYNC;
0196     pd[index].chan = 0;
0197 
0198     index = gpio_tab[PEROUT_GPIO] - 1;
0199     pd[index].func = PTP_PF_PEROUT;
0200     pd[index].chan = 0;
0201 
0202     for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
0203         index = gpio_tab[i] - 1;
0204         pd[index].func = PTP_PF_EXTTS;
0205         pd[index].chan = i - EXTTS0_GPIO;
0206     }
0207 }
0208 
0209 /* a list of clocks and a mutex to protect it */
0210 static LIST_HEAD(phyter_clocks);
0211 static DEFINE_MUTEX(phyter_clocks_lock);
0212 
0213 static void rx_timestamp_work(struct work_struct *work);
0214 
0215 /* extended register access functions */
0216 
0217 #define BROADCAST_ADDR 31
0218 
0219 static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
0220                   u16 val)
0221 {
0222     return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
0223 }
0224 
0225 /* Caller must hold extreg_lock. */
0226 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
0227 {
0228     struct dp83640_private *dp83640 = phydev->priv;
0229     int val;
0230 
0231     if (dp83640->clock->page != page) {
0232         broadcast_write(phydev, PAGESEL, page);
0233         dp83640->clock->page = page;
0234     }
0235     val = phy_read(phydev, regnum);
0236 
0237     return val;
0238 }
0239 
0240 /* Caller must hold extreg_lock. */
0241 static void ext_write(int broadcast, struct phy_device *phydev,
0242               int page, u32 regnum, u16 val)
0243 {
0244     struct dp83640_private *dp83640 = phydev->priv;
0245 
0246     if (dp83640->clock->page != page) {
0247         broadcast_write(phydev, PAGESEL, page);
0248         dp83640->clock->page = page;
0249     }
0250     if (broadcast)
0251         broadcast_write(phydev, regnum, val);
0252     else
0253         phy_write(phydev, regnum, val);
0254 }
0255 
0256 /* Caller must hold extreg_lock. */
0257 static int tdr_write(int bc, struct phy_device *dev,
0258              const struct timespec64 *ts, u16 cmd)
0259 {
0260     ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0]  */
0261     ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);   /* ns[31:16] */
0262     ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
0263     ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16);    /* sec[31:16]*/
0264 
0265     ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
0266 
0267     return 0;
0268 }
0269 
0270 /* convert phy timestamps into driver timestamps */
0271 
0272 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
0273 {
0274     u32 sec;
0275 
0276     sec = p->sec_lo;
0277     sec |= p->sec_hi << 16;
0278 
0279     rxts->ns = p->ns_lo;
0280     rxts->ns |= (p->ns_hi & 0x3fff) << 16;
0281     rxts->ns += ((u64)sec) * 1000000000ULL;
0282     rxts->seqid = p->seqid;
0283     rxts->msgtype = (p->msgtype >> 12) & 0xf;
0284     rxts->hash = p->msgtype & 0x0fff;
0285     rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
0286 }
0287 
0288 static u64 phy2txts(struct phy_txts *p)
0289 {
0290     u64 ns;
0291     u32 sec;
0292 
0293     sec = p->sec_lo;
0294     sec |= p->sec_hi << 16;
0295 
0296     ns = p->ns_lo;
0297     ns |= (p->ns_hi & 0x3fff) << 16;
0298     ns += ((u64)sec) * 1000000000ULL;
0299 
0300     return ns;
0301 }
0302 
0303 static int periodic_output(struct dp83640_clock *clock,
0304                struct ptp_clock_request *clkreq, bool on,
0305                int trigger)
0306 {
0307     struct dp83640_private *dp83640 = clock->chosen;
0308     struct phy_device *phydev = dp83640->phydev;
0309     u32 sec, nsec, pwidth;
0310     u16 gpio, ptp_trig, val;
0311 
0312     if (on) {
0313         gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
0314                     trigger);
0315         if (gpio < 1)
0316             return -EINVAL;
0317     } else {
0318         gpio = 0;
0319     }
0320 
0321     ptp_trig = TRIG_WR |
0322         (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
0323         (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
0324         TRIG_PER |
0325         TRIG_PULSE;
0326 
0327     val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
0328 
0329     if (!on) {
0330         val |= TRIG_DIS;
0331         mutex_lock(&clock->extreg_lock);
0332         ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
0333         ext_write(0, phydev, PAGE4, PTP_CTL, val);
0334         mutex_unlock(&clock->extreg_lock);
0335         return 0;
0336     }
0337 
0338     sec = clkreq->perout.start.sec;
0339     nsec = clkreq->perout.start.nsec;
0340     pwidth = clkreq->perout.period.sec * 1000000000UL;
0341     pwidth += clkreq->perout.period.nsec;
0342     pwidth /= 2;
0343 
0344     mutex_lock(&clock->extreg_lock);
0345 
0346     ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
0347 
0348     /*load trigger*/
0349     val |= TRIG_LOAD;
0350     ext_write(0, phydev, PAGE4, PTP_CTL, val);
0351     ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff);   /* ns[15:0] */
0352     ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16);      /* ns[31:16] */
0353     ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff);    /* sec[15:0] */
0354     ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16);       /* sec[31:16] */
0355     ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
0356     ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);    /* ns[31:16] */
0357     /* Triggers 0 and 1 has programmable pulsewidth2 */
0358     if (trigger < 2) {
0359         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
0360         ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
0361     }
0362 
0363     /*enable trigger*/
0364     val &= ~TRIG_LOAD;
0365     val |= TRIG_EN;
0366     ext_write(0, phydev, PAGE4, PTP_CTL, val);
0367 
0368     mutex_unlock(&clock->extreg_lock);
0369     return 0;
0370 }
0371 
0372 /* ptp clock methods */
0373 
0374 static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
0375 {
0376     struct dp83640_clock *clock =
0377         container_of(ptp, struct dp83640_clock, caps);
0378     struct phy_device *phydev = clock->chosen->phydev;
0379     u64 rate;
0380     int neg_adj = 0;
0381     u16 hi, lo;
0382 
0383     if (scaled_ppm < 0) {
0384         neg_adj = 1;
0385         scaled_ppm = -scaled_ppm;
0386     }
0387     rate = scaled_ppm;
0388     rate <<= 13;
0389     rate = div_u64(rate, 15625);
0390 
0391     hi = (rate >> 16) & PTP_RATE_HI_MASK;
0392     if (neg_adj)
0393         hi |= PTP_RATE_DIR;
0394 
0395     lo = rate & 0xffff;
0396 
0397     mutex_lock(&clock->extreg_lock);
0398 
0399     ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
0400     ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
0401 
0402     mutex_unlock(&clock->extreg_lock);
0403 
0404     return 0;
0405 }
0406 
0407 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
0408 {
0409     struct dp83640_clock *clock =
0410         container_of(ptp, struct dp83640_clock, caps);
0411     struct phy_device *phydev = clock->chosen->phydev;
0412     struct timespec64 ts;
0413     int err;
0414 
0415     delta += ADJTIME_FIX;
0416 
0417     ts = ns_to_timespec64(delta);
0418 
0419     mutex_lock(&clock->extreg_lock);
0420 
0421     err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
0422 
0423     mutex_unlock(&clock->extreg_lock);
0424 
0425     return err;
0426 }
0427 
0428 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
0429                    struct timespec64 *ts)
0430 {
0431     struct dp83640_clock *clock =
0432         container_of(ptp, struct dp83640_clock, caps);
0433     struct phy_device *phydev = clock->chosen->phydev;
0434     unsigned int val[4];
0435 
0436     mutex_lock(&clock->extreg_lock);
0437 
0438     ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
0439 
0440     val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
0441     val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
0442     val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
0443     val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
0444 
0445     mutex_unlock(&clock->extreg_lock);
0446 
0447     ts->tv_nsec = val[0] | (val[1] << 16);
0448     ts->tv_sec  = val[2] | (val[3] << 16);
0449 
0450     return 0;
0451 }
0452 
0453 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
0454                    const struct timespec64 *ts)
0455 {
0456     struct dp83640_clock *clock =
0457         container_of(ptp, struct dp83640_clock, caps);
0458     struct phy_device *phydev = clock->chosen->phydev;
0459     int err;
0460 
0461     mutex_lock(&clock->extreg_lock);
0462 
0463     err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
0464 
0465     mutex_unlock(&clock->extreg_lock);
0466 
0467     return err;
0468 }
0469 
0470 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
0471                   struct ptp_clock_request *rq, int on)
0472 {
0473     struct dp83640_clock *clock =
0474         container_of(ptp, struct dp83640_clock, caps);
0475     struct phy_device *phydev = clock->chosen->phydev;
0476     unsigned int index;
0477     u16 evnt, event_num, gpio_num;
0478 
0479     switch (rq->type) {
0480     case PTP_CLK_REQ_EXTTS:
0481         /* Reject requests with unsupported flags */
0482         if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
0483                     PTP_RISING_EDGE |
0484                     PTP_FALLING_EDGE |
0485                     PTP_STRICT_FLAGS))
0486             return -EOPNOTSUPP;
0487 
0488         /* Reject requests to enable time stamping on both edges. */
0489         if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
0490             (rq->extts.flags & PTP_ENABLE_FEATURE) &&
0491             (rq->extts.flags & PTP_EXTTS_EDGES) == PTP_EXTTS_EDGES)
0492             return -EOPNOTSUPP;
0493 
0494         index = rq->extts.index;
0495         if (index >= N_EXT_TS)
0496             return -EINVAL;
0497         event_num = EXT_EVENT + index;
0498         evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
0499         if (on) {
0500             gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
0501                             PTP_PF_EXTTS, index);
0502             if (gpio_num < 1)
0503                 return -EINVAL;
0504             evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
0505             if (rq->extts.flags & PTP_FALLING_EDGE)
0506                 evnt |= EVNT_FALL;
0507             else
0508                 evnt |= EVNT_RISE;
0509         }
0510         mutex_lock(&clock->extreg_lock);
0511         ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
0512         mutex_unlock(&clock->extreg_lock);
0513         return 0;
0514 
0515     case PTP_CLK_REQ_PEROUT:
0516         /* Reject requests with unsupported flags */
0517         if (rq->perout.flags)
0518             return -EOPNOTSUPP;
0519         if (rq->perout.index >= N_PER_OUT)
0520             return -EINVAL;
0521         return periodic_output(clock, rq, on, rq->perout.index);
0522 
0523     default:
0524         break;
0525     }
0526 
0527     return -EOPNOTSUPP;
0528 }
0529 
0530 static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
0531                   enum ptp_pin_function func, unsigned int chan)
0532 {
0533     struct dp83640_clock *clock =
0534         container_of(ptp, struct dp83640_clock, caps);
0535 
0536     if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
0537         !list_empty(&clock->phylist))
0538         return 1;
0539 
0540     if (func == PTP_PF_PHYSYNC)
0541         return 1;
0542 
0543     return 0;
0544 }
0545 
0546 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
0547 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
0548 
0549 static void enable_status_frames(struct phy_device *phydev, bool on)
0550 {
0551     struct dp83640_private *dp83640 = phydev->priv;
0552     struct dp83640_clock *clock = dp83640->clock;
0553     u16 cfg0 = 0, ver;
0554 
0555     if (on)
0556         cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
0557 
0558     ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
0559 
0560     mutex_lock(&clock->extreg_lock);
0561 
0562     ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
0563     ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
0564 
0565     mutex_unlock(&clock->extreg_lock);
0566 
0567     if (!phydev->attached_dev) {
0568         phydev_warn(phydev,
0569                 "expected to find an attached netdevice\n");
0570         return;
0571     }
0572 
0573     if (on) {
0574         if (dev_mc_add(phydev->attached_dev, status_frame_dst))
0575             phydev_warn(phydev, "failed to add mc address\n");
0576     } else {
0577         if (dev_mc_del(phydev->attached_dev, status_frame_dst))
0578             phydev_warn(phydev, "failed to delete mc address\n");
0579     }
0580 }
0581 
0582 static bool is_status_frame(struct sk_buff *skb, int type)
0583 {
0584     struct ethhdr *h = eth_hdr(skb);
0585 
0586     if (PTP_CLASS_V2_L2 == type &&
0587         !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
0588         return true;
0589     else
0590         return false;
0591 }
0592 
0593 static int expired(struct rxts *rxts)
0594 {
0595     return time_after(jiffies, rxts->tmo);
0596 }
0597 
0598 /* Caller must hold rx_lock. */
0599 static void prune_rx_ts(struct dp83640_private *dp83640)
0600 {
0601     struct list_head *this, *next;
0602     struct rxts *rxts;
0603 
0604     list_for_each_safe(this, next, &dp83640->rxts) {
0605         rxts = list_entry(this, struct rxts, list);
0606         if (expired(rxts)) {
0607             list_del_init(&rxts->list);
0608             list_add(&rxts->list, &dp83640->rxpool);
0609         }
0610     }
0611 }
0612 
0613 /* synchronize the phyters so they act as one clock */
0614 
0615 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
0616 {
0617     int val;
0618 
0619     phy_write(phydev, PAGESEL, 0);
0620     val = phy_read(phydev, PHYCR2);
0621     if (on)
0622         val |= BC_WRITE;
0623     else
0624         val &= ~BC_WRITE;
0625     phy_write(phydev, PHYCR2, val);
0626     phy_write(phydev, PAGESEL, init_page);
0627 }
0628 
0629 static void recalibrate(struct dp83640_clock *clock)
0630 {
0631     s64 now, diff;
0632     struct phy_txts event_ts;
0633     struct timespec64 ts;
0634     struct list_head *this;
0635     struct dp83640_private *tmp;
0636     struct phy_device *master = clock->chosen->phydev;
0637     u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
0638 
0639     trigger = CAL_TRIGGER;
0640     cal_gpio = 1 + ptp_find_pin_unlocked(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
0641     if (cal_gpio < 1) {
0642         pr_err("PHY calibration pin not available - PHY is not calibrated.");
0643         return;
0644     }
0645 
0646     mutex_lock(&clock->extreg_lock);
0647 
0648     /*
0649      * enable broadcast, disable status frames, enable ptp clock
0650      */
0651     list_for_each(this, &clock->phylist) {
0652         tmp = list_entry(this, struct dp83640_private, list);
0653         enable_broadcast(tmp->phydev, clock->page, 1);
0654         tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
0655         ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
0656         ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
0657     }
0658     enable_broadcast(master, clock->page, 1);
0659     cfg0 = ext_read(master, PAGE5, PSF_CFG0);
0660     ext_write(0, master, PAGE5, PSF_CFG0, 0);
0661     ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
0662 
0663     /*
0664      * enable an event timestamp
0665      */
0666     evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
0667     evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
0668     evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
0669 
0670     list_for_each(this, &clock->phylist) {
0671         tmp = list_entry(this, struct dp83640_private, list);
0672         ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
0673     }
0674     ext_write(0, master, PAGE5, PTP_EVNT, evnt);
0675 
0676     /*
0677      * configure a trigger
0678      */
0679     ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
0680     ptp_trig |= (trigger  & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
0681     ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
0682     ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
0683 
0684     /* load trigger */
0685     val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
0686     val |= TRIG_LOAD;
0687     ext_write(0, master, PAGE4, PTP_CTL, val);
0688 
0689     /* enable trigger */
0690     val &= ~TRIG_LOAD;
0691     val |= TRIG_EN;
0692     ext_write(0, master, PAGE4, PTP_CTL, val);
0693 
0694     /* disable trigger */
0695     val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
0696     val |= TRIG_DIS;
0697     ext_write(0, master, PAGE4, PTP_CTL, val);
0698 
0699     /*
0700      * read out and correct offsets
0701      */
0702     val = ext_read(master, PAGE4, PTP_STS);
0703     phydev_info(master, "master PTP_STS  0x%04hx\n", val);
0704     val = ext_read(master, PAGE4, PTP_ESTS);
0705     phydev_info(master, "master PTP_ESTS 0x%04hx\n", val);
0706     event_ts.ns_lo  = ext_read(master, PAGE4, PTP_EDATA);
0707     event_ts.ns_hi  = ext_read(master, PAGE4, PTP_EDATA);
0708     event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
0709     event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
0710     now = phy2txts(&event_ts);
0711 
0712     list_for_each(this, &clock->phylist) {
0713         tmp = list_entry(this, struct dp83640_private, list);
0714         val = ext_read(tmp->phydev, PAGE4, PTP_STS);
0715         phydev_info(tmp->phydev, "slave  PTP_STS  0x%04hx\n", val);
0716         val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
0717         phydev_info(tmp->phydev, "slave  PTP_ESTS 0x%04hx\n", val);
0718         event_ts.ns_lo  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
0719         event_ts.ns_hi  = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
0720         event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
0721         event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
0722         diff = now - (s64) phy2txts(&event_ts);
0723         phydev_info(tmp->phydev, "slave offset %lld nanoseconds\n",
0724                 diff);
0725         diff += ADJTIME_FIX;
0726         ts = ns_to_timespec64(diff);
0727         tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
0728     }
0729 
0730     /*
0731      * restore status frames
0732      */
0733     list_for_each(this, &clock->phylist) {
0734         tmp = list_entry(this, struct dp83640_private, list);
0735         ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
0736     }
0737     ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
0738 
0739     mutex_unlock(&clock->extreg_lock);
0740 }
0741 
0742 /* time stamping methods */
0743 
0744 static inline u16 exts_chan_to_edata(int ch)
0745 {
0746     return 1 << ((ch + EXT_EVENT) * 2);
0747 }
0748 
0749 static int decode_evnt(struct dp83640_private *dp83640,
0750                void *data, int len, u16 ests)
0751 {
0752     struct phy_txts *phy_txts;
0753     struct ptp_clock_event event;
0754     int i, parsed;
0755     int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
0756     u16 ext_status = 0;
0757 
0758     /* calculate length of the event timestamp status message */
0759     if (ests & MULT_EVNT)
0760         parsed = (words + 2) * sizeof(u16);
0761     else
0762         parsed = (words + 1) * sizeof(u16);
0763 
0764     /* check if enough data is available */
0765     if (len < parsed)
0766         return len;
0767 
0768     if (ests & MULT_EVNT) {
0769         ext_status = *(u16 *) data;
0770         data += sizeof(ext_status);
0771     }
0772 
0773     phy_txts = data;
0774 
0775     switch (words) {
0776     case 3:
0777         dp83640->edata.sec_hi = phy_txts->sec_hi;
0778         fallthrough;
0779     case 2:
0780         dp83640->edata.sec_lo = phy_txts->sec_lo;
0781         fallthrough;
0782     case 1:
0783         dp83640->edata.ns_hi = phy_txts->ns_hi;
0784         fallthrough;
0785     case 0:
0786         dp83640->edata.ns_lo = phy_txts->ns_lo;
0787     }
0788 
0789     if (!ext_status) {
0790         i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
0791         ext_status = exts_chan_to_edata(i);
0792     }
0793 
0794     event.type = PTP_CLOCK_EXTTS;
0795     event.timestamp = phy2txts(&dp83640->edata);
0796 
0797     /* Compensate for input path and synchronization delays */
0798     event.timestamp -= 35;
0799 
0800     for (i = 0; i < N_EXT_TS; i++) {
0801         if (ext_status & exts_chan_to_edata(i)) {
0802             event.index = i;
0803             ptp_clock_event(dp83640->clock->ptp_clock, &event);
0804         }
0805     }
0806 
0807     return parsed;
0808 }
0809 
0810 #define DP83640_PACKET_HASH_LEN     10
0811 
0812 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
0813 {
0814     struct ptp_header *hdr;
0815     u8 msgtype;
0816     u16 seqid;
0817     u16 hash;
0818 
0819     /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
0820 
0821     hdr = ptp_parse_header(skb, type);
0822     if (!hdr)
0823         return 0;
0824 
0825     msgtype = ptp_get_msgtype(hdr, type);
0826 
0827     if (rxts->msgtype != (msgtype & 0xf))
0828         return 0;
0829 
0830     seqid = be16_to_cpu(hdr->sequence_id);
0831     if (rxts->seqid != seqid)
0832         return 0;
0833 
0834     hash = ether_crc(DP83640_PACKET_HASH_LEN,
0835              (unsigned char *)&hdr->source_port_identity) >> 20;
0836     if (rxts->hash != hash)
0837         return 0;
0838 
0839     return 1;
0840 }
0841 
0842 static void decode_rxts(struct dp83640_private *dp83640,
0843             struct phy_rxts *phy_rxts)
0844 {
0845     struct rxts *rxts;
0846     struct skb_shared_hwtstamps *shhwtstamps = NULL;
0847     struct sk_buff *skb;
0848     unsigned long flags;
0849     u8 overflow;
0850 
0851     overflow = (phy_rxts->ns_hi >> 14) & 0x3;
0852     if (overflow)
0853         pr_debug("rx timestamp queue overflow, count %d\n", overflow);
0854 
0855     spin_lock_irqsave(&dp83640->rx_lock, flags);
0856 
0857     prune_rx_ts(dp83640);
0858 
0859     if (list_empty(&dp83640->rxpool)) {
0860         pr_debug("rx timestamp pool is empty\n");
0861         goto out;
0862     }
0863     rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
0864     list_del_init(&rxts->list);
0865     phy2rxts(phy_rxts, rxts);
0866 
0867     spin_lock(&dp83640->rx_queue.lock);
0868     skb_queue_walk(&dp83640->rx_queue, skb) {
0869         struct dp83640_skb_info *skb_info;
0870 
0871         skb_info = (struct dp83640_skb_info *)skb->cb;
0872         if (match(skb, skb_info->ptp_type, rxts)) {
0873             __skb_unlink(skb, &dp83640->rx_queue);
0874             shhwtstamps = skb_hwtstamps(skb);
0875             memset(shhwtstamps, 0, sizeof(*shhwtstamps));
0876             shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
0877             list_add(&rxts->list, &dp83640->rxpool);
0878             break;
0879         }
0880     }
0881     spin_unlock(&dp83640->rx_queue.lock);
0882 
0883     if (!shhwtstamps)
0884         list_add_tail(&rxts->list, &dp83640->rxts);
0885 out:
0886     spin_unlock_irqrestore(&dp83640->rx_lock, flags);
0887 
0888     if (shhwtstamps)
0889         netif_rx(skb);
0890 }
0891 
0892 static void decode_txts(struct dp83640_private *dp83640,
0893             struct phy_txts *phy_txts)
0894 {
0895     struct skb_shared_hwtstamps shhwtstamps;
0896     struct dp83640_skb_info *skb_info;
0897     struct sk_buff *skb;
0898     u8 overflow;
0899     u64 ns;
0900 
0901     /* We must already have the skb that triggered this. */
0902 again:
0903     skb = skb_dequeue(&dp83640->tx_queue);
0904     if (!skb) {
0905         pr_debug("have timestamp but tx_queue empty\n");
0906         return;
0907     }
0908 
0909     overflow = (phy_txts->ns_hi >> 14) & 0x3;
0910     if (overflow) {
0911         pr_debug("tx timestamp queue overflow, count %d\n", overflow);
0912         while (skb) {
0913             kfree_skb(skb);
0914             skb = skb_dequeue(&dp83640->tx_queue);
0915         }
0916         return;
0917     }
0918     skb_info = (struct dp83640_skb_info *)skb->cb;
0919     if (time_after(jiffies, skb_info->tmo)) {
0920         kfree_skb(skb);
0921         goto again;
0922     }
0923 
0924     ns = phy2txts(phy_txts);
0925     memset(&shhwtstamps, 0, sizeof(shhwtstamps));
0926     shhwtstamps.hwtstamp = ns_to_ktime(ns);
0927     skb_complete_tx_timestamp(skb, &shhwtstamps);
0928 }
0929 
0930 static void decode_status_frame(struct dp83640_private *dp83640,
0931                 struct sk_buff *skb)
0932 {
0933     struct phy_rxts *phy_rxts;
0934     struct phy_txts *phy_txts;
0935     u8 *ptr;
0936     int len, size;
0937     u16 ests, type;
0938 
0939     ptr = skb->data + 2;
0940 
0941     for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
0942 
0943         type = *(u16 *)ptr;
0944         ests = type & 0x0fff;
0945         type = type & 0xf000;
0946         len -= sizeof(type);
0947         ptr += sizeof(type);
0948 
0949         if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
0950 
0951             phy_rxts = (struct phy_rxts *) ptr;
0952             decode_rxts(dp83640, phy_rxts);
0953             size = sizeof(*phy_rxts);
0954 
0955         } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
0956 
0957             phy_txts = (struct phy_txts *) ptr;
0958             decode_txts(dp83640, phy_txts);
0959             size = sizeof(*phy_txts);
0960 
0961         } else if (PSF_EVNT == type) {
0962 
0963             size = decode_evnt(dp83640, ptr, len, ests);
0964 
0965         } else {
0966             size = 0;
0967             break;
0968         }
0969         ptr += size;
0970     }
0971 }
0972 
0973 static void dp83640_free_clocks(void)
0974 {
0975     struct dp83640_clock *clock;
0976     struct list_head *this, *next;
0977 
0978     mutex_lock(&phyter_clocks_lock);
0979 
0980     list_for_each_safe(this, next, &phyter_clocks) {
0981         clock = list_entry(this, struct dp83640_clock, list);
0982         if (!list_empty(&clock->phylist)) {
0983             pr_warn("phy list non-empty while unloading\n");
0984             BUG();
0985         }
0986         list_del(&clock->list);
0987         mutex_destroy(&clock->extreg_lock);
0988         mutex_destroy(&clock->clock_lock);
0989         put_device(&clock->bus->dev);
0990         kfree(clock->caps.pin_config);
0991         kfree(clock);
0992     }
0993 
0994     mutex_unlock(&phyter_clocks_lock);
0995 }
0996 
0997 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
0998 {
0999     INIT_LIST_HEAD(&clock->list);
1000     clock->bus = bus;
1001     mutex_init(&clock->extreg_lock);
1002     mutex_init(&clock->clock_lock);
1003     INIT_LIST_HEAD(&clock->phylist);
1004     clock->caps.owner = THIS_MODULE;
1005     sprintf(clock->caps.name, "dp83640 timer");
1006     clock->caps.max_adj = 1953124;
1007     clock->caps.n_alarm = 0;
1008     clock->caps.n_ext_ts    = N_EXT_TS;
1009     clock->caps.n_per_out   = N_PER_OUT;
1010     clock->caps.n_pins  = DP83640_N_PINS;
1011     clock->caps.pps     = 0;
1012     clock->caps.adjfine = ptp_dp83640_adjfine;
1013     clock->caps.adjtime = ptp_dp83640_adjtime;
1014     clock->caps.gettime64   = ptp_dp83640_gettime;
1015     clock->caps.settime64   = ptp_dp83640_settime;
1016     clock->caps.enable  = ptp_dp83640_enable;
1017     clock->caps.verify  = ptp_dp83640_verify;
1018     /*
1019      * Convert the module param defaults into a dynamic pin configuration.
1020      */
1021     dp83640_gpio_defaults(clock->caps.pin_config);
1022     /*
1023      * Get a reference to this bus instance.
1024      */
1025     get_device(&bus->dev);
1026 }
1027 
1028 static int choose_this_phy(struct dp83640_clock *clock,
1029                struct phy_device *phydev)
1030 {
1031     if (chosen_phy == -1 && !clock->chosen)
1032         return 1;
1033 
1034     if (chosen_phy == phydev->mdio.addr)
1035         return 1;
1036 
1037     return 0;
1038 }
1039 
1040 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1041 {
1042     if (clock)
1043         mutex_lock(&clock->clock_lock);
1044     return clock;
1045 }
1046 
1047 /*
1048  * Look up and lock a clock by bus instance.
1049  * If there is no clock for this bus, then create it first.
1050  */
1051 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1052 {
1053     struct dp83640_clock *clock = NULL, *tmp;
1054     struct list_head *this;
1055 
1056     mutex_lock(&phyter_clocks_lock);
1057 
1058     list_for_each(this, &phyter_clocks) {
1059         tmp = list_entry(this, struct dp83640_clock, list);
1060         if (tmp->bus == bus) {
1061             clock = tmp;
1062             break;
1063         }
1064     }
1065     if (clock)
1066         goto out;
1067 
1068     clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1069     if (!clock)
1070         goto out;
1071 
1072     clock->caps.pin_config = kcalloc(DP83640_N_PINS,
1073                      sizeof(struct ptp_pin_desc),
1074                      GFP_KERNEL);
1075     if (!clock->caps.pin_config) {
1076         kfree(clock);
1077         clock = NULL;
1078         goto out;
1079     }
1080     dp83640_clock_init(clock, bus);
1081     list_add_tail(&clock->list, &phyter_clocks);
1082 out:
1083     mutex_unlock(&phyter_clocks_lock);
1084 
1085     return dp83640_clock_get(clock);
1086 }
1087 
1088 static void dp83640_clock_put(struct dp83640_clock *clock)
1089 {
1090     mutex_unlock(&clock->clock_lock);
1091 }
1092 
1093 static int dp83640_soft_reset(struct phy_device *phydev)
1094 {
1095     int ret;
1096 
1097     ret = genphy_soft_reset(phydev);
1098     if (ret < 0)
1099         return ret;
1100 
1101     /* From DP83640 datasheet: "Software driver code must wait 3 us
1102      * following a software reset before allowing further serial MII
1103      * operations with the DP83640."
1104      */
1105     udelay(10);     /* Taking udelay inaccuracy into account */
1106 
1107     return 0;
1108 }
1109 
1110 static int dp83640_config_init(struct phy_device *phydev)
1111 {
1112     struct dp83640_private *dp83640 = phydev->priv;
1113     struct dp83640_clock *clock = dp83640->clock;
1114 
1115     if (clock->chosen && !list_empty(&clock->phylist))
1116         recalibrate(clock);
1117     else {
1118         mutex_lock(&clock->extreg_lock);
1119         enable_broadcast(phydev, clock->page, 1);
1120         mutex_unlock(&clock->extreg_lock);
1121     }
1122 
1123     enable_status_frames(phydev, true);
1124 
1125     mutex_lock(&clock->extreg_lock);
1126     ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1127     mutex_unlock(&clock->extreg_lock);
1128 
1129     return 0;
1130 }
1131 
1132 static int dp83640_ack_interrupt(struct phy_device *phydev)
1133 {
1134     int err = phy_read(phydev, MII_DP83640_MISR);
1135 
1136     if (err < 0)
1137         return err;
1138 
1139     return 0;
1140 }
1141 
1142 static int dp83640_config_intr(struct phy_device *phydev)
1143 {
1144     int micr;
1145     int misr;
1146     int err;
1147 
1148     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1149         err = dp83640_ack_interrupt(phydev);
1150         if (err)
1151             return err;
1152 
1153         misr = phy_read(phydev, MII_DP83640_MISR);
1154         if (misr < 0)
1155             return misr;
1156         misr |=
1157             (MII_DP83640_MISR_ANC_INT_EN |
1158             MII_DP83640_MISR_DUP_INT_EN |
1159             MII_DP83640_MISR_SPD_INT_EN |
1160             MII_DP83640_MISR_LINK_INT_EN);
1161         err = phy_write(phydev, MII_DP83640_MISR, misr);
1162         if (err < 0)
1163             return err;
1164 
1165         micr = phy_read(phydev, MII_DP83640_MICR);
1166         if (micr < 0)
1167             return micr;
1168         micr |=
1169             (MII_DP83640_MICR_OE |
1170             MII_DP83640_MICR_IE);
1171         return phy_write(phydev, MII_DP83640_MICR, micr);
1172     } else {
1173         micr = phy_read(phydev, MII_DP83640_MICR);
1174         if (micr < 0)
1175             return micr;
1176         micr &=
1177             ~(MII_DP83640_MICR_OE |
1178             MII_DP83640_MICR_IE);
1179         err = phy_write(phydev, MII_DP83640_MICR, micr);
1180         if (err < 0)
1181             return err;
1182 
1183         misr = phy_read(phydev, MII_DP83640_MISR);
1184         if (misr < 0)
1185             return misr;
1186         misr &=
1187             ~(MII_DP83640_MISR_ANC_INT_EN |
1188             MII_DP83640_MISR_DUP_INT_EN |
1189             MII_DP83640_MISR_SPD_INT_EN |
1190             MII_DP83640_MISR_LINK_INT_EN);
1191         err = phy_write(phydev, MII_DP83640_MISR, misr);
1192         if (err)
1193             return err;
1194 
1195         return dp83640_ack_interrupt(phydev);
1196     }
1197 }
1198 
1199 static irqreturn_t dp83640_handle_interrupt(struct phy_device *phydev)
1200 {
1201     int irq_status;
1202 
1203     irq_status = phy_read(phydev, MII_DP83640_MISR);
1204     if (irq_status < 0) {
1205         phy_error(phydev);
1206         return IRQ_NONE;
1207     }
1208 
1209     if (!(irq_status & MII_DP83640_MISR_INT_MASK))
1210         return IRQ_NONE;
1211 
1212     phy_trigger_machine(phydev);
1213 
1214     return IRQ_HANDLED;
1215 }
1216 
1217 static int dp83640_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
1218 {
1219     struct dp83640_private *dp83640 =
1220         container_of(mii_ts, struct dp83640_private, mii_ts);
1221     struct hwtstamp_config cfg;
1222     u16 txcfg0, rxcfg0;
1223 
1224     if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1225         return -EFAULT;
1226 
1227     if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1228         return -ERANGE;
1229 
1230     dp83640->hwts_tx_en = cfg.tx_type;
1231 
1232     switch (cfg.rx_filter) {
1233     case HWTSTAMP_FILTER_NONE:
1234         dp83640->hwts_rx_en = 0;
1235         dp83640->layer = 0;
1236         dp83640->version = 0;
1237         break;
1238     case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1239     case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1240     case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1241         dp83640->hwts_rx_en = 1;
1242         dp83640->layer = PTP_CLASS_L4;
1243         dp83640->version = PTP_CLASS_V1;
1244         cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1245         break;
1246     case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1247     case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1248     case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1249         dp83640->hwts_rx_en = 1;
1250         dp83640->layer = PTP_CLASS_L4;
1251         dp83640->version = PTP_CLASS_V2;
1252         cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
1253         break;
1254     case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1255     case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1256     case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1257         dp83640->hwts_rx_en = 1;
1258         dp83640->layer = PTP_CLASS_L2;
1259         dp83640->version = PTP_CLASS_V2;
1260         cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1261         break;
1262     case HWTSTAMP_FILTER_PTP_V2_EVENT:
1263     case HWTSTAMP_FILTER_PTP_V2_SYNC:
1264     case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1265         dp83640->hwts_rx_en = 1;
1266         dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1267         dp83640->version = PTP_CLASS_V2;
1268         cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1269         break;
1270     default:
1271         return -ERANGE;
1272     }
1273 
1274     txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1275     rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1276 
1277     if (dp83640->layer & PTP_CLASS_L2) {
1278         txcfg0 |= TX_L2_EN;
1279         rxcfg0 |= RX_L2_EN;
1280     }
1281     if (dp83640->layer & PTP_CLASS_L4) {
1282         txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1283         rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1284     }
1285 
1286     if (dp83640->hwts_tx_en)
1287         txcfg0 |= TX_TS_EN;
1288 
1289     if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1290         txcfg0 |= SYNC_1STEP | CHK_1STEP;
1291 
1292     if (dp83640->hwts_rx_en)
1293         rxcfg0 |= RX_TS_EN;
1294 
1295     mutex_lock(&dp83640->clock->extreg_lock);
1296 
1297     ext_write(0, dp83640->phydev, PAGE5, PTP_TXCFG0, txcfg0);
1298     ext_write(0, dp83640->phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1299 
1300     mutex_unlock(&dp83640->clock->extreg_lock);
1301 
1302     return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1303 }
1304 
1305 static void rx_timestamp_work(struct work_struct *work)
1306 {
1307     struct dp83640_private *dp83640 =
1308         container_of(work, struct dp83640_private, ts_work.work);
1309     struct sk_buff *skb;
1310 
1311     /* Deliver expired packets. */
1312     while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1313         struct dp83640_skb_info *skb_info;
1314 
1315         skb_info = (struct dp83640_skb_info *)skb->cb;
1316         if (!time_after(jiffies, skb_info->tmo)) {
1317             skb_queue_head(&dp83640->rx_queue, skb);
1318             break;
1319         }
1320 
1321         netif_rx(skb);
1322     }
1323 
1324     if (!skb_queue_empty(&dp83640->rx_queue))
1325         schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1326 }
1327 
1328 static bool dp83640_rxtstamp(struct mii_timestamper *mii_ts,
1329                  struct sk_buff *skb, int type)
1330 {
1331     struct dp83640_private *dp83640 =
1332         container_of(mii_ts, struct dp83640_private, mii_ts);
1333     struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1334     struct list_head *this, *next;
1335     struct rxts *rxts;
1336     struct skb_shared_hwtstamps *shhwtstamps = NULL;
1337     unsigned long flags;
1338 
1339     if (is_status_frame(skb, type)) {
1340         decode_status_frame(dp83640, skb);
1341         kfree_skb(skb);
1342         return true;
1343     }
1344 
1345     if (!dp83640->hwts_rx_en)
1346         return false;
1347 
1348     if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1349         return false;
1350 
1351     spin_lock_irqsave(&dp83640->rx_lock, flags);
1352     prune_rx_ts(dp83640);
1353     list_for_each_safe(this, next, &dp83640->rxts) {
1354         rxts = list_entry(this, struct rxts, list);
1355         if (match(skb, type, rxts)) {
1356             shhwtstamps = skb_hwtstamps(skb);
1357             memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1358             shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1359             list_del_init(&rxts->list);
1360             list_add(&rxts->list, &dp83640->rxpool);
1361             break;
1362         }
1363     }
1364     spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1365 
1366     if (!shhwtstamps) {
1367         skb_info->ptp_type = type;
1368         skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1369         skb_queue_tail(&dp83640->rx_queue, skb);
1370         schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1371     } else {
1372         netif_rx(skb);
1373     }
1374 
1375     return true;
1376 }
1377 
1378 static void dp83640_txtstamp(struct mii_timestamper *mii_ts,
1379                  struct sk_buff *skb, int type)
1380 {
1381     struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1382     struct dp83640_private *dp83640 =
1383         container_of(mii_ts, struct dp83640_private, mii_ts);
1384 
1385     switch (dp83640->hwts_tx_en) {
1386 
1387     case HWTSTAMP_TX_ONESTEP_SYNC:
1388         if (ptp_msg_is_sync(skb, type)) {
1389             kfree_skb(skb);
1390             return;
1391         }
1392         fallthrough;
1393     case HWTSTAMP_TX_ON:
1394         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1395         skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1396         skb_queue_tail(&dp83640->tx_queue, skb);
1397         break;
1398 
1399     case HWTSTAMP_TX_OFF:
1400     default:
1401         kfree_skb(skb);
1402         break;
1403     }
1404 }
1405 
1406 static int dp83640_ts_info(struct mii_timestamper *mii_ts,
1407                struct ethtool_ts_info *info)
1408 {
1409     struct dp83640_private *dp83640 =
1410         container_of(mii_ts, struct dp83640_private, mii_ts);
1411 
1412     info->so_timestamping =
1413         SOF_TIMESTAMPING_TX_HARDWARE |
1414         SOF_TIMESTAMPING_RX_HARDWARE |
1415         SOF_TIMESTAMPING_RAW_HARDWARE;
1416     info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1417     info->tx_types =
1418         (1 << HWTSTAMP_TX_OFF) |
1419         (1 << HWTSTAMP_TX_ON) |
1420         (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1421     info->rx_filters =
1422         (1 << HWTSTAMP_FILTER_NONE) |
1423         (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1424         (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1425         (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1426         (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1427     return 0;
1428 }
1429 
1430 static int dp83640_probe(struct phy_device *phydev)
1431 {
1432     struct dp83640_clock *clock;
1433     struct dp83640_private *dp83640;
1434     int err = -ENOMEM, i;
1435 
1436     if (phydev->mdio.addr == BROADCAST_ADDR)
1437         return 0;
1438 
1439     clock = dp83640_clock_get_bus(phydev->mdio.bus);
1440     if (!clock)
1441         goto no_clock;
1442 
1443     dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1444     if (!dp83640)
1445         goto no_memory;
1446 
1447     dp83640->phydev = phydev;
1448     dp83640->mii_ts.rxtstamp = dp83640_rxtstamp;
1449     dp83640->mii_ts.txtstamp = dp83640_txtstamp;
1450     dp83640->mii_ts.hwtstamp = dp83640_hwtstamp;
1451     dp83640->mii_ts.ts_info  = dp83640_ts_info;
1452 
1453     INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1454     INIT_LIST_HEAD(&dp83640->rxts);
1455     INIT_LIST_HEAD(&dp83640->rxpool);
1456     for (i = 0; i < MAX_RXTS; i++)
1457         list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1458 
1459     phydev->mii_ts = &dp83640->mii_ts;
1460     phydev->priv = dp83640;
1461 
1462     spin_lock_init(&dp83640->rx_lock);
1463     skb_queue_head_init(&dp83640->rx_queue);
1464     skb_queue_head_init(&dp83640->tx_queue);
1465 
1466     dp83640->clock = clock;
1467 
1468     if (choose_this_phy(clock, phydev)) {
1469         clock->chosen = dp83640;
1470         clock->ptp_clock = ptp_clock_register(&clock->caps,
1471                               &phydev->mdio.dev);
1472         if (IS_ERR(clock->ptp_clock)) {
1473             err = PTR_ERR(clock->ptp_clock);
1474             goto no_register;
1475         }
1476     } else
1477         list_add_tail(&dp83640->list, &clock->phylist);
1478 
1479     dp83640_clock_put(clock);
1480     return 0;
1481 
1482 no_register:
1483     clock->chosen = NULL;
1484     kfree(dp83640);
1485 no_memory:
1486     dp83640_clock_put(clock);
1487 no_clock:
1488     return err;
1489 }
1490 
1491 static void dp83640_remove(struct phy_device *phydev)
1492 {
1493     struct dp83640_clock *clock;
1494     struct list_head *this, *next;
1495     struct dp83640_private *tmp, *dp83640 = phydev->priv;
1496 
1497     if (phydev->mdio.addr == BROADCAST_ADDR)
1498         return;
1499 
1500     phydev->mii_ts = NULL;
1501 
1502     enable_status_frames(phydev, false);
1503     cancel_delayed_work_sync(&dp83640->ts_work);
1504 
1505     skb_queue_purge(&dp83640->rx_queue);
1506     skb_queue_purge(&dp83640->tx_queue);
1507 
1508     clock = dp83640_clock_get(dp83640->clock);
1509 
1510     if (dp83640 == clock->chosen) {
1511         ptp_clock_unregister(clock->ptp_clock);
1512         clock->chosen = NULL;
1513     } else {
1514         list_for_each_safe(this, next, &clock->phylist) {
1515             tmp = list_entry(this, struct dp83640_private, list);
1516             if (tmp == dp83640) {
1517                 list_del_init(&tmp->list);
1518                 break;
1519             }
1520         }
1521     }
1522 
1523     dp83640_clock_put(clock);
1524     kfree(dp83640);
1525 }
1526 
1527 static struct phy_driver dp83640_driver = {
1528     .phy_id     = DP83640_PHY_ID,
1529     .phy_id_mask    = 0xfffffff0,
1530     .name       = "NatSemi DP83640",
1531     /* PHY_BASIC_FEATURES */
1532     .probe      = dp83640_probe,
1533     .remove     = dp83640_remove,
1534     .soft_reset = dp83640_soft_reset,
1535     .config_init    = dp83640_config_init,
1536     .config_intr    = dp83640_config_intr,
1537     .handle_interrupt = dp83640_handle_interrupt,
1538 };
1539 
1540 static int __init dp83640_init(void)
1541 {
1542     return phy_driver_register(&dp83640_driver, THIS_MODULE);
1543 }
1544 
1545 static void __exit dp83640_exit(void)
1546 {
1547     dp83640_free_clocks();
1548     phy_driver_unregister(&dp83640_driver);
1549 }
1550 
1551 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1552 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1553 MODULE_LICENSE("GPL");
1554 
1555 module_init(dp83640_init);
1556 module_exit(dp83640_exit);
1557 
1558 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1559     { DP83640_PHY_ID, 0xfffffff0 },
1560     { }
1561 };
1562 
1563 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
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