net/phy/bcm63xx.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  *  Driver for Broadcom 63xx SOCs integrated PHYs
0004  */
0005 #include "bcm-phy-lib.h"
0006 #include <linux/module.h>
0007 #include <linux/phy.h>
0008
0009 #define MII_BCM63XX_IR      0x1a    /* interrupt register */
0010 #define MII_BCM63XX_IR_EN   0x4000  /* global interrupt enable */
0011 #define MII_BCM63XX_IR_DUPLEX   0x0800  /* duplex changed */
0012 #define MII_BCM63XX_IR_SPEED    0x0400  /* speed changed */
0013 #define MII_BCM63XX_IR_LINK 0x0200  /* link changed */
0014 #define MII_BCM63XX_IR_GMASK    0x0100  /* global interrupt mask */
0015
0016 MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver");
0017 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
0018 MODULE_LICENSE("GPL");
0019
0020 static int bcm63xx_config_intr(struct phy_device *phydev)
0021 {
0022     int reg, err;
0023
0024     reg = phy_read(phydev, MII_BCM63XX_IR);
0025     if (reg < 0)
0026         return reg;
0027
0028     if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
0029         err = bcm_phy_ack_intr(phydev);
0030         if (err)
0031             return err;
0032
0033         reg &= ~MII_BCM63XX_IR_GMASK;
0034         err = phy_write(phydev, MII_BCM63XX_IR, reg);
0035     } else {
0036         reg |= MII_BCM63XX_IR_GMASK;
0037         err = phy_write(phydev, MII_BCM63XX_IR, reg);
0038         if (err)
0039             return err;
0040
0041         err = bcm_phy_ack_intr(phydev);
0042     }
0043
0044     return err;
0045 }
0046
0047 static int bcm63xx_config_init(struct phy_device *phydev)
0048 {
0049     int reg, err;
0050
0051     /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */
0052     linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
0053
0054     reg = phy_read(phydev, MII_BCM63XX_IR);
0055     if (reg < 0)
0056         return reg;
0057
0058     /* Mask interrupts globally.  */
0059     reg |= MII_BCM63XX_IR_GMASK;
0060     err = phy_write(phydev, MII_BCM63XX_IR, reg);
0061     if (err < 0)
0062         return err;
0063
0064     /* Unmask events we are interested in  */
0065     reg = ~(MII_BCM63XX_IR_DUPLEX |
0066         MII_BCM63XX_IR_SPEED |
0067         MII_BCM63XX_IR_LINK) |
0068         MII_BCM63XX_IR_EN;
0069     return phy_write(phydev, MII_BCM63XX_IR, reg);
0070 }
0071
0072 static struct phy_driver bcm63xx_driver[] = {
0073 {
0074     .phy_id     = 0x00406000,
0075     .phy_id_mask    = 0xfffffc00,
0076     .name       = "Broadcom BCM63XX (1)",
0077     /* PHY_BASIC_FEATURES */
0078     .flags      = PHY_IS_INTERNAL,
0079     .config_init    = bcm63xx_config_init,
0080     .config_intr    = bcm63xx_config_intr,
0081     .handle_interrupt = bcm_phy_handle_interrupt,
0082 }, {
0083     /* same phy as above, with just a different OUI */
0084     .phy_id     = 0x002bdc00,
0085     .phy_id_mask    = 0xfffffc00,
0086     .name       = "Broadcom BCM63XX (2)",
0087     /* PHY_BASIC_FEATURES */
0088     .flags      = PHY_IS_INTERNAL,
0089     .config_init    = bcm63xx_config_init,
0090     .config_intr    = bcm63xx_config_intr,
0091     .handle_interrupt = bcm_phy_handle_interrupt,
0092 } };
0093
0094 module_phy_driver(bcm63xx_driver);
0095
0096 static struct mdio_device_id __maybe_unused bcm63xx_tbl[] = {
0097     { 0x00406000, 0xfffffc00 },
0098     { 0x002bdc00, 0xfffffc00 },
0099     { }
0100 };
0101
0102 MODULE_DEVICE_TABLE(mdio, bcm63xx_tbl);